CN115935878B - Multi-bit data calculating circuit, chip and calculating device based on analog signals - Google Patents
Multi-bit data calculating circuit, chip and calculating device based on analog signals Download PDFInfo
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Abstract
The embodiment of the disclosure discloses a multi-bit data calculating circuit, a chip and a calculating device based on analog signals, wherein the circuit comprises: a preset number of calculation unit groups and a preset number of addition unit groups; for each of a preset number of computing unit groups, the computing unit group corresponds to a target adding unit group and has a corresponding accumulating weight, and the output end of each computing unit is connected with the input end of the corresponding adding unit; the target addition unit group is used for distributing corresponding digital weights to each calculation unit in the calculation unit group, accumulating calculation result signals output by each calculation unit according to the corresponding digital weights, and outputting accumulated result signals through a signal output end of the addition unit group; the preset number of addition unit groups each include different proportional relationships of characteristic metric values of respective addition units. Embodiments of the present disclosure help reduce the area and power consumption of the overall computing circuit.
Description
Technical Field
The present disclosure relates to the field of integrated circuit design technologies, and in particular, to a multi-bit data computing circuit, a chip and a computing device based on analog signals.
Background
The integrated memory-calculation array based on the analog signal domain plays an important role in multiply-accumulate (MAC, multiply Accumulate) operation, the calculation mode is commonly applied to a deep neural network algorithm and used for executing intensive multiply-accumulate operation, and the calculation mode has the advantages of high parallelism and low power consumption. The signals of the analog signal domain comprise a current domain, a charge domain, a time domain and the like. The current analog signal commonly used in the integrated memory array is a charge domain signal, because the processing precision of the capacitor in the integrated circuit is higher, and compared with other two analog signals, the charge domain calculation method realized by using the capacitor has better linearity.
According to the currently adopted charge domain multiplication accumulation scheme comprising capacitors, the capacitance values of a plurality of capacitors corresponding to each single-bit storage data (for example, one bit in weight data in a neural network scene) are distributed according to a proportion relation of 1:2:4:8 … …, so that the superposition of products is realized according to corresponding weights after the multiplication of the same single-bit storage data and each single bit of multi-bit input data is realized according to the principle of capacitive voltage division.
Disclosure of Invention
Embodiments of the present disclosure provide a multi-bit data calculation circuit based on an analog signal, the circuit comprising: a preset number of calculation unit groups and a preset number of addition unit groups; for each of a preset number of computing unit groups, the computing unit group corresponds to a target adding unit group and has a corresponding accumulating weight, and the output end of each computing unit in the computing unit group is connected with the input end of the corresponding adding unit; the target addition unit group is used for distributing corresponding digital weights to each calculation unit in the calculation unit group, accumulating calculation result signals output by each calculation unit according to the corresponding digital weights, and outputting accumulated result signals through a signal output end of the addition unit group, wherein the digital weights corresponding to each calculation unit are determined based on characteristic metric values and accumulated weights of each addition unit in the target addition unit group; the preset number of addition unit groups each include different proportional relationships of characteristic metric values of respective addition units.
In some embodiments, the circuit further includes a preset number of analog-to-digital converters, a shift accumulator, wherein each of the preset number of analog-to-digital converters corresponds to one addition unit group; each analog-to-digital converter in the preset number of analog-to-digital converters is used for receiving the accumulated result signals output by the corresponding addition unit group, generating digital signals according to the received accumulated result signals, and sending the obtained digital signals to the shift accumulator; and the shift accumulator is used for carrying out shift accumulation operation on the received second preset number of digital signals according to the corresponding accumulation weights respectively to obtain multi-bit accumulation result data.
In some embodiments, for a calculation unit group of a preset number of calculation unit groups, each calculation unit included in the calculation unit group corresponds to one storage unit, the storage unit is used for storing single-bit storage data, each calculation unit is used for calculating single-bit data in the corresponding storage unit and input single-bit input data, and a calculation result signal is input to the corresponding addition unit.
In some embodiments, the computing unit groups in the preset number of computing unit groups are formed by multipliers, and the multipliers are used for multiplying the single-bit stored data in the corresponding storage units and the input single-bit input data and outputting a computing result signal.
In some embodiments, the multiplier includes a first switch for outputting the input single-bit input data as the calculation result signal when the single-bit stored data in the storage unit corresponding to the multiplier is the first data, and a second switch for outputting the preset level as the calculation result signal when the single-bit stored data in the storage unit corresponding to the multiplier is the second data.
In some embodiments, for an addition unit group of the preset number of addition unit groups, an addition unit included in the addition unit group is a capacitance value of a capacitor, and a characteristic metric value of the addition unit is the capacitance value; alternatively, the summing unit group includes a transistor, and the characteristic metric value of the summing unit is a transconductance parameter of the transistor.
In some embodiments, for an addition unit group of the preset number of addition unit groups, if the addition unit group is composed of capacitors, the accumulation result signal output by the addition unit group is a voltage signal, and the analog-to-digital converter corresponding to the addition unit group is used for converting the voltage signal into a digital signal; if the adding unit group consists of transistors, the accumulated result signal output by the adding unit group is a current signal, and the analog-to-digital converter corresponding to the adding unit group is used for converting the current signal into a digital signal.
According to another aspect of an embodiment of the present disclosure, there is provided a chip including the above-described multi-bit data calculation circuit based on an analog signal.
According to another aspect of embodiments of the present disclosure, there is provided a computing device comprising the chip described above.
According to the multi-bit data calculating circuit, the chip and the calculating device based on the analog signals, a preset number of calculating unit groups and a preset number of adding unit groups are arranged in the circuit, each calculating unit group corresponds to one adding unit group, the adding unit groups distribute corresponding digital weights to each calculating unit in the corresponding calculating unit groups, the calculating result signals output by each calculating unit are accumulated according to the corresponding digital weights, the accumulated result signals are output through a signal output end, the digital weights corresponding to each calculating unit are determined based on the characteristic metric value and the accumulated weight of each adding unit in the corresponding adding unit group, and the proportional relation of the characteristic metric values of all adding units included in each adding unit group in the preset number of adding unit groups is different. Compared with the existing multi-bit data multiply-accumulate circuit based on analog signals, the embodiment of the disclosure does not need to enable all the adding units in each adding unit group to be distributed according to the same proportion relation, reduces the sum of special metric values of the adding units on the basis of realizing calculation and accumulation of multi-bit storage data and multi-bit input data, avoids the problem that the characteristic metric values of the adding units are exponentially increased along with the increase of bit width of calculation data, and is further beneficial to reducing the area and power consumption of the whole calculating circuit.
The technical scheme of the present disclosure is described in further detail below through the accompanying drawings and examples.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent by describing embodiments thereof in more detail with reference to the accompanying drawings. The accompanying drawings are included to provide a further understanding of embodiments of the disclosure, and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure, without limitation to the disclosure. In the drawings, like reference numerals generally refer to like parts or steps;
FIG. 1 is a schematic diagram of a prior art analog signal based multi-bit data multiply-accumulate circuit;
FIG. 2 is a schematic diagram of an analog signal based multi-bit data computation circuit provided in an exemplary embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a calculation rule for multiplying four-bit stored data and four-bit input data provided by an exemplary embodiment of the present disclosure;
FIG. 4 is another schematic diagram of an analog signal based multi-bit data computation circuit provided in an exemplary embodiment of the present disclosure;
FIG. 5 is another schematic diagram of an analog signal based multi-bit data computation circuit provided in an exemplary embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a connection relationship between a storage unit, a calculation unit, and an addition unit provided in an exemplary embodiment of the present disclosure;
FIG. 7 is a schematic diagram of a multiplication unit provided by an exemplary embodiment of the present disclosure;
fig. 8 is another schematic diagram of a multi-bit data calculation circuit based on analog signals according to an exemplary embodiment of the present disclosure.
Detailed Description
Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present disclosure and not all of the embodiments of the present disclosure, and that the present disclosure is not limited by the example embodiments described herein.
It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise.
It will be appreciated by those of skill in the art that the terms "first," "second," etc. in embodiments of the present disclosure are used merely to distinguish between different steps, devices or modules, etc., and do not represent any particular technical meaning nor necessarily logical order between them.
It should also be understood that in embodiments of the present disclosure, "plurality" may refer to two or more, and "at least one" may refer to one, two or more.
It should also be appreciated that any component, data, or structure referred to in the presently disclosed embodiments may be generally understood as one or more without explicit limitation or the contrary in the context.
In addition, the term "and/or" in this disclosure is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the front and rear association objects are an or relationship.
It should also be understood that the description of the various embodiments of the present disclosure emphasizes the differences between the various embodiments, and that the same or similar features may be referred to each other, and for brevity, will not be described in detail.
Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.
Fig. 1 shows an exemplary schematic diagram of a present analog signal-based multiply-accumulate circuit. As shown in FIG. 1, the K four-bit weight data and the four-bit input data are multiplied and accumulated, and SRAM (Static Random-Access Memory) units in the figure storeSingle bit weight data W i [3:0]I is a row number. The same column stores weight data of the same bit number, and multiplication and addition results of different columns have different digital weights (meeting the binary proportional relation of 1:1/2:1/4:1/8).
The multiplication unit in the figure is used for realizing the input data I i [3:0]And weight data W i [3:0]Is a multiplication of (a) by (b). The output end of each multiplication unit is connected with a capacitor, and the capacity value meets the binary scale relationship, so that the weight relationship of input data is realized. For example, for four-bit input data, the capacitance ratio of the capacitors corresponding to the four capacitors is 8:4:2:1, and according to the principle of capacitive voltage division, the arrangement of the capacitors can make the multiplication and addition result be expressed as I i [3]×W×8/16+ I i [2]×W×4/16+ I i [1]×W×2/16+ I i [0]XW is multiplied by 1/16, thereby realizing that the multiplication results are accumulated according to weights respectively corresponding to the four-bit data. The capacitor not connected to the multiplication unit is a virtual (Dummy) capacitor, and the capacitor is used to cooperate with other capacitors to adjust the digital weight.
As can be seen from fig. 1, the current multiply-accumulate operation circuit based on analog signals has the following disadvantages:
1. the binary proportional relation of the capacitor is utilized to realize the weight of multi-bit input data, so that the problem of exponential increase of capacitance value of the capacitor can be faced when the input of high bit width is processed, and the bit width of the input data is limited.
2. The total capacitance value of the capacitor is larger, so that the area and the power consumption of the calculation array are increased, and the area efficiency and the energy efficiency of the storage and calculation integrated array are reduced. Taking the four-bit data operation of fig. 1 as an example, when four-bit data multiplication is implemented in each row, the required capacitance is 4× (8c+4c+2c+1c) =7c (capacitance value of unit capacitance).
The embodiment of the disclosure aims to solve the above problems, and proposes a multi-bit data computing circuit based on analog signals, where each adding unit group (i.e., a plurality of adding units corresponding to single-bit stored data) of the circuit includes different proportional relationships of characteristic metric values of each adding unit, for example, when four-bit data is computed and accumulated, each adding unit group is not required to be distributed according to the proportional relationship of 8:4:2:1, so that the problem of exponential increase of the characteristic metric values during high-bit wide data computation is solved, and the area utilization efficiency and the energy utilization efficiency of the circuit are improved.
Exemplary Structure
Fig. 2 is a schematic diagram of a multi-bit data calculation circuit based on analog signals according to an exemplary embodiment of the present disclosure. The individual components of the circuit may be integrated into one chip or may be provided in different chips or circuit boards, between which links for data communication are established.
As shown in fig. 2, the circuit includes: a preset number of groups of computing units (including 201, 203, 205, 207, 209) and a preset number of groups of adding units (including 202, 204, 206, 208, 210). Wherein each computing unit group corresponds to one adding unit group. The preset number may be set as desired. As shown in FIG. 2, data I is input for four bits i [3:0]And four bits of storage data W i [3:0]When multiplication is performed, the number of required computing units is 16, the 16 computing units and the corresponding adding units are divided into 5 columns, and the plurality of computing units and the plurality of adding units included in each column are respectively a corresponding computing unit group and an adding unit group, namely, the preset number is 5.
The calculation units included in the calculation unit group may perform any type of calculation as needed. For example, the calculation unit may be a multiplier for multiplying the input single-bit input data and the single-bit stored data. Alternatively, the calculation unit may also perform addition, exclusive or, exclusive nor, etc. calculations.
The addition unit group is used for accumulating the calculation result signals output by the corresponding calculation units in the analog signal domain. The summing unit included in the summing unit group may be formed of any type of device, as shown in fig. 2, the summing unit being a capacitor.
It should be noted that, the number of the computing units and the number of the adding units included in the corresponding computing unit groups and the corresponding adding units may be the same or different, as shown in fig. 2, in order to assign weights to the computing result signals of the computing unit groups, virtual capacitances may be added, that is, capacitances of one end connected to the ground and the other end connected to the signal output end shown in the drawing.
In this embodiment, for each of a preset number of calculation unit groups, the calculation unit group corresponds to a target addition unit group and has a corresponding accumulation weight, and an output end of each calculation unit in the calculation unit group is connected to an input end of a corresponding addition unit.
The target addition unit group is one addition unit group of a preset number of addition unit groups, as shown in fig. 2, and for the calculation unit group 201, the corresponding target addition unit group is 202. The corresponding accumulation weight of the calculation unit group refers to that after the corresponding addition unit group outputs the accumulation result signal, the data represented by the accumulation result signal is multiplied by the corresponding accumulation weight, so that the accumulation data corresponding to the calculation unit group can be obtained.
As shown in FIG. 2, the five computing unit groups respectively correspond to the accumulation weights of 1, 1/2, 1/4, 1/8 and 1/16. It should be noted that, the accumulation weights shown in fig. 2 are relative weights, that is, the accumulation weights corresponding to the signal output ends of two adjacent addition unit groups respectively satisfy a 2-time relationship, and in the analog-digital converter and the shift accumulator, absolute weights can be set according to actual needs, so as to complete calculation of an actual scene.
The target addition unit group is used for distributing corresponding digital weights to each calculation unit in the corresponding calculation unit group, accumulating calculation result signals output by each calculation unit according to the corresponding digital weights, and outputting accumulated result signals through a signal output end of the addition unit group, wherein the digital weights corresponding to each calculation unit are determined based on characteristic metric values and accumulated weights of each addition unit in the target addition unit group.
As an example, when the adding unit is a capacitor as shown in fig. 2, the characteristic metric value of the adding unit is the capacitance value of the capacitor, and 1C, 2C, etc. shown in fig. 2 represent the capacitance value of the capacitor. For one of the computing units in a certain computing unit group, its corresponding digital weight is determined by the ratio of the capacitance value of the capacitor connected thereto to the total capacitance value of the corresponding adding unit group. For example, for the calculation unit 2011 in the calculation unit group 201 in fig. 2, the corresponding digital weight is 8C/(8c+4c+2c+1c) =1/2, and for the calculation unit 2012 in fig. 2, the corresponding digital weight is 4C/(8c+4c+2c+1c+1c) =1/4.
In the present embodiment, the proportional relationship of the characteristic metric values of the respective addition units included in each of the preset number of addition unit groups is different.
As shown in fig. 2, for the adding unit group 202, the ratio of the characteristic metric values of the adding units is 8:4:2:1:1, and for the adding unit group 204, the ratio of the characteristic metric values of the adding units is 2:1:1. Similarly, the proportional relationship of the characteristic metric values of each addition unit in the other addition unit groups is 1:1:1:1, 1:1:1, and 2:2:1:3 respectively.
In contrast to the conventional analog signal based multiply-accumulate computing circuit shown in fig. 1, each column also includes a computing unit group (formed by multiplication units) and an adding unit group (formed by capacitors), and the proportional relationships of the characteristic metric values of the adding units in the adding unit group shown in fig. 1 are equal and are all 8:4:2:1:1. The total characteristic metric value of the addition unit required for the circuit shown in fig. 1 is 4× (8c+4c+2c+1c+1c) =64c. In the present embodiment, by reorganizing the positions of the calculation unit and the addition unit and reassigning the proportional relation of the respective addition unit groups, the total characteristic metric value of the circuit provided in the present embodiment as shown in fig. 2 is (8c+4c+2c+1c+1c) + (2c+1c+1c+1c+1c) + (1c+1c+1c) + (2c+2c+1c+3c) =36c, and the total characteristic metric value is greatly reduced compared with the circuit shown in fig. 1.
Next, the principle of assigning capacitance values of the respective capacitances in the circuit shown in fig. 2 will be described based on the principle of multiplying four-bit input data and four-bit weight data. As shown in fig. 3, which shows four bits of storage data W i [3:0]And four bits of input data I i [3:0]And (3) a calculation rule of multiplication. Each column of values shown in fig. 3 (i.e.Single bit product) corresponds to a product weight, W i [3:0]And I i [3:0]The final product is obtained by multiplying each single-bit product by the corresponding product weight and adding the products. The corresponding product weight for each single bit product shown in fig. 3 is equal to the digital weight of the corresponding addition unit in fig. 2 multiplied by the corresponding accumulation weight.
For example, for I i [3]*W i [3]The corresponding digital weight is 1/2, the corresponding accumulated weight is 1, and the corresponding product weight is 1/2;
for I i [2]*W i [2]The corresponding digital weight is 1/4, the corresponding accumulated weight is 1/2, and the corresponding product weight is 1/8;
for I i [1]*W i [1]The corresponding digital weight is 1/4, the corresponding accumulated weight is 1/8, and the corresponding product weight is 1/16.
It should be noted that the distribution of the calculation units and the addition units shown in fig. 2 is merely an example, and alternatively, the distribution of the calculation units and the addition units may be adjusted as needed when the multi-bit data multiplication calculation satisfies the multi-bit calculation rule shown in fig. 3 and the columns shown in fig. 3 are arranged in a binary manner. For example, I in FIG. 2 may be i [0]、W i [3]The corresponding calculation units and capacitors can be arranged in the third column (i.e. column with accumulated weight of 1/4), and the virtual capacitor grounded in the third column is deleted, and the capacitance value of the virtual capacitor grounded in the first column is set to 2C, then I i [0]、W i [3]The corresponding product weight is still 1/4 x 1/4=1/16.
The circuit provided in the foregoing embodiment of the present disclosure sets a preset number of calculation unit groups and a preset number of addition unit groups, each calculation unit group corresponds to one addition unit group, the addition unit groups allocate a corresponding digital weight to each calculation unit in the corresponding calculation unit group, accumulate calculation result signals output by each calculation unit according to the corresponding digital weight, output the accumulated result signals through a signal output terminal, the digital weight corresponding to each calculation unit is determined based on a characteristic metric value and an accumulated weight of each addition unit in the corresponding addition unit group, and a proportional relationship of characteristic metric values of respective addition units included in each addition unit group in the preset number of addition unit groups is different. Compared with the existing multi-bit data multiply-accumulate circuit based on analog signals, the embodiment of the disclosure does not need to enable all the adding units in each adding unit group to be distributed according to the same proportion relation, reduces the sum of special metric values of the adding units on the basis of realizing calculation and accumulation of multi-bit storage data and multi-bit input data, avoids the problem that the characteristic metric values of the adding units are exponentially increased along with the increase of bit width of calculation data, and is further beneficial to reducing the area and power consumption of the whole calculating circuit.
In some alternative implementations, as shown in fig. 4, the circuit further includes a preset number of analog-to-digital converters 211, a shift accumulator 212. Wherein, each of the preset number of analog-to-digital converters 211 corresponds to one addition unit group.
Each of the preset number of analog-to-digital converters 211 is configured to receive the accumulation result signal output by the corresponding addition unit group, generate a digital signal according to the received accumulation result signal, and send the obtained digital signal to the shift accumulator 212.
The shift accumulator 212 is configured to perform shift accumulation operation on the received second preset number of digital signals according to the corresponding accumulation weights, so as to obtain multi-bit accumulation result data.
As an example, as shown in fig. 2, for the accumulation result signal output by the addition unit group 202, which represents accumulation of the calculation result (for example, multiplication calculation result) output by each calculation unit in the calculation unit group 201, the corresponding analog-to-digital converter may convert the analog signal into a digital signal.
Each digital signal corresponds to an accumulation weight, and according to the calculation rule of the multi-bit multiplication shown in fig. 3, the shift accumulator 104 can multiply (e.g. byOvershift implementation), and then adding the products to obtain the product of a multi-bit input data and a multi-bit stored data. For example, the multi-bit accumulated result data shown in FIG. 2 is I i [3:0]*W i [3:0]Is a product of (a) and (b).
According to the embodiment, through the arrangement of the analog-to-digital converter and the shift accumulator, the accumulated result signals of the analog signal domains output by each addition unit group are converted into digital signals, and the digital signals are accumulated according to the corresponding accumulated weights to obtain multi-bit accumulated result signals of the digital signal domains, so that further processing of the multi-bit accumulated result signals of the digital signal domains is facilitated, and the application field of the multi-bit data computing circuit is expanded.
Alternatively, as shown in fig. 5, the circuits shown in fig. 2 may be arranged into a plurality of groups, and according to the circuits shown in fig. 5, a plurality of calculation unit groups and addition unit groups corresponding to the same accumulation weight are arranged into the same column, and the output ends of all the addition unit groups of the column are connected to the same accumulation line, so that calculation and accumulation of a plurality of multi-bit input data and multi-bit storage data are realized.
As shown in fig. 5, the accumulation result signals output by the same accumulation line represent the accumulation of the calculation results output by k+1 calculation unit groups, the accumulation result signals output by each accumulation line are input to the corresponding analog-to-digital converter to obtain digital signals, the digital signals are input to the shift accumulator, the shift accumulator calculates multiple multi-bit accumulation result data of multiple multi-bit input data and multiple-bit storage data according to the corresponding accumulation weights, i.e. when the calculation units are used for executing single-bit multiplication calculation, the multi-bit accumulation result data output by the circuit shown in fig. 5 is W 0 [3:0]* I 0 [3:0]+ W 1 [3:0]* I 1 [3:0]+…+ W K [3:0]* I K [3:0]。
The circuit shown in fig. 5 can be applied to a memory integrated array, so that calculation of a plurality of multi-bit data is realized, and the area and the power consumption of the memory integrated array are reduced.
In some optional implementations, for a computing unit group in the preset number of computing unit groups, each computing unit included in the computing unit group corresponds to one storage unit, the storage unit is used for storing single-bit storage data, each computing unit is used for computing single-bit data in the corresponding storage unit and input single-bit input data, and a computing result signal is input to the corresponding addition unit.
As shown in FIG. 6, one input of the computing unit is connected to a memory unit for storing one single bit of stored data, e.g., W i [0]The other input of the computing unit is for receiving a single bit of input data, e.g. I i [0]The calculation unit outputs a calculation result signal to the addition unit.
In this embodiment, the memory unit and the computing unit may be configured to form a memory unit, so as to implement a memory unit array, and the memory unit array includes the circuit shown in fig. 2, so that the area and power consumption of the memory unit array may be reduced in this embodiment.
In some optional implementations, the computing unit groups in the preset number of computing unit groups are composed of multipliers, and the multipliers are used for multiplying the single-bit stored data in the corresponding storage units and the input single-bit input data and outputting a computing result signal.
Wherein the multiplier may be implemented by various configurations of circuits. For example, the multiplier is implemented by circuits such as a double N-type field effect transistor, an N-type P-type combined field effect transistor, and the like. The working flow of the multiplier is as follows: when a single bit in a memory cell stores data (e.g., W i [0]) When 1, the multiplier is turned on to input single bit of input data (e.g. I i [0]) Directly output to the corresponding adding unit; when the single bit stored data in the memory cell is 0, the output terminal of the multiplier is turned on with a preset level (e.g., low level), i.e., outputs a level representing a digital 0 to the corresponding addition cell.
According to the embodiment, the calculation units are arranged as the multipliers, so that multiplication calculation of single-bit storage data and single-bit input data can be realized by each calculation unit, the accumulated result signals output by each addition unit group are the multiplication and accumulation result signals, and then multi-bit data multiplication and accumulation calculation based on analog signals is realized.
In some optional implementations, the multiplier includes a first switch for outputting the input single-bit input data as the calculation result signal when the single-bit stored data in the storage unit corresponding to the multiplier is the first data, and a second switch for outputting the preset level as the calculation result signal when the single-bit stored data in the storage unit corresponding to the multiplier is the second data.
The first data may be 1, the second data may be 0, and the preset level may be a low level. As shown in fig. 7, one calculation unit is a multiplier composed of a first switch 701 and a second switch 702. The first switch 701 and the second switch 702 are N-type MOS transistors, gates of the first switch 701 and the second switch 702 are respectively connected to a Q terminal and a QB terminal of the memory unit 703, the Q terminal outputs stored single-bit data, and the QB terminal outputs inverted data of the single-bit data.
The specific working flow is as follows: when Q is 1, QB is 0, the first switch 701 is turned on, the second switch 702 is turned off, and the input single bit input data (e.g., I i [0]) Directly output to the adding unit 704; when Q is 0, QB is 1, the first switch 701 is turned off, the second switch 702 is turned on, and the drain of the second switch 702 is grounded, so that the signal input to the adding unit 704 is a low level signal, thereby realizing multiplication of the single-bit stored data and the single-bit input data.
It should be noted that, the multiplier composed of two N-type MOS transistors shown in fig. 7 is merely an example, and the types of the first switch and the second switch may be arbitrarily set on the premise that multiplication calculation can be implemented, for example, may be a triode.
According to the embodiment, the multiplier is formed by arranging the first switch and the second switch, so that multiplication calculation of single-bit stored data and single-bit input data can be realized through a simple circuit, the circuit is easier to realize, and the circuit operation is more stable.
In some optional implementations, for an addition unit group in the preset number of addition unit groups, an addition unit included in the addition unit group is a capacitance value of a capacitor, and a characteristic metric value of the addition unit is the capacitance value; alternatively, the summing unit group includes a transistor, and the characteristic metric value of the summing unit is a transconductance parameter of the transistor.
The summing units included in the summing unit groups in the circuits shown in fig. 2-5 are all capacitors, through which proportional superposition of the charge domains (i.e. voltages) can be achieved at the signal output.
As shown in fig. 8, which shows a schematic diagram of a multi-bit data calculation circuit in which the addition unit is a transistor. The adding unit in fig. 8 is an N-type MOS transistor, and the output signal end can be overlapped in the current domain through the transconductance parameter of the MOS transistor. The transconductance parameters of each MOS transistor in fig. 8 are denoted as 8k, 4k, 2k, and 1k, that is, the distribution of weights for the calculation result signals in the current domain is realized. The accumulated result signal output from the signal output terminals of each of the summing unit groups shown in FIG. 8 is a current signal, and for a summing unit group composed of MOS transistors, the current output from the summing unit group is equivalent to the sum (I) of the product of the calculated result signal output from each calculating unit and the split ratio (i.e. digital weight) sum4 、I sum3 、I sum2 、I sum1 、I sum0 ) The shunt ratio is the ratio of the transconductance parameter of a single MOS tube to the total transconductance parameter of each MOS tube.
For example, for the first column of MOS tubes 801, the corresponding accumulated weight is 1, the corresponding digital weights of each MOS tube are 8/15, 4/15, 2/15, 1/15, and the corresponding product weights are 8/15, 4/15, 2/15, 1/15, respectively.
For the second row of MOS tubes 802, the corresponding accumulated weight is 8/15, the digital weights corresponding to each MOS tube are 2/4, 1/4 and 1/4 respectively, and the product weights corresponding to each MOS tube are 4/15, 2/15 and 2/15 respectively;
for the third row of MOS tubes 803, the corresponding accumulated weight is 1/5, the corresponding digital weights of each MOS tube are 1/3, 1/3 and 1/3, and the corresponding product weights are 1/15, 1/15 and 1/15;
for the fourth row of MOS tubes 804, the corresponding accumulated weight is 1/10, the corresponding digital weights of each MOS tube are 1/3, 1/3 and 1/3, and the corresponding product weights are 1/30, 1/30 and 1/30;
for the fifth row of MOS tubes 805, the corresponding accumulated weight is 1/24, the digital weights corresponding to each MOS tube are 2/5, and 1/5, and the product weights corresponding to each MOS tube are 1/60, and 1/120.
Based on the above example, the data W is stored in combination with four bits shown in fig. 3 i [3:0]And four bits of input data I i [3:0]The calculation rule of multiplication can be seen that, each multiplication factor in fig. 3 corresponds to each data in fig. 8, the multiplication weight between each column in fig. 3 is still 2 times of the relation, and in the analog-digital converter and the shift accumulator, absolute weights can be set according to actual needs, so that the calculation of an actual scene is completed.
For example, for I i [3]*W i [2]The corresponding digit weight is 2/4, the corresponding accumulated weight is 8/15, and the corresponding product weight is 4/15;
for I i [2]*W i [2]The corresponding digital weight is 1/4, the corresponding accumulated weight is 8/15, and the corresponding product weight is 2/15;
for I i [1]*W i [2]The corresponding digital weight is 1/3, the corresponding accumulated weight is 3/15, and the corresponding product weight is 1/15.
According to the embodiment, the capacitor or the transistor is used as an addition unit, so that the superposition of analog signals in a charge domain or a current domain is realized, the flexibility of circuit design is further improved on the basis of reducing the area and the power consumption of a circuit, and the application scene is expanded.
In some optional implementations, for an addition unit group in the preset number of addition unit groups, if the addition unit group is composed of a capacitor, the accumulation result signal output by the addition unit group is a voltage signal, and the analog-to-digital converter corresponding to the addition unit group is used for converting the voltage signal into a digital signal;
if the adding unit group consists of transistors, the accumulated result signal output by the adding unit group is a current signal, and the analog-to-digital converter corresponding to the adding unit group is used for converting the current signal into a digital signal.
According to the embodiment, different types of analog-to-digital converters are arranged according to different types of accumulated result signals, so that the flexibility of circuit design is further improved, the area and the power consumption of a circuit can be reduced by using a multi-bit computing circuit based on different types of analog signals, and the application field of the circuit is expanded.
Embodiments of the present disclosure also provide a chip on which an analog signal-based multi-bit data calculation circuit is integrated, and technical details of the analog signal-based multi-bit data calculation circuit are shown in fig. 1 to 8 and related descriptions, which are not described here.
Embodiments of the present disclosure also provide a computing device including the chip described in the above embodiments. The computing device may also include input devices, output devices, and necessary memory, among others. The input device may include, for example, a mouse, a keyboard, a touch screen, a communication network connector, etc., for inputting multi-bit input data, multi-bit stored data, etc. The output means may comprise, for example, a display, a printer, a communication network and a remote output device connected thereto, etc., for outputting multi-bit accumulated result data, etc. The memory is used for storing the data input by the input device and the data generated in the operation process of the multi-bit data computing circuit based on the analog signals. The memory may include volatile memory and/or nonvolatile memory. Volatile memory can include, for example, random Access Memory (RAM) and/or cache memory (cache) and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like.
The basic principles of the present disclosure have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present disclosure are merely examples and not limiting, and these advantages, benefits, effects, etc. are not to be considered as necessarily possessed by the various embodiments of the present disclosure. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, since the disclosure is not necessarily limited to practice with the specific details described.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, so that the same or similar parts between the embodiments are mutually referred to.
The block diagrams of the devices, apparatuses, devices, systems referred to in this disclosure are merely illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.
The circuitry of the present disclosure may be implemented in many ways. For example, the circuitry of the present disclosure may be implemented in software, hardware, firmware, or any combination of software, hardware, firmware. The above-described sequence of steps for a method in a circuit is for illustration only, and the steps of the method of the present disclosure are not limited to the sequence specifically described above unless specifically stated otherwise. Further, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, the programs including machine-readable instructions for implementing the functions of the circuits according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the functions of the circuit according to the present disclosure.
It should also be noted that in the circuits of the present disclosure, components or steps may be decomposed and/or recombined. Such decomposition and/or recombination should be considered equivalent to the present disclosure.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the disclosure to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.
Claims (9)
1. A multi-bit data computation circuit based on analog signals, comprising: a preset number of calculation unit groups and a preset number of addition unit groups;
for each of the preset number of computing unit groups, the computing unit group corresponds to the target adding unit group and has a corresponding accumulating weight, and the output end of each computing unit in the computing unit group is connected with the input end of the corresponding adding unit;
the target addition unit group is used for distributing corresponding digital weights to each calculation unit in the calculation unit group, accumulating calculation result signals output by each calculation unit according to the corresponding digital weights, and outputting accumulated result signals through a signal output end of the addition unit group, wherein the digital weights corresponding to each calculation unit are determined based on characteristic metric values and the accumulated weights of each addition unit in the target addition unit group;
the proportional relationship of the characteristic metric values of the respective addition units included in each of the preset number of addition unit groups is different.
2. The circuit of claim 1, wherein the circuit further comprises a preset number of analog-to-digital converters, a shift accumulator, wherein each of the preset number of analog-to-digital converters corresponds to a group of addition units;
each analog-to-digital converter in the preset number of analog-to-digital converters is used for receiving the accumulated result signals output by the corresponding adding unit group, generating digital signals according to the received accumulated result signals, and sending the obtained digital signals to the shift accumulator;
and the shift accumulator is used for carrying out shift accumulation operation on the received second preset number of digital signals according to the corresponding accumulation weights respectively to obtain multi-bit accumulation result data.
3. The circuit according to claim 1, wherein for a calculation unit group among the preset number of calculation unit groups, each calculation unit included in the calculation unit group corresponds to one storage unit for storing single-bit storage data, each calculation unit for calculating single-bit data in the corresponding storage unit and inputted single-bit input data, and inputting a calculation result signal to the corresponding addition unit.
4. The circuit of claim 3, wherein the calculation unit groups of the preset number of calculation unit groups are composed of multipliers for multiplying the single-bit stored data in the corresponding storage unit and the input single-bit input data, and outputting a calculation result signal.
5. The circuit of claim 4, wherein the multiplier comprises a first switch for outputting the input single-bit input data as the calculation result signal when the single-bit stored data in the memory cell corresponding to the multiplier is the first data, and a second switch for outputting the preset level as the calculation result signal when the single-bit stored data in the memory cell corresponding to the multiplier is the second data.
6. The circuit of claim 1, wherein for a group of adding units of the preset number of groups of adding units, the group of adding units includes adding units that are capacitance values of capacitors, and the characteristic metric value of the adding unit is a capacitance value; alternatively, the summing unit group includes a transistor, and the characteristic metric value of the summing unit is a transconductance parameter of the transistor.
7. The circuit of claim 6, wherein for an addition unit group of the preset number of addition unit groups, if the addition unit group is composed of a capacitor, the accumulation result signal output by the addition unit group is a voltage signal, and the analog-to-digital converter corresponding to the addition unit group is used for converting the voltage signal into a digital signal;
if the adding unit group consists of transistors, the accumulated result signal output by the adding unit group is a current signal, and the analog-to-digital converter corresponding to the adding unit group is used for converting the current signal into a digital signal.
8. A chip comprising the multi-bit data calculation circuit based on analog signals according to any one of claims 1 to 7.
9. A computing device comprising the chip of claim 8.
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