CN115906731A

CN115906731A - Circuit dividing method, equivalence verification method, and storage medium

Info

Publication number: CN115906731A
Application number: CN202211537212.4A
Authority: CN
Inventors: 梁豪杰; 苏宇; 白耿
Original assignee: Shenzhen Guomicrochip Technology Co ltd
Current assignee: Shenzhen Guomicrochip Technology Co ltd
Priority date: 2022-12-01
Filing date: 2022-12-01
Publication date: 2023-04-04

Abstract

The invention discloses a circuit dividing method, an equivalence verification method and a storage medium. The circuit dividing method comprises the following steps: firstly, carrying out equivalence verification on the combinational logic of the reference circuit and the realization circuit to obtain a register which fails in matching and/or a register which fails in equivalence verification of the combinational logic; using the obtained register with failed matching and/or the register with failed combinational logic equivalence verification as possible segmentation nodes, and searching all cone tops of the possible segmentation nodes; when any two possible segmentation nodes have the same cone top, dividing the nodes into a group; the reference circuit and the corresponding implementation circuit are divided in groups, and the registers in a group and the corresponding combinatorial circuits are divided into local circuits. The invention can simplify the complexity of the circuit equivalence verification of the large-scale netlist, and improve the efficiency of the circuit equivalence verification of the large-scale netlist.

Description

Circuit dividing method, equivalence verification method, and storage medium

Technical Field

The invention relates to the technical field of equivalence verification of a time sequence circuit, in particular to a circuit dividing method, namely a method for identifying and dividing a local time sequence equivalent circuit.

Background

Equivalence verification is a type of formal verification that mathematically fully proves or verifies whether an implementation of a circuit fulfills the functions described by a circuit design. The equivalence verification is mainly used for verifying functional consistency between bottom-layer circuits, such as the verification between RTL (real time language) level and gate-level netlists before and after synthesis. With the rapid increase of the scale of the integrated circuit, the verification difficulty is higher and higher, and the traditional simulation and emulation method has the defects of long consumed time, low verification coverage rate and the like. Compared with the traditional method, the method adopts a mathematical method for equivalence verification, directly compares the realization circuit with the reference circuit, does not need to develop a test vector, can greatly shorten the verification time, and has the verification coverage rate of 100 percent.

Conventional combinational circuit functional equivalence verification is accomplished by constructing a canonical representation of two circuits, such as a truth table or a binary decision diagram bdds, that are functionally equivalent if and only if their canonical representations are isomorphic. In order to verify the equivalence of two sequential circuits, it is usually necessary to treat them as finite state machines and construct a product automaton of the two. brand refers to this computational model as mitor. It is implemented by coupling together the respective original inputs of each pair of two state machines, while coupling the respective original outputs of each pair to an exclusive or gate, which forms the output of the product automaton. If each raw output of the product automaton is constant at 0 for each input sequence, then the two sequential circuits are equivalent. In other words, it is for any input vector and reachable state that the original output response of the product automaton is always 0. Typically, the first step in proving the equivalence of a state machine is to compute all reachable states, starting from an initial state. This is typically based on finite state machine traversal algorithms.

Thus, to verify that two combinational circuits are equivalent, one can construct the mitter circuits for their outputs (sharing an input signal, the outputs being connected with an exclusive-or gate), and then settle the mitter circuits using a SAT resolver (satisfiability problem solver), which prove that the two circuits are equivalent if the SAT resolver does not find a set of inputs such that the output of the mitter circuit is 1. For a sequential circuit, the circuit is required to be cut into a plurality of combinational logic blocks along a register, the divided combinational logic blocks are mapped one by one, a mitizer circuit is created, and then a SAT solution is used for solving.

However, due to the optimization strategy of the synthesis tool, the synthesized gate-level netlist and the RTL-level netlist thereof may have some matching points that are not equivalent in the combinatorial logic equivalence verification, but are equivalent in the sequential equivalence verification of the two netlists. However, the requirement for performing timing equivalence verification on two complete netlists is high, and the size of the netlist needs to be small enough. When the size of the netlist is large, the time required to complete the sequence equivalence verification may be unacceptable.

Therefore, how to provide a circuit dividing method is a technical problem to be solved for cutting a netlist with a large scale into partial circuits.

Disclosure of Invention

The invention provides a circuit dividing method, an equivalence verification method and a storage medium, and aims to solve the technical problem that in the prior art, the time required by a netlist with a large scale to complete time sequence equivalence verification is not acceptable.

The circuit dividing method provided by the invention comprises the following steps:

firstly, carrying out equivalence verification on the combinational logic of the reference circuit and the realization circuit to obtain a register which fails in matching and/or a register which fails in equivalence verification of the combinational logic;

using the obtained register with failed matching and/or the register with failed combinational logic equivalence verification as possible segmentation nodes, and searching all cone tops of the possible segmentation nodes;

when any two possible segmentation nodes have the same cone top, dividing the nodes into a group;

the reference circuit and the corresponding implementation circuit are divided in groups, and the registers in a group and the corresponding combinatorial circuits are divided into local circuits.

Further, the implementation circuit is a circuit after timing optimization.

Further, the vertex is a D end of the register in the load direction and/or a main output of the top module.

The method for verifying the circuit equivalence provided by the invention adopts the circuit dividing method in the technical scheme to divide the reference circuit and the corresponding realization circuit thereof to obtain a local circuit of the reference circuit and a local circuit of the realization circuit;

judging whether the input and the output of the local circuits of the reference circuit and the corresponding realization circuit are equal and matched with each other, if so, carrying out equivalence verification on the local circuit of the reference circuit and the local circuit corresponding to the realization circuit; otherwise, the input and the output of the local circuits of the reference circuit and the corresponding realization circuit are appointed, and after the input and the output of the local circuits of the reference circuit and the corresponding realization circuit are equal and matched with each other, equivalence verification is carried out.

The computer-readable storage medium provided by the present invention is used for storing a computer program, and the computer program executes the circuit dividing method according to the above technical solution when running.

The invention ensures that the potential local time sequence equivalent circuit is correctly identified and segmented after the circuit has the result of combined equivalent verification, and the time sequence equivalent verification is carried out on the segmented local circuit. The invention solves the problems that the RTL level circuit and the gate level circuit do not pass the combination equivalence verification and the overall time sequence equivalence verification complexity is too high under the condition that the comprehensive tool carries out local time sequence optimization on the circuit. The application of the invention in formal verification of RTL level circuits and gate level circuits will greatly reduce the verification time.

Drawings

The invention is described in detail below with reference to examples and figures, in which:

FIG. 1 is a flow chart of an embodiment of the present invention.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.

Thus, a feature indicated in this specification will serve to explain one of the features of one embodiment of the invention, and does not imply that every embodiment of the invention must have the stated feature. Further, it should be noted that this specification describes many features. Although some features may be combined to show a possible system design, these features may also be used in other combinations not explicitly described. Thus, the combinations illustrated are not intended to be limiting unless otherwise specified.

The reference circuit refers to a circuit serving as a reference standard in the equivalence verification, and the implementation circuit needs to be proved to be equivalent to the reference circuit. The reference circuit is usually verilog code of RTL level, and the implementation circuit is usually gate level circuit after synthesis. The equivalence verification referred to in the present invention refers to equivalence verification of two sequential circuits, i.e., a reference circuit and an implementation circuit. The sequential circuit comprises a register and an associated combinational logic circuit. The equivalence verification is divided into combinational logic equivalence verification and time sequence equivalence verification. Combinational logic equivalence verification refers to performing equivalence verification on two circuits that contain only combinational logic. Sequential equivalence verification refers to performing equivalence verification on two circuits containing sequential logic, namely, registers and related combinational logic. The combinatorial logic does not contain registers. The combinational logic equivalence verification is to essentially match the registers of the two sequential circuits one by one, then cut out a pair of combinational logic circuits for driving the pair of registers, and finally perform combinational logic equivalence verification on the pair of combinational logic circuits.

As shown in fig. 1, the circuit partitioning method provided by the present invention mainly includes the following steps.

And performing equivalence verification on the reference circuit and the combinational logic of the realization circuit to obtain a register with failed matching and/or a register with failed equivalence verification of the combinational logic. That is, the registers are matched to obtain the register with failed matching, and then the combinational logic corresponding to the register with successful matching is subjected to equivalence verification to obtain the register with failed equivalence verification of the combinational logic. The register that failed the match does not undergo combinational logic equivalence verification because there is no corresponding register and combinational logic circuitry driving that register to compare against it.

when any two possible segmentation nodes have the same cone top, dividing the two possible segmentation nodes into a group;

the reference circuit and the corresponding realization circuit are divided by taking a group as a unit, and the registers in the group and the corresponding combination circuit are divided into local circuits.

In one embodiment, the process of finding the vertex of the cone comprises the following steps.

Registers failing the verification of the equivalence of combinational logic and registers failing the matching are collected and referred to as potential nodes of partitioning.

And performing depth-first traversal from the direction of the output ends of the possible segmentation nodes, namely traversing from the input end of one gate to the output end of the top module or stopping traversal at the D end of the register passing the verification in the first round of the verification of the combinational logic equivalence, and recording the traversed register as a cone top, namely the output of the top module.

For example, through the above-mentioned step of finding the vertex, the vertex of the register a has the register 2, the vertex of the register B has the register 2 and the register 3, and the vertex of the register C has the register 3, so that the register a, the register B, and the register C are all divided into the same group. Since register A and register B have a common vertex, register 2, first, they are divided into the same group. There are now two registers in the group, and the union of the vertices of these two registers constitutes the vertex of the group, i.e. if the vertex of register a is 2, then the vertex of the group in which register a is located is 2, 3. The vertex set of registers that need to be grouped, if it intersects the vertex set of a certain group, then the registers are sorted into the group, and then the vertex set of the group is the union of the vertex sets of all registers within the group.

In one embodiment, the implementation circuit may be subjected to timing optimization, and then the combinational logic of the implementation circuit and the reference circuit after the timing optimization is subjected to equivalence verification, so as to obtain a register with failed matching and/or a register with failed equivalence verification of the combinational logic.

In one embodiment, the vertex may be the D-terminal of the register in the load direction, and/or the primary output of the top module.

The load direction is the direction from the input of one gate to the output of this gate. The top module refers to the module with the hierarchy at the top. The circuit design is formed by a top module and a plurality of sub-modules in the module.

The method for verifying the equivalence of the circuit comprises the steps of dividing a reference circuit and a corresponding realization circuit by adopting the circuit dividing method to obtain a local circuit of the reference circuit and a local circuit of the realization circuit, judging whether the input and the output of the local circuit of the reference circuit are equal and matched with each other, and verifying the equivalence of the local circuit of the reference circuit and the local circuit corresponding to the realization circuit if the input and the output are equal in quantity and matched with each other. Otherwise, the input and output of the unmatched local circuit are designated by manual operation and the like, so that the local circuit of the test circuit and the local circuit corresponding to the realization circuit can meet the input and output condition of the equivalence verification.

The input and output of the divided local circuits are not necessarily equal in quantity and are matched with each other, and only the local circuits with equal input and output quantity and matched with each other can be used for verifying the time sequence equivalence. Generally, if the timing optimization of the circuit is implemented to result in a large percentage of unmatched registers, the number of inputs and outputs of the cut local circuits is not equal or matched with each other, and at this time, manual intervention is needed to designate the inputs and outputs of the local circuits, so that the local circuits are cut according to the designated inputs and outputs, and the timing equivalence verification is performed.

By the circuit dividing method, the netlist circuit with larger scale can be divided into the local circuits, so that the verification complexity is reduced, the verification time of the circuit is shortened, and the verification efficiency of the circuit is improved.

The present invention also protects a computer-readable storage medium for storing a computer program which, when running, executes the circuit dividing method according to the above-described aspect of the present invention.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. A method of partitioning a circuit, comprising:

2. The method for partitioning a circuit according to claim 1, wherein said realized circuit is a timing-optimized circuit.

3. The method of partitioning a circuit as claimed in claim 1, wherein said vertex is D of a register in a load direction

End, and/or main output of the top module.

4. A method of partitioning a circuit as claimed in claim 1, wherein the vertex of any one group is the union of the vertices of all the partitioned possible nodes in the group.

5. The method of circuit partitioning as claimed in claim 1, wherein said finding all vertices of each partitioned possible node comprises:

traversing from the direction of the output end of each possible node, stopping traversing to the output port of the top module or the D end of the register which passes the verification in the first round of the verification of the combinational logic equivalence, and recording the traversed register as the cone top.

6. A circuit equivalence verification method is characterized in that a reference circuit and a corresponding realization circuit are divided by the circuit dividing method according to any one of claims 1 to 5 to obtain a local circuit of the reference circuit and a local circuit of the realization circuit;

judging whether the input and the output of the local circuits of the reference circuit and the corresponding realization circuit are equal and matched with each other, if so, carrying out equivalence verification on the local circuit of the reference circuit and the local circuit corresponding to the realization circuit; otherwise, the input and output of the partial circuits of the reference circuit and the corresponding realization circuit are appointed, so that the input and output of the partial circuits of the reference circuit and the corresponding realization circuit are equal and matched with each other, and then the equivalence verification is carried out.

7. A computer-readable storage medium for storing a computer program, wherein the computer program is operable to perform the method of dividing a circuit according to any one of claims 1 to 5.