CN115827636A

CN115827636A - Method for storing and reading simulation data of logic system design from waveform database

Info

Publication number: CN115827636A
Application number: CN202211632226.4A
Authority: CN
Inventors: 白继伟
Original assignee: Core Huazhang Technology Xiamen Co ltd
Current assignee: Core Huazhang Technology Xiamen Co ltd
Priority date: 2022-12-19
Filing date: 2022-12-19
Publication date: 2023-03-21

Abstract

The application relates to the technical field of data storage, and particularly discloses a method for storing and reading simulation data of a logic system design from a waveform database, which comprises the following steps: determining a structure tree file corresponding to the logic system design according to the logic system design, wherein the structure tree file comprises a plurality of modules in a plurality of levels and a plurality of identifications of signals corresponding to the modules, and the identifications comprise first identifications of first signals; receiving first data comprising a change in a value of the first signal at a first time; saving a first identification of the first signal and the first data in association to a first data file; and associating the structure tree file with the first data file. According to the method and the device, the waveform data generated in the simulation process of the logic system design are stored in the waveform database in a mode of separating the data structure of the signal from the value change data, so that the storage efficiency is improved, and the data redundancy of the waveform database is reduced.

Description

Method for storing and reading simulation data of logic system design from waveform database

Technical Field

The present disclosure relates to the field of data storage, and more particularly, to a method for storing and reading simulation data of a logic system design from a waveform database.

Background

A database generally refers to a warehouse that organizes, stores, and manages data according to a data structure, and may be an organized, sharable, and uniformly managed collection of large amounts of data that is stored in a computer for a long period of time. With the development of cloud computing and the arrival of the big data era, more and more data are required to be stored and managed in the database, and higher requirements are put on the database. Storing waveform data is critical to the operation of a traceback design, for example, during logic design verification. As the design scale increases, the amount of waveform data that needs to be stored increases.

In the related art, in order to accelerate the storage speed of waveform data, one waveform database may be split into a plurality of waveform databases, so that data may be written to the plurality of databases at the same time. Each of the divided databases is an independent database, and the waveform structure and the signal value change data of the data are stored. However, as the design scale increases, the waveform structure of the data occupies a larger storage space, so that there is a large amount of redundant data per split database.

Disclosure of Invention

In view of the above, it is necessary to provide a method of storing simulation data of a logic system design, a method of reading simulation data of a logic system design from a waveform database, an electronic device, and a non-transitory computer-readable storage medium.

In a first aspect, the present application provides a method of storing simulation data for a logic system design. The method comprises the following steps:

determining a structure tree file corresponding to the logic system design according to the logic system design, wherein the structure tree file comprises a plurality of modules in a plurality of levels and a plurality of identifications of signals corresponding to the modules, and the identifications comprise first identifications of first signals;

receiving first data comprising a change in a value of the first signal at a first time;

saving a first identification of the first signal and the first data in association to a first data file; and

associating the structure tree file with the first data file.

In a second aspect, the present application also provides a method of reading simulation data of a logic system design from a waveform database. The waveform database includes a structure tree file corresponding to the logic system design, the structure tree file including a plurality of modules at a plurality of levels and a plurality of identifications of signals corresponding to the plurality of modules, the plurality of identifications including a first identification of a first signal, a first data file, and a second data file, the structure tree file being associated with the first data file and the second data file, the method comprising:

receiving an instruction of reading a waveform of a target signal, and determining an identifier of the target signal;

according to the identification of the target signal, obtaining structural data of the target signal in the structure tree file, wherein the structural data comprises information of a module to which the target signal belongs;

and loading the first data file or the second data file, and acquiring the value change data of the target signal according to the identification of the target signal.

In a third aspect, the present application also provides a non-transitory computer-readable storage medium storing a set of instructions of a computer for, when executed, causing the computer to perform the method of the first or second aspect.

According to the embodiment of the application, through a debugging tool, waveform data generated in a simulation process of logic system design is stored in a waveform database in a mode of separating a data structure of a signal from value change data, a specific structure tree file stores a plurality of modules in multiple levels and a plurality of identifications of the signal corresponding to the modules, the data file stores the value change data of the signal and associates the structure tree file with the data files, the value change data generated in the simulation process can be stored in the data file rapidly according to the associated structure tree file, the data file can be added flexibly according to the scale of the value change data generated in the simulation process, the data structure and the value change data are stored separately, the storage space occupied in the data file is avoided, and the data structure is repeatedly stored, so that the storage efficiency is improved, and the data redundancy of the waveform database is reduced. In addition, by establishing the correspondence between the signal name and the signal identification, data can be read and stored in the waveform database.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present disclosure, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 shows a schematic diagram of a host according to an embodiment of the application.

FIG. 2A shows a schematic diagram of a simulation tool, a debugging tool and a debugging tool according to an embodiment of the application.

Fig. 2B shows a schematic diagram of a waveform database according to an embodiment of the application.

FIG. 3 shows a schematic diagram of a structure tree file according to an embodiment of the present application.

FIG. 4 shows a schematic diagram of a storage tool determining a structure tree file according to an embodiment of the present application.

FIG. 5 shows a data file schematic according to an embodiment of the application.

FIG. 6 is a schematic diagram illustrating a method of storing simulation data for a logic system design according to an embodiment of the present application.

FIG. 7 is a schematic diagram illustrating a method of reading simulation data for a logic system design from a waveform database according to an embodiment of the application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

It should be noted that the terms "first," "second," and the like in the description and claims of the present disclosure and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are capable of operation in sequences other than those illustrated or otherwise described herein. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the presence of additional identical or equivalent elements in a process, method, article, or apparatus that comprises the recited elements is not excluded. For example, if the terms first, second, etc. are used to denote names, they do not denote any particular order.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.

Fig. 1 shows a schematic diagram of a host 100 according to an embodiment of the application. The host 100 may be an electronic device running an emulation system. As shown in fig. 1, the host 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Wherein processor 102, memory 104, network interface 106, and peripheral interface 108 are communicatively coupled to each other within the host via bus 110.

Processor 102 may be a Central Processing Unit (CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits. The processor 102 may be used to perform functions associated with the techniques described herein. In some embodiments, processor 102 may also include multiple processors integrated into a single logic component. As shown in FIG. 1, the processor 102 may include a plurality of

processors

102a, 102b, and 102c.

The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, the simulation test system for simulating a test design may be a computer program stored in memory 104. As shown in fig. 1, the data stored by the memory may include program instructions (e.g., for implementing the method of the present application to launch software in terms of functionality) and data to be processed (e.g., the memory may store temporary code generated during the compilation process). The processor 102 may also access memory-stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include volatile memory devices or non-volatile memory devices. In some embodiments, the memory 104 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSDs), flash memory, memory sticks, and the like.

The network interface 106 may be configured to provide communications with other external devices to the host 100 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the above. It is to be understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, and the like.

The peripheral interface 108 may be configured to connect the host 100 with one or more peripheral devices to enable information input and output. For example, the peripheral devices may include input devices such as keyboards, mice, touch pads, touch screens, microphones, various sensors, and output devices such as displays, speakers, vibrators, indicator lights, and the like.

The bus 110 may be configured to transfer information between various components of the host 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (e.g., a USB port, a PCI-E bus), and so forth.

It should be noted that although the host architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in a specific implementation, the host architecture may also include other components necessary to achieve normal operation. Furthermore, those skilled in the art will appreciate that the above-described host architecture may also include only the components necessary to implement the embodiments of the present application, and need not include all of the components shown in the figures.

FIG. 2A shows a schematic diagram of a simulation tool 202 and a debugging tool 200 according to an embodiment of the present application. Debug tool 200 may be a computer program running on host 100. Simulation tool 202 may be a software simulation tool or a hardware simulation tool.

In the field of chip design, a design may be simulated using a simulation tool. The simulation tool may be, for example, a GalaxSim simulation tool available from Chihua chapter science and technology, inc. The example simulation tool 202 shown in FIG. 2A may include a compiler 120 and a simulator 220. Compiler 120 may compile a design (e.g., verification design 214) into object code 204, simulator 220 may simulate from object code 204, and output simulation results 206. For example, the simulation tool 202 may output simulation results (e.g., a simulation waveform diagram) onto an output device (e.g., displayed on a display) via the peripheral interface 108 of fig. 1. The verification design 214 may include a logic system design 214a and a verification environment 214b. The verification environment 214b may also be referred to as a test bench (testbench). For example, the verification environment 214b may be a UVM environment.

The debug tool 200 may also read the simulation results 206. The debugging tool 200 may be, for example, a Fusion Debug tool available from Chihua Chapter science and technology, inc. For example, the debugging tool 200 may read the simulation results 206 stored in a waveform file and generate corresponding simulation waveforms for debugging. Debug tool 200 can also read the description of verification system 214 (typically SystemVerilog and Verilog code) and display it to the user. The debugging tool 200 may also generate various graphical interfaces (e.g., debugging windows) to facilitate the user's debugging effort. The user may issue a debug command 208 to the debug tool 200 (e.g., run the verification design 214 to a certain point in time), which the debug tool 200 then applies to the simulation tool 202 to execute accordingly. Debug tool 200 may also read the log file. Various information of the simulation process can be included in the log file, including information of simulation errors, a row number of error reporting, time of occurrence of the simulation errors, and the like.

It will be appreciated that in addition to interfacing with simulation tool 202, debug tool 200 may also interface with a hardware simulator (emulator).

Before the logic system design is put into practical operation, the compiled logic system design needs to be debugged by using the debugging tool 200. The debugging tool 200 may receive user instructions from a user and make corresponding debugging actions. In some embodiments, a user may issue a user instruction in a graphical interface by clicking a mouse; in some embodiments, a user may enter a command line in a command line interface to issue a user instruction. In the debugging process, a user often stores a waveform file in simulation data and inquires a waveform signal of a variable signal within a certain time range, so that the user can find the abnormity of the logic system design through waveform visualization, further diagnose, find out the reason and the specific source position of the abnormity, correct and ensure the robustness of the logic system design.

The debugging tool 200 may read the simulation results 206 and store the simulation results 206 in the form of a waveform database 212. The waveform database 212 storing waveform data may also be referred to as a waveform file.

As the scale of logic system design increases, the waveform data that needs to be stored becomes more voluminous. In order to accelerate the storage speed of the waveform data, one waveform database can be divided into a plurality of waveform databases, so that data can be written into the plurality of databases at the same time. Each database is an independent database, and the structure tree and the signal value change data of the logic system design are stored. Logic system designs typically include multiple levels, each level having a respective signal. The multiple levels and the signals at each level form a tree of structures for the logic system design. It is common practice to provide a complete structure tree for each individual waveform database, so that the signal value change data of the waveform database can correspond to a specific signal, and the debugging tool can restore the signal. However, with the increase of the design scale, the number of the levels of the logic system design is increased, and signals in each level are increased, so that the structure tree occupies a larger storage space, a large amount of redundant data exists in each split database, the whole waveform file is enlarged, and the read-write efficiency is reduced.

In view of the above, embodiments of the present application provide a method of storing logic system simulation data, a method of reading logic system simulation data from a waveform database, an electronic device, and a non-transitory computer-readable storage medium. By the method, in the simulation test process, the waveform data in the simulation result 206 can be stored in a plurality of waveform databases, specifically, the structure data of the variable signal in the logic system design is stored in the structure tree files in the plurality of waveform databases, the value change data of the variable signal is stored in the data files in the structure tree files in the plurality of waveform databases, and the association relationship between the structure tree files and the data files is established, so that the redundant data of the waveform structures in the plurality of waveform databases can be reduced, the waveform data can be stored in the waveform databases quickly and efficiently, and the waveform data can be read from the waveform databases quickly.

Next, the present application will explain how to store the waveform data in the simulation result 206 in a plurality of waveform databases and how to read the waveform data from the waveform databases.

Fig. 2B shows a schematic diagram of a waveform database 212 according to an embodiment of the application. Waveform database 212 may include a structure tree file 210 and a data file 220.

Debug tool 200 may determine, from the logic system design (e.g., source code of logic system design 214 a), a structure tree file 210 corresponding to the logic system design. The structure tree file 210 includes a complete structure tree of the logic system design for recording the structure of the waveform data. The debugging tool 200 may receive the value change data of the variable signal in the simulation result 206 within a certain time range, store the value change data in the data file 220, and associate the structure tree file 210 with the data file 220. The structure tree file 210 may correspond to a plurality of data files 220, such as a first data file 220a, a second data file 220b, \8230; \8230anNth data file 220N. According to the embodiment of the application, the structure tree and the value change data of the waveform data are stored by adopting the storage files respectively, and one structure tree file is associated with a plurality of data files, so that data redundancy caused by variable storage structure data in the data files can be avoided, the storage segmentation of the data files is facilitated, and the storage is quicker and more flexible.

FIG. 3 shows a schematic diagram of a structure tree file according to an embodiment of the present application. Current logic system designs include multiple levels, each of which may include one or more modules.

The tree file 210 may store a plurality of modules of a plurality of levels of the logic system design and a plurality of signals corresponding to the plurality of modules through a tree structure. The structure tree file 210 may include a root directory (root scope) and a hierarchy directory (scope) corresponding to a plurality of hierarchies. The root directory (root scope) and the hierarchical directory (scope) of the plurality of levels correspond to the plurality of modules of the plurality of levels of the logic system design one to one. For example, fig. 3 shows that the root directory (root directory) of the structure tree file 210 includes the primary directories Scope _1 and Scope _2. The primary directory Scope _1 includes therein secondary directories Scope _1 \, and variable var4. Variables var1 and var2 are included under the secondary directory Scope _1 \1. The variable var3 is included under the secondary directory Scope _1 \2. A secondary directory Scope _2 \1is included under the primary directory Scope _2. The variable var5 is included under the secondary directory Scope _2 \1. The root directory (root directory), the primary directories Scope _1 and Scope _2, the secondary directories Scope _1 \, and Scope _2 \, respectively correspond to a plurality of modules of a plurality of levels of the logic system design, and the variables var1 to var5 are signals in the logic system design.

In some embodiments, while storing values (e.g., value changes) of signals of a logic system design to a waveform database, debug tool 200 may also store signal Identifications (IDs) corresponding to the signals in structure tree file 210. The structure tree file 210 stores variables var1 to var5 in the form of a structure, and is used for recording signal identifications and global names of signals in the structure tree. For example, the global title of variable var1 in the structure tree is "root _ scope _1.Scope_1 _. Var1". The structure tree file 210 also stores the corresponding relationship between the signal and the signal identifier, for example, the corresponding relationship may be stored in a mapping table manner. The signal Identification (ID) may be a number corresponding to a plurality of signals. For example, the mapping table may record a corresponding relationship between a signal name and a signal identifier, and specifically refer to table one, where variables var1 to var5 in the mapping table are variable signal names.

ID	Var
			1	var1
2	Var2
		3	Var3
4	Var4
		5	Var5

Watch 1

It is to be noted that when storing the value change data of the variable signal into the data file, the signal identification and the value change of the signal may be directly stored. Since the signal identification is a digital type variable (e.g., int) and the name of the variable signal is a character string type variable, using the signal identification can help to further increase the storage speed of the value change data and facilitate the subsequent quick query of the value change data of the signal according to the signal identification.

Fig. 4 shows a schematic diagram of a storage tool determination structure tree file 210 according to an embodiment of the present application. As shown in fig. 4, the structure tree file 210 may further include a plurality of signal block files (e.g., a first signal block file 210a and a second signal block file 210 b) in addition to the structure of the recorded logic system design. When the simulation of the logic system design is carried out, the waveform data is generated continuously along with the advance of the simulation time. The generated waveform data is first stored in the buffer memory, and after a certain amount of waveform data is buffered, the waveform data is stored in the waveform database 212 in the form of one data block. That is, each of the first data file 220a, the second data file 220b, \ 8230, and the nth data file 220N may include a plurality of data blocks. The signal block file may indicate the location of the data block to which the signal identifier belongs, so that reading and writing of the value of the signal may be performed in the corresponding data file 220.

In some embodiments, during the process of reading the simulation data of the logic system design from the waveform database, the debugging tool 200 may receive a user instruction from a user to view the waveform of the target signal. The command for reading the waveform of the target signal usually includes the signal name of the target signal. Furthermore, the debugging tool 200 may read a plurality of signal identifications and signal names corresponding relations (for example, a mapping table one) in the structure tree file 210, and may determine an Identification (ID) of the target signal according to the signal name of the target signal. The debugging tool 200 may quickly locate the structure data of the target signal in the structure tree file 210 according to the determined Identification (ID) of the target signal, that is, may determine the module to which the target signal specifically belongs in the logic system design. The debugging tool 200 may also quickly locate the value change data of the target signal in the data file according to the determined Identification (ID) of the target signal, generate waveform data of the target signal by combining the structure data of the target signal and the value change data, and display the waveform of the target signal to the user through the debugging tool 200.

The emulation data may include a signal name and value change data. The process of writing simulation data to the waveform database is similar to the process of reading simulation data described above. That is, the debugging tool 200 may determine, according to the signal name of the generated simulation data, a signal identifier corresponding to the signal name based on a correspondence relationship between a plurality of signal identifiers and the signal name. Debug tool 200 may store value change data to data file 220 based on the determined signal identification.

FIG. 5 shows a schematic diagram of a data file 500 according to an embodiment of the application. The data files 500 shown in fig. 5 may include data file a, data file B, and data file C. Data file a, data file B, and data file C are associated with structure tree file 210. The data file can be divided according to time ranges, namely a data file A is used for storing value change data with the time range of [0, 100], a data file B is used for storing value change data with the time range of [101, 200], and a data file C is used for storing value change data with the time range of [201, 300 ]. The unit of the time range may be set by the user himself.

In determining value change data of a target signal according to an Identification (ID) of the target signal, the debugging tool 200 may load a target data file satisfying an instruction among a plurality of data files. The instruction for reading the waveform of the target signal usually includes a time range of the target signal required to display the waveform. The debugging tool 200 may determine the target time range of the target signal according to an instruction of the waveform of the target signal, for example, an instruction of reading the waveform of the target signal indicates to acquire waveform data of the target signal in the time range of [80, 150 ].

The debugging tool 200 may determine the target data file to be loaded according to the time ranges of the plurality of data files and the target time range, so that the target data file includes the value change data of the target time range, thereby enabling the debugging tool 200 to load the target data file quickly and reducing unnecessary data loading.

In some embodiments, the debugging tool 200 determines whether the time ranges of the plurality of data files and the target time range have an overlap range, and then uses the value change data of the overlap range in the data file as the target data file. Referring to fig. 5, the debugging tool 200 compares the time range [0, 100] of the data file a with the target time range [80, 150] to determine whether the time ranges overlap. At this time, the debug tool 200 determines yes and sets [80, 100] in the data file a as the target data file. The storage tool 200 continuously compares the time range [101, 200] of the data file B with the target time range [80, 150] to judge whether the time range has an overlapping range. At this time, the debug tool 200 determines yes, and sets [101, 150] in the data file B as the target data file. The debugging tool 200 continuously compares the time range [201, 300] of the data file C with the target time range [80, 150] to judge whether the time range has an overlapping range. At this time, the debugging tool 200 determines no, and the debugging tool 200 may end the determination, with [80, 100] in the data file a and [101, 150] in the data file B as the target data file. After determining all target data files, debugging tool 200 loads [80, 100] in data file a and [101, 150] time-range value change data in data file B, and determines value change data of target signals in target time ranges according to the target signals. According to the embodiment, the target data file in the target time range can be accurately loaded in the plurality of data files in the time range, the data reading speed can be further improved, and unnecessary data loading is reduced.

According to the embodiment of the application, through a debugging tool, waveform data generated in a simulation process of logic system design is stored in a waveform database in a mode of separating a data structure of a signal from value change data, a specific structure tree file stores a plurality of modules in multiple levels and a plurality of identifications of the signal corresponding to the modules, the data file stores the value change data of the signal and associates the structure tree file with the data files, the value change data generated in the simulation process can be stored in the data file rapidly according to the associated structure tree file, the data file can be added flexibly according to the scale of the value change data generated in the simulation process, the data structure and the value change data are stored separately, the storage space occupied in the data file is avoided, and the data structure is repeatedly stored, so that the storage efficiency is improved, and the data redundancy of the waveform database is reduced. In addition, by establishing the correspondence between the signal name and the signal identifier, data can be read and stored in the waveform database.

Some embodiments of the present application also provide a method of storing logic system emulation data.

FIG. 6 illustrates a schematic diagram of a method 600 of storing logic system emulation data in accordance with an embodiment of the present application. Method 600 may be performed by host 100 of fig. 1, and more specifically, may be performed by debug tool 200 of fig. 2A running on host 100. The method 600 may include the following steps.

At step 610, host 100 may determine a structure tree file corresponding to the logic system design from the logic system design (e.g., source code of the logic system design). The structure tree file (e.g., 210 in fig. 2B and 3) includes a plurality of modules at a plurality of levels and a plurality of identifications of signals corresponding to the plurality of modules, the signal identifications being used to determine corresponding signals. The plurality of identifications may include a first identification of the first signal and a second identification of the second signal. It is understood that the host 100 may analyze and compile the logic system design, and further analyze the modules therein to obtain a plurality of modules at a plurality of levels of the logic system design and a plurality of signals under the plurality of modules.

At step 620, the host 100 may receive first data, wherein the first data includes a change in a value of the first signal at a first time. Wherein, the first data can be value change data generated by the simulation tool simulation process first signal.

At step 630, host 100 may save the first identification of the first signal and the first data in association to a first data file.

At step 640, host 100 may associate the structure tree file with the first data file. That is, a first data file corresponding to the first signal can be determined through the structure tree file, the structure data and the first identifier of the first signal are stored in the structure tree file, and the value change data and the first identifier of the first signal are stored in the first data file.

In some embodiments, the method 600 further comprises:

at step 650, the host 100 may receive second data including a change in a value of the second signal at a second time.

At step 660, host 100 may save the second identification of the second signal and the second data in association to a second data file.

At step 670, the host 100 may associate the structure tree file with the first data file and the second data file. The structure tree file and the first and second data files are stored in association as a waveform database (e.g., waveform database 212 of fig. 2A) that includes the structure tree file and a plurality of data files associated with the structure tree file, the plurality of data files including the first and second data files, the structure tree file further including a first signal block file. The first data file and the second data file may include a plurality of data blocks, the plurality of signal identifications may include a target signal identification, and the first signal block file may indicate a location of the data block to which the target signal identification belongs.

It should be noted that the first signal and the second signal are both variable signals in the logic system design, the first signal and the second signal each include a plurality of variable signals, and the plurality of variable signals included in the first signal and the plurality of variable signals included in the second signal may be completely different or partially/completely the same. The first time and the second time may be completely different or partially/completely the same time range, typically the first time and the second time are completely different.

In some embodiments, the plurality of numbers are identified as corresponding to a plurality of signals, and the structure tree file includes a correspondence between the plurality of numbers and signal names of the plurality of signals (e.g., the mapping table one).

In some embodiments, step 610 further comprises: in conjunction with FIG. 4, host 100 may determine a plurality of modules at multiple levels in a logical system design and store the plurality of modules to a first cache file. The host 100 may further determine signals corresponding to a plurality of modules, and store the signals corresponding to the plurality of modules in a second cache file. The host 100 may determine a structure tree file corresponding to the logic system design from the first cache file and the second cache file.

Also provided in some embodiments of the present application is a method of reading logic system emulation data from a waveform database.

FIG. 7 is a schematic diagram illustrating a method of reading logic system emulation data from a waveform database in accordance with an embodiment of the present application. The waveform database includes a structure tree file corresponding to the logic system design, the structure tree file including a plurality of modules at a plurality of levels and a plurality of identifications of signals corresponding to the plurality of modules, the plurality of identifications including a first identification of the first signal, the structure tree file being associated with the first data file and the second data file. Method 700 may be performed by host 100 of fig. 1, and more specifically may be performed by debug tool 410 of fig. 2A running on host 100. The method 700 may include the following steps.

At step 710, host 100 may receive an instruction to read a waveform of a target signal (e.g., debug command 208 in FIG. 2A) and determine an identification of the target signal. Specifically, the host 100 may receive an instruction of a user to read a waveform of a target signal by clicking a mouse in the graphical interface, and may also receive an instruction of a user to read a waveform of a target signal by inputting a command line in the command line interface. In some embodiments, the instruction for reading the waveform of the target signal generally includes the signal name of the target signal, and the host 100 may determine the signal name of the target signal according to the instruction for reading the waveform of the target signal, and further read the correspondence between the plurality of numbers and the signal names of the plurality of signals from the structure tree file to determine the number of the target signal.

In step 720, the host 100 may obtain the structure data of the target signal in the structure tree file according to the identifier of the target signal, where the structure data includes the information of the module to which the target signal belongs.

In step 730, the host 100 may load the first data file or the second data file, and obtain the value change data of the target signal according to the identifier of the target signal.

In some embodiments, step 730 further includes steps 732-736 as follows.

In step 732, the host 100 may determine a target time range of the target signal according to an instruction to read the waveform of the target signal. The instruction to read the waveform of the target signal typically also includes a target time range of the target signal.

At step 734, host 100 may determine a target data file to be loaded according to the first time of the first data file, the second time of the second data file, and the target time range, where the target data file is a part or all of the first data file and/or a part or all of the second data file. Wherein the target data file includes at least value change data of the target signal within the target time range.

At step 736, host 100 may load the target data file and obtain the value change data of the target signal in the target time range according to the identification of the target signal in the target data file.

In some embodiments, step 734 further comprises: the host 100 may determine whether the first time and the target time range overlap, and in response to the first time and the target time range overlapping, the host 100 may determine that value change data of the first time and the target time range in the first data file overlap as the target data file. The host 100 may determine whether there is an overlap range between the second time and the target time range, and in response to the existence of the overlap range between the second time and the target time range, the host 100 may determine that the value change data of the second time and the target time range in the second data file has the overlap range as the target data file.

The embodiment of the application also provides the electronic equipment. The electronic device may be the host 100 of fig. 1. The electronic device may include a memory to store a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform method 600 or method 700.

Embodiments of the present application also provide a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores a set of instructions of a computer for causing the computer to perform the method 600 or the method 700 when executed.

Some embodiments of the present application are described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the context of the present application, technical features in the above embodiments or in different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the present application described above, which are not provided in detail for the sake of brevity.

While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures, such as Dynamic RAM (DRAM), may use the discussed embodiments.

The present application is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalents, improvements, and the like that may be made without departing from the spirit or scope of the present application are intended to be included within the scope of the claims.

Claims

1. A method of storing simulation data for a logic system design, the method comprising:

associating the structure tree file with the first data file.

2. The method of claim 1, wherein the method comprises:

receiving second data, the second data comprising a change in a value of the second signal at a second time;

saving a second identification of the second signal and the second data in association to a second data file;

associating the structure tree file with the first data file and the second data file.

3. The method of claim 1, wherein the plurality of identifications are numbers corresponding to the plurality of signals, and wherein the structure tree file includes a correspondence of the plurality of numbers to signal names of the plurality of signals.

4. The method of claim 2, wherein the structure tree file and the first data file and the second data file are stored in association as a waveform database, the waveform database including the structure tree file and a plurality of data files associated with the structure tree file, the plurality of data files including the first data file and the second data file, the structure tree file further including a first signal block file.

5. A method of reading simulation data for a logic system design from a waveform database, the waveform database including a structure tree file, a first data file, and a second data file corresponding to the logic system design, the structure tree file including a plurality of modules at a plurality of levels and a plurality of identifications of signals corresponding to the plurality of modules, the plurality of identifications including a first identification of a first signal, the structure tree file being associated with the first data file and the second data file, the method comprising:

6. The method of claim 5, wherein the plurality of identifiers are numbers corresponding to the plurality of signals, and the structure tree file comprises a correspondence between the plurality of numbers and signal names of the plurality of signals; the receiving an instruction to read a waveform of a target signal and determining an identity of the target signal further comprises:

and reading the corresponding relation between the plurality of numbers and the signal names of the plurality of signals from the structure tree file, and determining the number of the target signal.

7. The method of claim 5, wherein the loading the first data file or the second data file, and the obtaining the value change data of the target signal according to the identification of the target signal further comprises:

determining a target time range of the target signal according to the instruction for reading the waveform of the target signal;

determining a target data file to be loaded according to the first time of the first data file, the second time of the second data file and the target time range, wherein the target data file is a part or all of the first data file and/or a part or all of the second data file;

and loading the target data file, and acquiring the value change data of the target signal in the target time range in the target data file according to the identification of the target signal.

8. The method of claim 7, wherein determining the target data file to be loaded according to the first time of the first data file, the second time of the second data file, and the target time range further comprises:

judging whether a coincidence range exists between the first time and the target time range;

responding to the coincidence range between the first time and the target time range, and determining value change data of the coincidence range between the first time and the target time range in the first data file as the target data file;

judging whether a coincidence range exists between the second time and the target time range;

and in response to the second time and the target time range having the coincidence range, determining value change data of the second data file having the coincidence range between the second time and the target time range as the target data file.

9. An electronic device, comprising

A memory for storing a set of instructions; and

at least one processor configured to execute the set of instructions to cause the electronic device to perform the method of any of claims 1-8.

10. A non-transitory computer-readable storage medium storing a set of instructions of a computer, the set of instructions, when executed, causing the computer to perform the method of any of claims 1 to 8.