CN115728723A - Balanced detector and frequency modulation continuous wave radar - Google Patents
Balanced detector and frequency modulation continuous wave radar Download PDFInfo
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- CN115728723A CN115728723A CN202111016005.XA CN202111016005A CN115728723A CN 115728723 A CN115728723 A CN 115728723A CN 202111016005 A CN202111016005 A CN 202111016005A CN 115728723 A CN115728723 A CN 115728723A
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- 239000003990 capacitor Substances 0.000 claims description 92
- 230000000903 blocking effect Effects 0.000 claims description 42
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- 230000003287 optical effect Effects 0.000 claims description 30
- 238000001514 detection method Methods 0.000 claims description 17
- 230000003321 amplification Effects 0.000 claims description 14
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 14
- 230000035559 beat frequency Effects 0.000 claims description 12
- 230000010355 oscillation Effects 0.000 claims description 7
- 230000003139 buffering effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 17
- 230000001427 coherent effect Effects 0.000 description 8
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/36—Means for anti-jamming, e.g. ECCM, i.e. electronic counter-counter measures
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/41—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00 using analysis of echo signal for target characterisation; Target signature; Target cross-section
Abstract
A balanced detector and frequency modulated continuous wave radar, the balanced detector comprising: first detector, second detector, amplifying unit and direct current bypass, wherein: the second end of the first detector is coupled with the first end of the second detector; the input end of the amplifying unit is coupled with the second end of the first detector and the first end of the second detector, and is coupled with the direct current bypass; a DC bypass adapted to direct a DC component output by the first detector and the second detector; the direct current component and the direct current bypass form a loop to stabilize the voltage at the input end of the amplifying unit. According to the scheme, the influence of unequal direct current components of different detectors on the balance detector can be avoided, and the signal-to-noise ratio of the output signal of the balance detector is improved.
Description
Technical Field
The invention relates to the technical field of radars, in particular to a balanced detector and a frequency modulation continuous wave radar.
Background
According to the modulation and detection modes of a transmission link, laser communication and detection can be divided into two basic modes, namely coherent and incoherent. Coherent laser communication/detection has the advantages of high conversion gain, capability of obtaining all frequency and phase information, good filtering performance, capability of being applied to detection of weak signals and the like. However, in coherent detection, the effects of local oscillation Noise, relative Intensity Noise (RIN) of the laser, shot Noise, and temperature difference cannot be eliminated. In order to better utilize the local oscillator optical power, inhibit RIN and further improve the system sensitivity, various balance detectors based on coherent detection technology are widely applied.
Referring to fig. 1, a schematic diagram of coherent detection of a conventional balanced detector is shown. Local oscillation light Alo and return light signal As are respectively introduced into the coupler by the waveguide, the Alo and As interfere in the coupler, and the light intensity of coherent light can be expressed As
Wherein
And
in order to produce the direct-current light component,
is an ac coherent term. The coupler outputs light as I1 and I2 shown in FIG. 1, where the DC optical signals of I1 and I2 are equal in amplitude and opposite in phase. I1 and I2 respectively irradiate the detector PD1 and the detector PD2 to generate photocurrent I 1 And i 2 Wherein i 1 And i 2 The direct current components have the same magnitude and opposite directions and can be mutually counteracted; the alternating current components have the same amplitude and opposite phases, and the balance detector outputs the differential value of the alternating current components of the photocurrents generated by the two detectors, so that the influence of common-mode noise is weakened.
The basic structure of the balanced detector is that a Trans-Impedance Amplifier (TIA) is connected to an output i of fig. 1, and a difference value of alternating current components of photocurrents output by the detector PD1 and the detector PD2 is converted into a voltage to be output. However, the operating voltage of a TIA is typically low (typically below 5V) and due to the two couplersThe difference of the path splitting light and the responsivity of the detector PD1 and the detector PD2 also have difference, so that the current i generated by the detector PD1 1 With the current i generated by the detector PD2 2 The dc component of (a) is unequal such that the current input to TIA contains a dc component, and the dc component generated by detector PD1 is about 100 μ a different from the dc component generated by detector PD 2. If the TIA has a gain of 50k, when a dc current of 100 μ Α is input to the TIA, a voltage of 5V is generated, which causes the TIA to be always in a saturation state, so that the balance detector cannot output a valid signal.
To avoid that the TIA is always in saturation, a prior art balanced detector is shown in fig. 2. In FIG. 2, the first end of detector PD1 is V +, and the second end of detector PD2 is V-, and V + and V-are equal and opposite in magnitude. The balance detector adopts two-stage amplification circuits for amplification, taking the total gain of 50K as an example, the first-stage amplification circuit adopts TIA (three-dimensional interactive application) with the gain of 2K, and the second-stage amplification circuit adopts an amplification circuit with the gain of 25 times, so that the total gain of 50K is achieved. Because the gain of the first-stage amplifying circuit is small, even if a direct-current component exists at the input of the first-stage amplifying circuit, the amplified direct-current component can not cause the TIA to be in a saturation state. A blocking capacitor C is arranged at the output end of the first-stage amplifying circuit, and is used for filtering out a direct current component in the output of the first-stage amplifying circuit, and at the moment, the direct current component input by the second-stage amplifying circuit is approximately 0 and can be ignored.
However, the balanced detector using two stages of amplification circuits can amplify the noise of both amplification circuits, and the signal-to-noise ratio of the output signal of the balanced detector is low.
Disclosure of Invention
One of the purposes of the embodiment of the invention is to improve the signal-to-noise ratio of the output signal of the balance detector while avoiding the influence on the balance detector caused by the unequal direct current components of the two detectors.
To achieve the above object, an embodiment of the present invention provides a balanced detector, including: first detector, second detector, amplifying unit and direct current bypass, wherein: a second end of the first detector is coupled with a first end of the second detector; the input end of the amplifying unit is coupled with the second end of the first detector, the first end of the second detector and the direct current bypass; the direct current bypass is suitable for guiding the direct current components output by the first detector and the second detector; the direct current component and the direct current bypass form a loop to stabilize the voltage at the input end of the amplifying unit.
Optionally, the second end of the first detector outputs a first dc component pointing to the input end of the amplifying unit, the first end of the second detector outputs a second dc component pointing to the first end thereof, and the first dc component and the second dc component have opposite directions; when the first direct-current component is larger than the second direct-current component, the compensation voltage of the direct-current bypass is reduced; when the first DC component is smaller than the second DC component, the compensation voltage of the DC bypass is increased.
Optionally, the dc bypass includes a seventh resistor and a compensation module; when the first direct current component is larger than the second direct current component, the compensation voltage at the output end of the compensation module is reduced; when the first direct current component is smaller than the second direct current component, the compensation voltage at the output end of the compensation module is increased.
Optionally, the amplifying unit includes a first differential amplifier; the compensation module comprises an integration circuit; the first input terminal of the integrating circuit is coupled to the first output terminal of the first differential amplifier, the second input terminal of the integrating circuit is coupled to the second output terminal of the first differential amplifier, and the output terminal of the integrating circuit is coupled to the seventh resistor.
Optionally, the integration circuit includes: first integral unit, first integral capacitor and second integral capacitor, wherein: the first integrating unit has a first input terminal coupled to the first output terminal of the first differential amplifier, a second input terminal coupled to the second output terminal of the first differential amplifier, and an output terminal coupled to the first terminal of the seventh resistor; a first end of the first integration capacitor is coupled with a first input end of the first integration unit, and a second end of the first integration capacitor is grounded; the first end of the second integration capacitor is coupled to the second input end of the first integration unit, and the second end of the second integration capacitor is coupled to the output end of the second integration capacitor.
Optionally, the first output terminal of the first differential amplifier is a positive output terminal, and the second output terminal of the first differential amplifier is a negative output terminal; the first input end of the first integration unit is a positive input end, and the second input end of the first integration unit is a negative input end.
Optionally, a first end of the seventh resistor is coupled to the output end of the compensation module, and a second end of the seventh resistor is coupled to the input end of the amplification unit.
Optionally, a first end of the dc bypass is coupled to the input end of the amplifying unit, and a second end of the dc bypass is grounded.
Optionally, when the first dc component is greater than the second dc component, the dc bypass guides the dc component to form a loop with a second end of the dc bypass.
Optionally, the dc bypass includes: third blocking capacitor and sixth resistance, wherein: a first end of the third blocking capacitor is coupled to the second end of the first detector and the first end of the second detector, and a second end of the third blocking capacitor is coupled to the input end of the amplifying unit; and a first end of the sixth resistor is coupled with a first end of the third dc blocking capacitor, and a second end of the sixth resistor is grounded.
Optionally, the balanced detector further comprises: first blocking capacitance and second blocking capacitance, wherein: a first end of the first blocking capacitor is coupled with the first output end of the amplifying unit, and a second end of the first blocking capacitor is coupled with the first output end of the balance detector; and a first end of the second blocking capacitor is coupled with the second output end of the amplifying unit, and a second end of the second blocking capacitor is coupled with the second output end of the balance detector.
Optionally, the balanced detector further comprises: a buffer circuit coupled with the amplifying unit.
Optionally, the buffer circuit includes: buffer cell, first feedback unit and second feedback unit, wherein: the first input terminal of the buffer unit is coupled to the first terminal of the first feedback unit, the first output terminal thereof is coupled to the second terminal of the first feedback unit, the second input terminal thereof is coupled to the first terminal of the second feedback unit, and the second output terminal thereof is coupled to the second terminal of the second feedback unit.
Optionally, the first feedback unit includes a first compensation capacitor and a first feedback resistor, where: a first end of the first compensation capacitor is coupled to the first end of the first feedback unit, and a second end of the first compensation capacitor is coupled to the second end of the first feedback unit; the first end of the first feedback resistor is coupled to the first end of the first compensation capacitor, and the second end of the first feedback resistor is coupled to the second end of the first compensation capacitor.
Optionally, the second feedback unit includes a second compensation capacitor and a second feedback resistor, where: a first end of the second compensation capacitor is coupled to the first end of the second feedback unit, and a second end of the second compensation capacitor is coupled to the second end of the second feedback unit; the first end of the second feedback resistor is coupled to the first end of the second compensation capacitor, and the second end of the second feedback resistor is coupled to the second end of the second compensation capacitor.
Optionally, the buffer circuit further includes: a fourth resistor and a fifth resistor, wherein: the first end of the fourth resistor is coupled with the first output end of the amplifying unit, and the second end of the fourth resistor is coupled with the first input end of the buffer unit; a first end of the fifth resistor is coupled to the second output end of the amplifying unit, and a second end of the fifth resistor is coupled to the second input end of the buffering unit.
Optionally, the buffer unit includes a second differential amplifier.
The embodiment of the invention also provides a frequency modulation continuous wave radar, which comprises: a light source, a beam splitter, a mixer, and a balanced detector according to any of the above, wherein: the light source is suitable for emitting light, and the light is frequency-modulated continuous laser; the optical splitter is suitable for separating local oscillation light and detection light from the light; the frequency mixer is suitable for mixing the echo light reflected by the obstacle by the detection light and the local oscillator light to obtain a beat frequency optical signal; and the balance detector is suitable for receiving the beat frequency optical signal and converting the beat frequency optical signal into an electric signal.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the direct current bypass is coupled with the input end of the amplifying unit, and the direct current component output by the first detector and the direct current component output by the second detector are guided by arranging the direct current bypass, so that the direct current component and the direct current bypass form a loop, the voltage at the input end of the amplifying unit is further ensured to be stable, and the amplifying unit is not influenced by the direct current component. Therefore, only one stage of amplification unit needs to be arranged in the balanced detector, so that the signal-to-noise ratio of the output signal of the balanced detector is high.
Furthermore, two differential output ends of the first differential amplifier are respectively coupled with two input ends of the first integrating unit, the input end of the first differential amplifier is coupled with the output end of the first integrating unit, and the voltage difference output by the two differential output ends of the first differential amplifier is fed back to the input end of the first differential amplifier through the first integrating unit, so that the direction of the first direct current component and the second direct current component is guided, and the voltage stability of the input end of the first differential amplifier is ensured.
In addition, a buffer circuit is arranged, the buffer circuit can limit the output bandwidth of the amplifying unit, the amplitude of out-of-band output signals is reduced, the system stability is improved, and unnecessary interference signals are attenuated.
Drawings
FIG. 1 is a schematic diagram of coherent detection of a prior art balanced detector;
FIG. 2 is a schematic diagram of a prior art balanced detector;
FIG. 3 is a schematic diagram of a balanced detector in an embodiment of the invention;
FIG. 4 is a schematic diagram of the operation of a balanced detector in an embodiment of the present invention;
FIG. 5 is a schematic diagram of the operation of another balanced detector in an embodiment of the invention;
FIG. 6 is a schematic diagram of another balanced detector in an embodiment of the invention;
FIG. 7 is a schematic diagram of a structure of yet another balanced detector in an embodiment of the invention;
FIG. 8 is a schematic diagram of a further balanced detector in an embodiment of the invention;
FIG. 9 is a schematic diagram of a further balanced detector in an embodiment of the invention;
fig. 10 is a schematic diagram of a frequency modulated continuous wave radar in an embodiment of the present invention.
Detailed Description
As described in the background, in the prior art, a balanced detector with two stages of TIAs is used, and the signal-to-noise ratio of the output signal is low.
In the embodiment of the invention, the direct current bypass is coupled with the input end of the amplifying unit, and the direct current components output by the first detector and the second detector are guided by arranging the direct current bypass, so that the direct current components and the direct current bypass form a loop, and the voltage at the input end of the amplifying unit is further ensured to be stable, and the amplifying unit is not influenced by the direct current components. Therefore, only one stage of amplifying unit is needed to be arranged in the balance detector, so the signal-to-noise ratio of the output signal of the balance detector is high.
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanying figures are described in detail below.
The embodiment of the present invention provides a balance detector, and the following describes the balance detector provided in the embodiment of the present invention in detail.
In a particular implementation, the balanced detector may include a first detector, a second detector, an amplification unit, and a dc bypass.
In an embodiment of the present invention, a first terminal of the first detector may be connected to a first power source, a second terminal of the second detector may be connected to a second power source, and the second terminal of the first detector is coupled to the first terminal of the second detector. The output voltage of the first power supply is equal to and opposite to the output voltage of the second power supply.
The input of the amplifying unit may be coupled to the second terminal of the first detector and the first terminal of the second detector, and to the dc bypass.
The direct current bypass can guide the direct current component output by the first detector and the direct current component output by the second detector, and the direct current component and the direct current bypass can form a loop, so that the voltage at the input end of the amplifying unit is stabilized.
In an embodiment of the present invention, the second end of the first detector outputs a first dc component, and the first dc component is directed to the input end of the amplifying unit. That is, the second terminal of the first detector outputs a first direct current component, and the first direct current component is output to the input terminal of the amplifying unit. The first end of the second detector outputs a second direct current component, and the second direct current component is directed to the first end of the second detector. When the first direct current component is larger than the second direct current component, the compensation voltage of the direct current bypass is reduced; conversely, when the first dc component is smaller than the second dc component, the compensation voltage of the dc bypass increases.
In an embodiment of the present invention, the dc bypass may include a seventh resistor and a compensation module. The input end of the compensation module is coupled with the output end of the amplifying unit, and the output end of the compensation module is coupled with the seventh resistor. The seventh resistor may be coupled between the compensation module and the input terminal of the amplifying unit.
Preferably, when the first dc component is greater than the second dc component, the compensation voltage output by the output terminal of the compensation module decreases; more preferably, when the first dc component is smaller than the second dc component, the compensation voltage output by the output terminal of the compensation module increases.
The structure of the above-described balance detector will be specifically described below. Referring to fig. 3, a circuit structure diagram of a balanced detector in an embodiment of the present invention is shown.
In the embodiment of the present invention, a first end of the first detector PD1 is connected to a first power supply, a second end of the first detector PD1 is coupled to a first end of the second detector PD2, and an output voltage of the first power supply is V1; the second end of the second detector PD2 is connected to a second power supply, and the output voltage of the second power supply is V2.
In an embodiment of the present invention, V1-V2 may enable the first detector PD1 and the second detector PD2 to operate in a linear state, respectively.
The output voltage V1 of the first power supply may be in anti-phase with the output voltage V2 of the second power supply, and the magnitude of V1 is equal to V2. Alternatively, the output voltage V1 of the first power supply may be inverted with respect to the output voltage V2 of the second power supply, but the magnitude of V1 is not equal to V2.
The amplifying unit comprises a first differential amplifier 10, the first differential amplifier 10 comprising an input terminal and a first output terminal OUT + and a second output terminal OUT-. In the dc bypass, the compensation module includes an integration circuit. The integration circuit includes a first integration unit 20, a first integration capacitance C11, and a second integration capacitance C12.
The input terminals of the first differential amplifier 10 may be coupled to the second terminal of the first detector PD1 and the first terminal of the second detector PD 2; the first output terminal OUT + of the first differential amplifier 10 is a positive output terminal of the first differential amplifier 10, and is coupled to the first input terminal of the first integrating unit 20; the second output OUT-of the first differential amplifier 10 is a negative output of the first differential amplifier 10 and is coupled to a second input of the first integrating unit 20.
The first input of the first integration unit 20 is the positive input of the first integration unit "+", and the second input of the first integration unit 20 is the negative input of the second integration unit "-".
An output terminal of the first integrating unit 20 is coupled to a first terminal of a seventh resistor R7, and a second terminal of the seventh resistor R7 is coupled to an input terminal of the first differential amplifier 10.
A first end of the first integrating capacitor C11 is coupled to a first input end of the first integrating unit 20, and a second end of the first integrating capacitor C11 is grounded.
A first terminal of the second integrating capacitor C12 is coupled to a second input terminal of the first integrating unit 20, and a second terminal of the second integrating capacitor C12 is coupled to an output terminal of the second integrating unit.
In a specific implementation, the dc bypass may further include a first resistor R21 and a second resistor R22, where: a first end of the first resistor R21 is coupled to the first output end of the first differential amplifier 10, a second end of the first resistor R21 is coupled to the first input end of the first integrating unit 20, and a first end of the first integrating capacitor C11 is coupled to the second end of the first resistor R21; a first terminal of the second resistor R22 is coupled to the second output terminal of the first differential amplifier 10, a second terminal of the second resistor R22 is coupled to the second input terminal of the first integrating unit 20, and a first terminal of the second integrating capacitor C12 is coupled to the second terminal of the second resistor R22.
The operation of the balanced detector provided in fig. 3 will be described with reference to fig. 4 to 5.
In a specific implementation, the output currents of the first detector PD1 and the second detector PD2 each include a dc component and an ac component, and for convenience of describing the technical solution of the present invention, only the dc component will be described below.
The direct current output by the first detector PD1 includes a first direct current component, the direct current output by the second detector PD2 includes a second direct current component, and the directions of the first direct current component and the second direct current component are the same and are both the directions in which V1 points to V2.
If the first dc component is greater than the second dc component, there is a dc component in the total output current of the first detector PD1 and the second detector PD2, which is directed toward the input end of the first differential amplifier 10, at this time, the output voltage of the positive output end of the first differential amplifier 10 decreases, and the output voltage of the negative output end of the first differential amplifier 10 is greater than the output voltage of the positive output end thereof, that is: the input voltage at the negative input of first integrating unit 20 is greater than the input voltage at the positive input of first integrating unit 20.
When the input voltage of the negative input terminal of the first integration unit 20 is greater than the input voltage of the positive input terminal thereof, the output voltage of the first integration unit 20 decreases, and the voltage at the point B (i.e. the output terminal of the first integration unit 20) is less than the voltage at the point a (i.e. the input terminal of the first differential amplifier 10), so that the total output dc current i of the first detector PD1 and the second detector PD2 is as shown in fig. 4 1 Leading to the output of the first integrator unit 20, forming i in fig. 4 1 The compensation loop shown (i.e., directing the total output dc current from point a to point B).
On the contrary, if the first dc component is less than the second dc component, the total output current of the first detector PD1 and the second detector PD2 has a dc component with a direction opposite to that of the first differential amplifier 10, at this time, the output voltage of the positive output terminal of the first differential amplifier 10 increases, and the output voltage of the positive output terminal of the first differential amplifier 10 is greater than the output voltage of the negative output terminal thereof, that is: the input voltage at the positive input of the first integrating unit 20 is greater than the input voltage at the negative input of the first integrating unit 20.
Referring to fig. 5, if no dc bypass is used, a dc component i directed from the input of the first differential amplifier 10 to the PD2 is generated 2 ' causing a change in the voltage at the input of the first differential amplifier 10.
With the dc bypass of the present invention, when the input voltage of the positive input terminal of the first integration unit 20 is greater than the input voltage of the negative input terminal of the first integration unit 20, the voltage at the output terminal of the first integration unit 20 increases, and the voltage at the point B is higher than the voltage at the point a, so as to guide the total output dc current of the first detector PD1 and the second detector PD2 to the input terminal of the first differential amplifier 10, thereby forming i in fig. 5 2 The compensation loop shown, (i.e., the total output current is directed from point B to point a).
If the first dc component is equal to the second dc component, no dc component exists in the total output current of the first detector PD1 and the second detector PD2, the voltage amplitude output by the positive output end of the first differential amplifier 10 is equal to the voltage amplitude output by the negative output end, and the output end of the first integrating unit 20 outputs stably. At this time, the voltage at point B is the same as that at point a.
It can be seen that, by the dc bypass, no matter whether the total output dc current is directed from point B to point a or from point a to point B, compensation can be performed by the dc bypass, so that the voltage at the input terminal of the first differential amplifier 10 is kept stable. No matter how the output currents of the two detectors change, the input end voltage of the first differential amplifier 10 can be stabilized at the initial setting voltage all the time, and will not be influenced by the total output direct current of the two detectors to fluctuate. Therefore, the first differential amplifier 10 does not saturate due to the dc component existing in the total output current of the two detectors, and thus ac information can be stably and reliably output during detection.
In the embodiment of the present invention, a first end of the dc bypass may also be coupled to the input terminal of the amplifying unit, and a second end of the dc bypass is grounded. When the first dc component is greater than the second dc component, the dc bypass may guide the dc component to form a loop with the second end of the dc bypass, thereby stabilizing the voltage at the input end of the amplifying unit.
Referring to fig. 6, a schematic diagram of another balanced detector in an embodiment of the invention is shown.
The dc bypass may comprise a third dc blocking capacitor C23 and a sixth resistor R26, wherein:
a first end of a third dc blocking capacitor C23 is coupled to the second end of the first detector PD1 and the first end of the second detector PD2, and a second end of the third dc blocking capacitor C23 is coupled to the input end of the amplifying unit 10;
a first terminal of the sixth resistor R26 is coupled to the first terminal of the third dc-blocking capacitor C23, and a second terminal of the sixth resistor R26 is grounded.
By providing the third dc blocking capacitor C23, a dc blocking effect can be achieved, and a dc component is prevented from being input to the amplifying unit 10. By providing the sixth resistor R26 for conducting direct current.
When the first dc component is larger than the second dc component, there is a dc component in the total output current of the first detector PD1 and the second detector PD2, which is directed toward the input terminal of the first differential amplifier 10. The dc component towards the input of the first differential amplifier 10 is led to ground through a dc bypass, thereby keeping the voltage at the input of the first differential amplifier 10 stable.
In a particular implementation, the balanced detector may also include a buffer circuit. The buffer circuit may be coupled to the output of the amplifying unit to limit the output bandwidth of the amplifying unit within a predetermined bandwidth range.
Referring to fig. 7, a schematic structural diagram of another balanced detector in the embodiment of the present invention is shown.
In a specific implementation, the buffer circuit may include a buffer unit 30, a first feedback unit, and a second feedback unit. In an embodiment of the present invention, the buffer unit 30 may be a second differential amplifier.
In the embodiment of the present invention, a first input terminal of the buffer unit 30 is coupled to a first terminal of the first feedback unit, a second input terminal of the buffer unit 30 is coupled to a first terminal of the second feedback unit, a first output terminal of the buffer unit 30 is coupled to a second terminal of the first feedback unit, and a second output terminal of the buffer unit 30 is coupled to a second terminal of the second feedback unit.
Specifically, the first input terminal of the buffer unit 30 is a positive input terminal, and the second input terminal is a negative input terminal.
Specifically, a first output terminal of the buffer unit 30 serves as a first output terminal of the balanced detector, and a second output terminal of the buffer unit 30 serves as a second output terminal of the balanced detector.
In the embodiment of the present invention, the first feedback unit may include a first compensation capacitor C31 and a first feedback resistor R31, wherein:
a first terminal of the first compensation capacitor C31 is coupled to the first terminal of the first feedback unit, and a second terminal of the first compensation capacitor C31 is coupled to the second terminal of the first feedback unit;
a first terminal of the first feedback resistor R31 is coupled to a first terminal of the first compensation capacitor C31, and a second terminal of the first feedback resistor R31 is coupled to a second terminal of the first compensation capacitor C31.
As can be seen from fig. 7, the first compensation capacitor C31 is connected in parallel with the first feedback resistor R31.
In the embodiment of the present invention, the second feedback unit may include a second compensation capacitor C32 and a second feedback resistor R32, wherein:
a first terminal of the second compensation capacitor C32 is coupled to the first terminal of the second feedback unit, and a second terminal of the second compensation capacitor C32 is coupled to the second terminal of the second feedback unit;
a first terminal of the second feedback resistor R32 is coupled to a first terminal of the second compensation capacitor C32, and a second terminal of the second feedback resistor R32 is coupled to a second terminal of the second compensation capacitor C32.
As can be seen from fig. 7, the second compensation capacitor C32 is connected in parallel with the second feedback resistor R32.
In the embodiment of the present invention, the bandwidth limiting circuit can limit the system bandwidth within a certain range, and the corresponding high-frequency cutoff frequency f can be approximated as:
wherein, the capacitance values of the first compensation capacitor and the second compensation capacitor are equal, and C is the capacitance value of the first compensation capacitor C31/the second compensation capacitor C32; the resistance of the first feedback resistor is equal to the resistance of the second feedback resistor, and R is the resistance of the first feedback resistor R331/the second feedback resistor R32.
By arranging the buffer circuit, the bandwidth of the system can be limited, the amplitude of the out-of-band output signal is reduced, the stability of the system is increased, and unnecessary interference signals are attenuated. Further, by selecting different capacitance values C, the high-frequency cut-off frequency of the bandwidth limiting circuit can be adjusted, and the system bandwidth can be adjusted. In addition, the buffer circuit can also play a role in buffering, so that the output level of the balance detector is matched with a sampling circuit at the later stage.
In a specific implementation, the buffer circuit may further include a fourth resistor R24 and a fifth resistor R25, where:
a first terminal of the fourth resistor R24 is coupled to the first output terminal of the first differential amplifier 10, and a second terminal of the fourth resistor R24 is coupled to the first input terminal of the buffer unit 30;
a first terminal of the fifth resistor R25 is coupled to the second output terminal of the first differential amplifier 10, and a second terminal of the fifth resistor R25 is coupled to the second input terminal of the buffer unit 30.
With continued reference to fig. 7, in a specific implementation, the balanced detector further includes a third resistor R23. The third resistor R23 may function as impedance matching between the first differential amplifier 10 and the buffer unit 30.
In a specific implementation, the balanced detector may further include a first dc blocking capacitor and a second dc blocking capacitor, where:
the first end of the first blocking capacitor is coupled with the first output end of the amplifying unit, and the second end of the first blocking capacitor is used as the first output end of the balance detector;
the first end of the second blocking capacitor is coupled with the second output end of the amplifying unit, and the second end of the second blocking capacitor is used as the second output end of the balance detector.
Through setting up first blocking capacitor and second blocking capacitor, can keep apart the direct current level in the two output end output signal of amplifying unit, eliminate the influence of direct current level to buffer circuit and back level sampling circuit.
Referring to fig. 8, a schematic structural diagram of another balanced detector in an embodiment of the present invention is shown.
In fig. 8, the balanced detector may further include a first dc blocking capacitor C21 and a second dc blocking capacitor C22, where:
a first end of the first dc blocking capacitor C21 is coupled to the first output end OUT + of the first differential amplifier 10, and a second end of the first dc blocking capacitor C21 serves as a first output end of the balanced detector; a first terminal of the second dc blocking capacitor C22 is coupled to the second output terminal OUT-of the first differential amplifier 10, and a second terminal of the second dc blocking capacitor C22 serves as a second output terminal of the balanced detector.
Referring to fig. 9, a schematic diagram of a structure of another balanced detector in an embodiment of the present invention is shown. In fig. 9, compared with fig. 7, the first dc blocking capacitance C21 and the second dc blocking capacitance C2 are added to fig. 7.
In summary, in the embodiment of the present invention, the dc bypass is coupled to the input end of the amplifying unit, and the dc component output by the first detector and the dc component output by the second detector are guided by the dc bypass, so that the dc component and the dc bypass form a loop, thereby ensuring that the voltage at the input end of the amplifying unit is stable, and the amplifying unit is not affected by the dc component. Therefore, only one stage of amplification unit needs to be arranged in the balanced detector, so that the signal-to-noise ratio of the output signal of the balanced detector is high.
Referring to fig. 10, a schematic structural diagram of a frequency modulated continuous wave radar in an embodiment of the present invention is shown. The frequency modulated continuous wave radar may comprise: light source 110, beam splitter 120, mixer 150, and balanced detector 160, wherein:
the light source 110 is adapted to emit light, which is frequency modulated continuous laser light;
the optical splitter 120 is adapted to separate local oscillation light and probe light from the light;
the mixer 150 is adapted to mix the echo light reflected by the obstacle with the local oscillator light to obtain a beat frequency optical signal;
the balance detector 160 is adapted to receive the beat frequency light signal and convert the beat frequency light signal into an electrical signal.
In this embodiment of the present invention, the mixer 150 may specifically be the coupler in fig. 1, the local oscillator light and the echo light are mixed in the coupler to obtain a beat frequency optical signal, and the coupler outputs the beat frequency optical signal with a splitting ratio of 50. The specific structure of the optical balance detector 160 may refer to the optical balance detection provided in the above embodiment of the present invention, and two beams of light output by the coupler are respectively received by the first detector PD1 and the second detector PD2, and are converted into electrical signals, which are output by the amplifying unit, which is not described herein again.
In the embodiment of the present invention, the fm continuous wave radar further includes an amplifier 130, as shown in fig. 10, the amplifier 130 is coupled downstream of the optical path of the optical splitter 120, and amplifies the probe light output by the optical splitter 120, so as to improve the power of the probe light and improve the distance measurement capability of the radar. In other embodiments of the present invention, the amplifier 130 may be coupled between the optical source 110 and the optical splitter 120, and amplify the light emitted from the optical source and then separate the local oscillation light and the probe light.
In the embodiment of the present invention, the fm continuous wave radar is an in-line radar, that is, the probe light and the echo light may share an optical system (not shown), such as a collimating lens or a lens set, and the fm continuous wave radar further includes an isolator 140 adapted to isolate the transceiver optical path. The detection light is input from the first port and output from the second port of the isolator 140 after being amplified, and is emitted after being collimated by the optical system; the echo light reflected by the obstacle is received by the radar, focused by the optical system and then input into the isolator 140 through the second port, and the isolator 140 outputs the echo light from the third port, so that the echo light path is isolated from the detection light path. The echo light output from the third port and the local oscillation light output from the optical splitter 120 are input to the mixer 150, and a beat optical signal is obtained.
The separator 140 is not limited to the circulator shown in fig. 10, and may be another optical separating device.
According to the frequency modulation continuous wave radar, the balance detector provided by the embodiment of the invention is adopted to guide the direct current components output by the first detector and the second detector, so that the direct current components and the direct current bypass form a loop, and the voltage at the input end of the amplification unit is further ensured to be stable. Even if the mixer 150 has a direct current component in the total output current of the two detectors due to the difference in the split light, the input terminal voltage of the amplifying unit is not affected by the direct current component, and can be stabilized at the initial setting voltage, thereby stably and accurately outputting the alternating current signal. Furthermore, the frequency modulation continuous wave radar can obtain the distance and speed information of the obstacle after processing and calculation according to the alternating current information in the beat frequency optical signal, and has high detection accuracy.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A balanced detector, comprising: first detector, second detector, amplifying unit and direct current bypass, wherein:
a second end of the first detector is coupled to a first end of the second detector;
the input end of the amplifying unit is coupled with the second end of the first detector, the first end of the second detector and the direct current bypass;
the direct current bypass is suitable for guiding the direct current components output by the first detector and the second detector;
the direct current component and the direct current bypass form a loop to stabilize the voltage at the input end of the amplifying unit.
2. The balanced detector as claimed in claim 1, wherein the second terminal of the first detector outputs a first dc component directed to the input of the amplification unit, and the first terminal of the second detector outputs a second dc component directed to the first terminal thereof, the first dc component being opposite to the second dc component; when the first direct current component is larger than the second direct current component, the compensation voltage of the direct current bypass is reduced; when the first direct current component is smaller than the second direct current component, the compensation voltage of the direct current bypass is increased.
3. The balanced detector of claim 2, wherein the dc bypass includes a seventh resistor and a compensation module; when the first direct current component is larger than the second direct current component, the compensation voltage at the output end of the compensation module is reduced; when the first direct current component is smaller than the second direct current component, the compensation voltage at the output end of the compensation module is increased.
4. The balanced detector of claim 3, wherein the amplifying unit includes a first differential amplifier; the compensation module comprises an integrating circuit; the first input terminal of the integrating circuit is coupled to the first output terminal of the first differential amplifier, the second input terminal of the integrating circuit is coupled to the second output terminal of the first differential amplifier, and the output terminal of the integrating circuit is coupled to the seventh resistor.
5. The balanced detector of claim 4, wherein the integration circuit comprises: first integral unit, first integral capacitor and second integral capacitor, wherein:
the first integrating unit has a first input terminal coupled to the first output terminal of the first differential amplifier, a second input terminal coupled to the second output terminal of the first differential amplifier, and an output terminal coupled to the first terminal of the seventh resistor;
a first end of the first integration capacitor is coupled with a first input end of the first integration unit, and a second end of the first integration capacitor is grounded;
the first end of the second integration capacitor is coupled to the second input end of the first integration unit, and the second end of the second integration capacitor is coupled to the output end of the second integration capacitor.
6. The balanced detector of claim 5, wherein the first output of the first differential amplifier is a positive going output and the second output of the first differential amplifier is a negative going output; the first input end of the first integration unit is a positive input end, and the second input end of the first integration unit is a negative input end.
7. The balanced detector according to any of claims 3 to 6, characterized in that the seventh resistor has a first terminal coupled to the output of the compensation module and a second terminal coupled to the input of the amplification unit.
8. The balanced detector of claim 2, wherein the dc bypass has a first terminal coupled to the input terminal of the amplifying cell and a second terminal connected to ground.
9. The balanced detector of claim 8, wherein the dc bypass directs the dc component into a loop with a second end of the dc bypass when the first dc component is greater than the second dc component.
10. The balanced detector of claim 9, wherein the dc bypass includes: third blocking capacitor and sixth resistance, wherein:
a first end of the third blocking capacitor is coupled with a second end of the first detector and a first end of the second detector, and a second end of the third blocking capacitor is coupled with an input end of the amplifying unit;
and a first end of the sixth resistor is coupled to the first end of the third dc blocking capacitor, and a second end of the sixth resistor is grounded.
11. The balanced detector of claim 1, further comprising: first blocking capacitance and second blocking capacitance, wherein:
a first end of the first blocking capacitor is coupled to the first output end of the amplifying unit, and a second end of the first blocking capacitor is coupled to the first output end of the balanced detector;
and a first end of the second blocking capacitor is coupled with the second output end of the amplifying unit, and a second end of the second blocking capacitor is coupled with the second output end of the balance detector.
12. The balanced detector of claim 1, further comprising: a buffer circuit coupled with the amplifying unit.
13. The balanced detector of claim 12, wherein the buffer circuit comprises: buffer cell, first feedback unit and second feedback unit, wherein:
the first input terminal of the buffering unit is coupled to the first terminal of the first feedback unit, the first output terminal thereof is coupled to the second terminal of the first feedback unit, the second input terminal thereof is coupled to the first terminal of the second feedback unit, and the second output terminal thereof is coupled to the second terminal of the second feedback unit.
14. The balanced detector of claim 13, wherein the first feedback unit comprises a first compensation capacitor and a first feedback resistor, wherein:
a first end of the first compensation capacitor is coupled to the first end of the first feedback unit, and a second end of the first compensation capacitor is coupled to the second end of the first feedback unit;
the first end of the first feedback resistor is coupled to the first end of the first compensation capacitor, and the second end of the first feedback resistor is coupled to the second end of the first compensation capacitor.
15. The balanced detector according to claim 13, wherein the second feedback unit comprises a second compensation capacitor and a second feedback resistor, wherein:
a first end of the second compensation capacitor is coupled to the first end of the second feedback unit, and a second end of the second compensation capacitor is coupled to the second end of the second feedback unit;
the first end of the second feedback resistor is coupled to the first end of the second compensation capacitor, and the second end of the second feedback resistor is coupled to the second end of the second compensation capacitor.
16. The balanced detector of claim 13, wherein the buffer circuit further comprises: a fourth resistor and a fifth resistor, wherein:
the first end of the fourth resistor is coupled with the first output end of the amplifying unit, and the second end of the fourth resistor is coupled with the first input end of the buffer unit;
a first end of the fifth resistor is coupled to the second output end of the amplifying unit, and a second end of the fifth resistor is coupled to the second input end of the buffering unit.
17. The balanced detector of claim 13, wherein the buffer cell includes a second differential amplifier.
18. A frequency modulated continuous wave radar, comprising: a light source, a beam splitter, a mixer, and a balanced detector according to any of claims 1 to 17, wherein:
the light source is suitable for emitting light, and the light is frequency-modulated continuous laser;
the optical splitter is suitable for separating local oscillation light and detection light from the light;
the frequency mixer is suitable for mixing the echo light reflected by the obstacle by the detection light and the local oscillator light to obtain a beat frequency optical signal;
and the balance detector is suitable for receiving the beat frequency optical signal and converting the beat frequency optical signal into an electric signal.
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| CN202111016005.XA CN115728723A (en) | 2021-08-31 | 2021-08-31 | Balanced detector and frequency modulation continuous wave radar |
| PCT/CN2022/077585 WO2023029393A1 (en) | 2021-08-31 | 2022-02-24 | Balanced detector and frequency modulation continuous wave radar |
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| CN202111016005.XA CN115728723A (en) | 2021-08-31 | 2021-08-31 | Balanced detector and frequency modulation continuous wave radar |
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| CN104539373A (en) * | 2014-12-30 | 2015-04-22 | 天津大学 | High-speed CMOS monolithic integration light receiver front end of cross coupling structure |
| CN105157829B (en) * | 2015-05-15 | 2017-04-26 | 山西大学 | Low-frequency balanced zero beat photodetector |
| WO2019161388A1 (en) * | 2018-02-16 | 2019-08-22 | Xiaotian Steve Yao | Optical sensing based on wavelength division multiplexed (wdm) light at different wavelengths in light detection and ranging lidar systems |
| CN110779623A (en) * | 2019-11-07 | 2020-02-11 | 山西大学 | Balanced zero-beat detector integrated with locking branch |
| CN110806586B (en) * | 2020-01-08 | 2020-04-14 | 杭州爱莱达科技有限公司 | Non-scanning linear frequency modulation continuous wave speed and distance measuring laser three-dimensional imaging method and device |
| CN111397858B (en) * | 2020-04-04 | 2021-03-30 | 山西大学 | Balanced zero-beat detector |
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