CN115688643A

CN115688643A - Method, apparatus and storage medium for simulating logic system design

Info

Publication number: CN115688643A
Application number: CN202211298231.6A
Authority: CN
Inventors: 朱梦雅; 请求不公布姓名
Original assignee: Core Huazhang Technology Beijing Co ltd
Current assignee: Core Huazhang Technology Beijing Co ltd
Priority date: 2022-10-21
Filing date: 2022-10-21
Publication date: 2023-02-03

Abstract

The application provides a method, equipment and a storage medium for designing a simulation logic system. The method comprises the following steps: obtaining a description of the logic system design, wherein the logic system design includes combinational logic circuitry; determining a circuit structure of the combinational logic circuit based on the description of the logic system design; determining an expression of the circuit structure; modifying the description of the logic system design based on the expression; and simulating the modified logic system design.

Description

Method, apparatus and storage medium for simulating logic system design

Technical Field

The present application relates to the field of computer software technologies, and in particular, to a method, a device, and a storage medium for designing a simulation logic system.

Background

In the field of verification of integrated circuits, simulation may refer to compiling a logic system design and then running it using a simulation tool to perform simulation tests on various functions of the design. The design may be, for example, a design for an Application Specific Integrated Circuit (ASIC) or System-On-Chip (SOC) for a Specific Application. Therefore, a Design to be tested or verified in simulation may also be referred to as a Design Under Test (DUT).

A logic system design may generally include a circuit and may provide a module definition for the circuit. The simulation tool may instantiate the module definition during the simulation process, thereby generating an instantiated circuit module. During the simulation process, the large number of circuit connections between instantiated circuit blocks may consume a large amount of computing resources, slowing down the simulation speed.

Therefore, how to optimize the circuit connection before the simulation starts, so as to speed up the simulation is a problem to be solved.

Disclosure of Invention

A first aspect of the present application provides a method of simulating a logic system design, the method comprising: obtaining a description of the logic system design, wherein the logic system design includes combinational logic circuitry; determining a circuit structure of the combinational logic circuit based on the description of the logic system design; determining an expression of the circuit structure; modifying the description of the logic system design based on the expression; and simulating the modified logic system design.

A second aspect of the present application provides an electronic device comprising: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method of the first aspect.

A third aspect of the application provides a non-transitory computer readable storage medium storing a set of instructions of a computer for, when executed, causing the computer to perform the method of the first aspect.

According to the method, the device and the storage medium for designing the simulation logic system, the simplest circuit expression of the combinational logic circuit can be obtained by analyzing the split combinational logic circuit. The simulation tool can replace the description of the combinational logic circuit with the simplest circuit expression before simulation, and then directly simulate the modified logic system design. Therefore, the simulation tool can directly simulate the simplest circuit expression, so that the original combinational logic circuit is prevented from being instantiated in the simulation, and the simulation of the logic system design is accelerated.

Drawings

In order to more clearly illustrate the technical solutions in the present application or the related art, the drawings needed to be used in the description of the embodiments or the related art will be briefly introduced below, and it is obvious that the drawings in the following description are only embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 shows a schematic structural diagram of an exemplary electronic device according to an embodiment of the present application.

FIG. 2A shows a schematic diagram of an exemplary simulation tool according to an embodiment of the present application.

FIG. 2B illustrates a schematic diagram of an exemplary compiler, according to an embodiment of the present application.

FIG. 3A shows a schematic diagram of an exemplary logic system design according to an embodiment of the present application.

Fig. 3B shows a schematic diagram of an exemplary circuit structure according to an embodiment of the present application.

FIG. 3C shows a schematic diagram of an exemplary process of modifying a logic system design, according to an embodiment of the present application.

Fig. 3D shows a schematic diagram of an exemplary modified circuit structure according to an embodiment of the application.

FIG. 4 shows a flowchart of a method of simulating a logic system design according to an embodiment of the application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below with reference to the accompanying drawings in combination with specific embodiments.

It is to be noted that, unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which this application belongs. As used in this application, the terms "first," "second," and the like do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" and similar words are intended to mean that the elements or items listed before they occur in the word "comprise" and the equivalents thereof, without excluding other elements or items. "connected," and like terms, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Fig. 1 shows a schematic structural diagram of an electronic device 100 according to an embodiment of the present application. The electronic device 100 may be an electronic device running a simulation tool. As shown in fig. 1, the electronic device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Wherein the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively coupled to each other within the electronic device via a bus 110.

The processor 102 may be a Central Processing Unit (CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits. The processor 102 may be used to perform functions associated with the techniques described herein. In some embodiments, processor 102 may also include multiple processors integrated into a single logic component. As shown in FIG. 1, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, the simulation test system for simulating a test design may be a computer program stored in memory 104. As shown in fig. 1, the data stored by the memory may include program instructions (e.g., for implementing the methods of simulating a logic system design of the present application) as well as data to be processed (e.g., the memory may store temporary code generated during the compilation process). The processor 102 may also access memory-stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include volatile memory devices or non-volatile memory devices. In some embodiments, the memory 104 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSDs), flash memory, memory sticks, and the like.

The network interface 106 may be configured to provide communications with other external devices to the electronic device 100 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the above. It is to be understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, and the like.

The peripheral interface 108 may be configured to connect the electronic device 100 with one or more peripheral devices to enable input and output of information. For example, the peripheral devices may include input devices such as keyboards, mice, touch pads, touch screens, microphones, various sensors, and output devices such as displays, speakers, vibrators, indicator lights, and the like.

The bus 110 may be configured to transfer information between various components of the electronic device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (a USB port, a PCI-E bus), and so forth.

It should be noted that although the electronic device architecture described above only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in a specific implementation, the electronic device architecture may also include other components necessary to achieve normal operation. In addition, it can be understood by those skilled in the art that the electronic device architecture described above may also include only the components necessary to implement the embodiments of the present application, and not necessarily all the components shown in the drawings.

FIG. 2A shows a schematic diagram of an exemplary simulation tool 200 according to an embodiment of the present disclosure. The simulation tool 200 may be a computer program running on the electronic device 100.

In the field of chip design, a design may be simulated using a simulation tool. The simulation tool may be, for example, a GalaxSim simulation tool available from Chihua chapter science and technology, inc. The exemplary simulation tool 200 shown in FIG. 2A may include a compiler 210 and a simulator 220. Compiler 210 can receive source code 204 (e.g., a hardware description language such as VHDL, verilog, systemveilog, etc.) and compile into execution code 206 (e.g., machine code, assembly code, software code, etc.). It is understood that the description of the logic system design may be described in a Hardware Description Language (HDL), a Register Transfer Level (RTL) language, binary code, assembly code, or machine code, among others. The simulator 220 may simulate according to the execution code 206 and output the simulation result 208. For example, simulation tool 200 may output simulation results 208 to an output device (e.g., displayed on a display) via peripheral interface 108 of FIG. 1.

Fig. 2B is a diagram of an exemplary compiler 210 according to an embodiment of the present application. As shown in FIG. 2B, compiler 210 may include a front end 212, a middle end 214, and a back end 216.

Front end 212 may be used to analyze the lexical, syntactic, semantic properties of the source code according to a particular source language.

After lexical, grammatical, and semantic analysis of the source code is complete, the middle-end 214 may convert the source code into an intermediate representation (or intermediate code) and may optimize the intermediate representation. An intermediate language (intermediate code) is a syntax-oriented, equivalent internal representation code that is easily translated into source code for a target program. The understandability and the easy generation degree of the execution code are between the source code and the execution code. Commonly used intermediate codes are represented by inverse wave, quaternary, ternary, tree, etc. For example, the middle end 214 may remove useless code, remove inaccessible code, clear unused variables, and the like. The optimization may include machine dependent optimization and machine independent optimization. Among other things, machine-related optimization, for example, may be optimization of a Testbench (TB), and may utilize some of the Testbench's characteristics to assist in the optimization. The machine-independent optimization may be, for example, an optimization of a Design Under Test (DUT). The optimized intermediate representation may then be passed to the back end 126 for further processing.

The back end 216 may further optimize the intermediate representation according to the architecture of the target processor (e.g., processor 102 of FIG. 1) and generate execution code. Typically, the executing code is machine code.

It is to be understood that the structure of the compiler is not limited to the example of fig. 2B. For example, front end 212 and middle end 214 may be collectively referred to as the front end of a compiler.

The compiler 210 may generate execution code based on the computer code to be compiled. The computer code to be compiled may also be referred to as source code, such as a written logic system design. Typically, the source language in which the source code is written is a high level programming language. The high-level programming language may be a software programming language or a hardware programming language as described above. The execution code may be, for example, assembly code, machine code, or the like. In general, the compiler 210 may be stored in the memory 104 shown in FIG. 1 and executed by the processor 102 to compile a logic system design into executable code. Compiler 210 may convert the description of the logic system design from a high-level language description (e.g., an HDL language) to a lower-level description (e.g., an RTL language or binary code) so that the underlying hardware can run the logic system design.

As described above, when simulating a circuit in a logic system design, a simulation tool may generate instantiated circuit blocks, causing the circuit connections between the instantiated circuit blocks to consume significant computing resources, slowing simulation speed. How to optimize the circuit connection before the simulation starts so as to accelerate the simulation is a problem to be solved urgently. In order to solve the above problems, the present application provides a method for designing a simulation logic system.

FIG. 3A shows a schematic diagram of an exemplary logic system design 300, according to an embodiment of the present application.

Compiler 210 in simulation tool 200 may obtain a description of logic system design 300 before simulator 220 performs the simulation process. The description may be, for example, source code 204 in FIG. 2A written in a hardware description language such as VHDL, verilog, systemVerilog, or the like. As shown in FIG. 3A, logic system design 300 may generally include sequential logic circuit 301 and combinational logic circuit 302. The logic function of the combinational logic circuit 302 is characterized in that the output at any time is only dependent on the input at that time, and is independent of the original state of the circuit. The sequential logic circuit 301 has a logic function characteristic that the output at any time depends not only on the input signal at that time, but also on the original state of the circuit and the clock signal. That is, the output of sequential logic circuit 301 is related to previous inputs (i.e., related to timing).

Simulation tool 200 may consider an "always block" in code driven by a clock signal (i.e., the "clk" signal) as a sequential logic circuit portion; accordingly, the simulation tool 200 may consider the portion of the code that is not driven by the "clk" signal to be a combinational logic circuit portion. It should be noted that, when determining whether a signal in the circuit is driven by the "clk" signal, the simulation tool 200 not only needs to determine whether the signal is driven by the "clk" signal at the current time, but also needs to trace back to determine that the signal is not driven by the "clk" signal at the previous time. In response to the signal not being driven by the "clk" signal at all times, simulation tool 200 may determine the signal to be that of the combinational logic circuit portion. In this way, the simulation tool 200 can extract the description of the sequential logic circuit 301 and the description of the combinational logic circuit 302, respectively.

Simulation tool 200 may compile the description of combinational logic circuit 302 into intermediate code. Simulation tool 200 may also obtain information associated with sequential logic circuit 301 and combinational logic circuit 302. For example, the correlation information may be that the output of the sequential logic circuit 301 may be used as one of the inputs of the combinational logic circuit 302, the output of the combinational logic circuit 302 may be fed back to the sequential logic circuit 301, and so on. The information associated with the sequential logic circuit 301 and the combinational logic circuit 302 may be used in subsequent simulation processes performed by the simulation tool 200 to design a logic system.

Fig. 3B shows a schematic diagram of an exemplary circuit structure 310 according to an embodiment of the application.

Based on the description of logic system design 300, simulation tool 200 may determine a circuit structure 310 of combinational logic circuit 302. In some embodiments, the combinational logic circuit 302 may include a plurality of circuit blocks. For convenience of description, the embodiment of the present application is illustrated as a combinational logic circuit 302 composed of one and gate 3021 and one not gate 3022, wherein an output of the and gate 3021 may be an input of the not gate 3022.

Simulation tool 200 may obtain signals "1", "a" and "c" of AND gate 3021. Simulation tool 200 may also obtain signals "c" and "b" of not gate 3022. Accordingly, in the case where signals "1", "a", "c", and "b" are acquired, the simulation tool 200 may determine that the gates associated with these signals are the and gate 3021 and the not gate 3022. The simulation tool 200 may obtain the connection relationship between the and gate 3021 and the not gate 3022 according to the relationship that the output of the and gate 3021 may be the input of the not gate 3022.

Thus, as shown in fig. 3B, the simulation tool 200 may determine the simplest circuit structure of the combinational logic circuit 302 according to the signals "1", "a", "c", and "B" based on the connection relationship between the and gate 3021 and the not gate 3022. It should be noted that although specific instantiated and gate 3021 and not gate 3022 (shown in dashed outline) are shown in fig. 3B, this is merely for visually illustrating the circuit structure of the combinational logic circuit 302 and does not mean that the actual instantiation process is performed on the combinational logic circuit 302 in the simulation tool 200.

In this example, simulation tool 200 may determine the expression for the simplest circuit structure of combinational logic circuit 302 in the following manner. The input signals of the and gate 3021 are "1" and "a", and the output signal is "c = a &1". The input signal of the not gate 3022 is "c", and the output signal is "b = not (c)". Since the output signal "c" of the and gate 3021 is an input signal of the not gate 3022, the simulation tool 200 can combine the two identical signals "c". The simulation tool 200 may determine that the circuit configuration of the combinational logic circuit 302 has an expression of "b = not (a & 1)". Since the output signal "c = a &1" of and gate 3021 depends only on signal "a", simulation tool 200 may further determine that the most probable expression of the circuit structure of combinational logic circuit 302 is "b = not (a)".

Generally speaking, simulation tool 200 may simplify combinational logic circuit 302 in logic system design 300 for at least two reasons. First, a user typically describes the behavior of a circuit when writing logic system design 300 using a Hardware Description Language (HDL), rather than describing the structure of the circuit. Therefore, the simulation tool 200 generates corresponding circuits in modules when performing synthesis, and these circuits are not necessarily the simplest circuits, let alone, further provides space for optimization when the combinational logic circuits of a plurality of modules are combined together. Second, the simulation tool 200 does not initially know the value of each signal when performing the synthesis. After simulation tool 200 obtains more information about the value of the signal, simulation tool 200 has the ability to simplify combinatorial logic 302. Thus, the examples of FIGS. 3A-3B are merely exemplary. It will be appreciated that the simplification of the simulation tool 200 to the combinational logic circuit 302 does not necessarily result in the simplest circuit.

FIG. 3C shows a schematic diagram of an exemplary process 320 for modifying a logic system design, according to an embodiment of the present application. Simulation tool 200 may replace the description of combinational logic circuit 302 in logic system design 300 with the determined most probable expression of the circuit structure of combinational logic circuit 302 "b = not (a)". The description of the combinational logic circuit 302 herein may be the compiled intermediate code described previously.

Fig. 3D shows a schematic diagram of an exemplary modified circuit structure 330 according to an embodiment of the application.

During the simulation of logic system design 300, simulation tool 200 may instantiate "b = not (a)" directly, resulting in combinational logic circuit 332 (i.e., a not gate with "a" input signal and "b" output signal). Based on the correlation information that "the output of sequential logic circuit 301 can be used as one of the inputs of combinational logic circuit 302, and the output of combinational logic circuit 302 can be fed back to sequential logic circuit 301", simulation tool 200 can generate the connection relationship between combinational logic circuit 332 and sequential logic circuit 301 corresponding to the most simple expression "b = not (a)". For example, the connection relationship may be that the output "a" of the sequential logic circuit 301 may be used as an input to the combinational logic circuit 332, and the output "b" of the combinational logic circuit 332 may be fed back to the sequential logic circuit 301 as an input.

Thus, during simulation, simulation tool 200 need not instantiate two circuit blocks that produce connected AND gate 3021 and NOT gate 3022, but may directly instantiate the most simple expression "b = not (a)" to obtain combinational logic circuit 332 including one NOT gate. By adopting the method provided by the application, the simulation tool 200 can simplify circuit connection, further reduce the occupation of the circuit connection on computing resources and accelerate the simulation speed.

FIG. 4 illustrates a flow diagram of a method 400 of simulating a logic system design according to an embodiment of the application. Method 400 may be implemented by electronic device 100 shown in FIG. 1, and more specifically, by a simulation tool (e.g., simulation tool 200 in FIG. 2A) running on electronic device 100. The method 400 may include the following steps.

At step 402, simulation tool 200 may obtain a description of the logic system design (e.g., logic system design 300 in FIG. 3A), where the logic system design may include combinational logic circuits (e.g., combinational logic circuit 302 in FIG. 3A).

At step 404, simulation tool 200 may determine the circuit structure of the combinational logic circuit based on the description of the logic system design. In some embodiments, the combinational logic circuit may include a plurality of circuit blocks (e.g., and gate 3021 and not gate 3022 in fig. 3B). Simulation tool 200 may obtain signals (e.g., signals "1", "a", "c", and "B" in fig. 3B) for the plurality of circuit modules; determining the gate circuit associated with the signal (e.g., and gate 3021 associated with signals "1", "a", "c" and not gate 3022 associated with signals "c", "B" in fig. 3B); acquiring the connection relation of the gate circuit (for example, the output of the and gate 3021 in fig. 3B is the input of the not gate 3022); and a circuit configuration of the combinational logic circuit (for example, the circuit configuration of the combinational logic circuit 302 in fig. 3B) is generated according to the connection relationship of the signal and the gate circuit.

It should be noted that the and gate 3021 and the not gate 3022 outlined by dashed lines in fig. 3B are only for visually illustrating the circuit structure of the combinational logic circuit 302, and do not mean that the simulation tool 200 actually instantiates the combinational logic circuit 302.

At step 406, simulation tool 200 may determine an expression for the circuit structure. In some embodiments, the simulation tool 200 may look for the same signal in the gate circuit (e.g., the output signal "c" of the and gate 3021 and the input signal "c" of the not gate 3022 in fig. 3B). Simulation tool 200 may determine an expression for the circuit structure based on the same signal (e.g., expressions "c = a &1" and "b = not (c) based on signal" c ").

In some embodiments, simulation tool 200 may combine the same signals to determine an expression for the circuit structure (e.g., combining signal "c" results in the expression "b = not (a & 1)"). In some embodiments, the expression for the circuit structure may be a simplest expression (e.g., the expression "b = not (a & 1)" may be further reduced to a simplest expression "b = not (a)")

At step 408, the simulation tool 200 may modify the description of the logic system design based on the expression. In some embodiments, simulation tool 200 may replace the description of the combinational logic circuit with the most probable expression (e.g., replace combinational logic circuit 302 with the most probable expression "b = not (a)" shown in FIG. 3C).

In some embodiments, simulation tool 200 may compile the description of the combinational logic circuit into intermediate code; and replacing the intermediate code with the most probable expression.

At step 410, simulation tool 200 may simulate the modified logic system design (e.g., modified logic system design 320 shown in FIG. 3C).

In some embodiments, the logic system design may further include a sequential logic circuit (e.g., sequential logic circuit 301 in fig. 3A or 3B), and simulation tool 200 may further obtain information associated with the combinational logic circuit (e.g., "output of sequential logic circuit 301 in fig. 3B may be used as one of inputs of combinational logic circuit 302, and output of combinational logic circuit 302 may be fed back to sequential logic circuit 301"); and generating a connection relationship between a circuit (e.g., the combinational logic circuit 332 in fig. 3D) corresponding to the expression (e.g., the expression "b = not (a)") and the sequential logic circuit (e.g., the sequential logic circuit 301 in fig. 3D) according to the association information (e.g., a connection relationship in which "the output" a "of the sequential logic circuit 301 in fig. 3D may be an input of the combinational logic circuit 332, and the output" b "of the combinational logic circuit 332 may be fed back to the sequential logic circuit 301 as an input").

The embodiment of the application also provides the electronic equipment. The electronic device may be the electronic device 100 of fig. 1. The electronic device 100 may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform method 400.

Embodiments of the present application also provide a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores a set of instructions of a computer for causing the electronic device to perform the method 400 when executed.

Some embodiments of the present application are described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the context of the present application, technical features in the above embodiments or in different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the present application described above, which are not provided in detail for the sake of brevity.

While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures, such as Dynamic RAM (DRAM), may use the discussed embodiments.

The present application is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalents, improvements, and the like that may be made without departing from the spirit or scope of the present application are intended to be included within the scope of the claims.

Claims

1. A method of simulating a logic system design, comprising:

obtaining a description of the logic system design, wherein the logic system design comprises a combinational logic circuit;

determining a circuit structure of the combinational logic circuit based on the description of the logic system design;

determining an expression of the circuit structure;

modifying the description of the logic system design based on the expression; and

simulating the modified logic system design.

2. The method of claim 1, wherein the combinational logic circuit includes a plurality of circuit blocks, the determining a circuit structure of the combinational logic circuit based on the description of the logic system design further comprising:

acquiring signals of the plurality of circuit modules;

determining a gate associated with the signal;

acquiring the connection relation of the gate circuit; and

and generating the circuit structure of the combinational logic circuit according to the connection relation between the signal and the gate circuit.

3. The method of claim 2, wherein determining the expression for the circuit structure further comprises:

searching for the same signal in the gate circuit; and

determining an expression for the circuit structure based on the same signal.

4. The method of claim 3, wherein determining an expression for the circuit structure based on the same signal further comprises:

combining the same said signals to determine an expression for the circuit configuration.

5. A method as claimed in any one of claims 1 to 4, wherein the expression of the circuit structure is a best-effort expression.

6. The method of claim 5, wherein modifying the description of the logic system design based on the expression further comprises:

replacing the description of the combinational logic circuit with the most recent expression.

7. The method of claim 6, wherein replacing the description of the combinational logic circuit with the most probable expression further comprises:

compiling the description of the combinational logic circuit into intermediate code; and

replacing the intermediate code with the most probable expression.

8. The method of claim 1, wherein the logic system design further comprises sequential logic circuitry, the method further comprising:

acquiring the associated information of the combinational logic circuit and the sequential logic circuit; and

and generating the connection relation between the circuit corresponding to the expression and the sequential logic circuit according to the associated information.

9. An electronic device, comprising:

a memory for storing a set of instructions; and

at least one processor configured to execute the set of instructions to cause the electronic device to perform the method of any of claims 1-8.

10. A non-transitory computer readable storage medium storing a set of instructions of an electronic device, which when executed, cause the electronic device to perform the method of any of claims 1 to 8.