CN115617715A - FIFO device and data transmission method thereof - Google Patents
FIFO device and data transmission method thereof Download PDFInfo
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- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
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Abstract
The invention provides an FIFO device and a data transmission method thereof, comprising a write bit width indicating port, a write data port, a register file and a write control module; a write bit width indication port for receiving a bit width identifier of data to be written; a write data port for receiving a write request signal and data to be written; the register file comprises a plurality of registers, and each register is used for storing data with the minimum bit width; and the write control module is used for writing the data to be written into the register file according to the bit width of the data to be written, the bit width of the data written at the current time, the minimum bit width and the current pointing position of the write pointer, and updating the position of the write pointer. The invention fully utilizes the space of the FIFO to achieve the purpose of saving area, and the resource consumption is equivalent to that of the traditional FIFO.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to an FIFO device and a data transmission method thereof.
Background
The FIFO device is a data buffer widely used in ASIC design, and has the characteristic of first-in first-out, i.e. data entering the FIFO device first is read out, and the exit sequence is consistent with the entry sequence, and is generally used to buffer some information such as commands, data, etc.
The existing FIFO device usually has a structure of single channel, multiple channels and M-in N-out, the single channel FIFO device is a traditional FIFO device, the bit width of input data is equal to the bit width of output data, a single channel enters and a single channel outputs, the multi-channel FIFO device is characterized in that multiple channels enter and 1 or more channels output, and the M-in N-out FIFO device is characterized in that the bit width of the input data is different from the bit width of the output data. However, with the change of practical application scenarios, the data access method of the existing FIFO device cannot meet the real requirements, the existing FIFO device can only support writing data with a fixed bit width each time, and when the bit width of the written data is smaller than the fixed bit width of the FIFO device, the waste of storage space is caused.
Disclosure of Invention
The invention aims to provide an FIFO device and a data transmission method thereof, and solve the technical problems that the conventional FIFO device can only support the writing of data with a fixed bit width at each time, and when the bit width of the written data is smaller than the fixed bit width of the FIFO device, the storage space is wasted.
On one hand, the invention provides an FIFO device supporting various write bit widths, which comprises a write bit width indicating port, a write data port, a register file and a write control module;
the write bit width indication port is used for receiving a bit width identifier of data to be written, and the bit width identifier is used for determining the bit width of the data to be written at the current time;
the write data port is used for receiving a write request signal and data to be written;
the register file comprises a plurality of registers, and each register is used for storing data with a minimum bit width;
and the write control module is used for writing the data to be written into the register file according to the bit width of the data to be written, the bit width of the data written at the current time, the minimum bit width and the current pointing position of the write pointer, and updating the position of the write pointer.
Preferably, the write control module is specifically configured to:
determining the number of registers required by the current write-in data according to the bit width of the current write-in data and the minimum bit width of the register file;
writing the data to be written into the registers with the number corresponding to the number of the registers in the register file by taking the current pointing position of a write pointer as an initial position;
updating the pointing position of the write pointer by taking the number of the registers as the increment of the write pointer;
and repeating the steps of determining the number of the registers, writing the data to be written into the registers and updating the write pointer until the writing of the data to be written is completed.
Preferably, the method further comprises the following steps: an empty-full indication control module;
the empty and full indication control module is used for counting the data storage quantity of the plurality of registers and generating empty and full indication signals according to the data storage quantity, wherein the empty and full indication signals comprise empty signals and full signals;
the write control module is specifically configured to prohibit writing of the data to be written into the register file when the empty-full indication signal is a full signal; and when the empty and full indication signal is an empty signal, writing the data to be written into the register file, and writing the data to be written into the registers of which the number corresponds to the number of the registers in the register file according to the number of the registers and the current pointing position of the write pointer.
Preferably, the bit width identifier includes B kinds of preset identifiers, and the B kinds of preset identifiers correspond to different bit widths respectively; b is more than or equal to 2;
the empty and full indication control module is specifically configured to:
when at least B registers in the register file do not store data, generating an empty-full indication signal as an empty signal;
when all registers in the register file store data, generating an empty-full indication signal as a first full signal;
when only 1 register in the register file stores no data, generating an empty-full indication signal as a second full signal.
Preferably, the write control module is specifically configured to:
when the empty-full indication signal is a first full signal, forbidding to write the data to be written into the register file;
and when the empty-full indication signal is a second full signal, judging whether the number of registers required for storing the data to be written is equal to 1, if so, writing the data to be written into a register which does not store the data in the register file according to the current pointing position of a write pointer, and if not, forbidding to write the data to be written into the register file.
Preferably, the apparatus further comprises:
a read data port to receive a read request signal;
the read control module is used for reading data from the register file according to a first-in first-out principle when the read data port receives the read request signal and outputting the read data to the read data port; and updating the read pointer.
Preferably, the apparatus further comprises:
a clock port for receiving a clock signal;
the write enable port is used for receiving a write enable signal to activate the data write function of the FIFO device;
the read enable port is used for receiving a read enable signal to activate the data reading function of the FIFO device.
The second aspect of the present invention further provides a data transmission method, where the method includes:
the write data port receives a write request signal and data to be written, the write bit width indication port receives a bit width identifier of the data to be written, and the bit width identifier is used for determining the bit width of the data to be written at the current time;
and the write control module writes the data to be written into the register file according to the bit width of the data to be written, the bit width of the data written at the current time, the minimum bit width and the current pointing position of the write pointer, and updates the position of the write pointer.
Preferably, the writing the data to be written into the register file according to the bit width of the data to be written, the bit width of the data written at the current time, the minimum bit width, and the current pointing position of the write pointer, and updating the position of the write pointer specifically includes:
determining the number of registers required by the current write-in data according to the bit width of the current write-in data and the minimum bit width of the register file;
writing the data to be written into the registers with the number corresponding to the number of the registers in the register file by taking the current pointing position of a write pointer as an initial position;
updating the pointing position of the write pointer by taking the number of the registers as the increment of the write pointer;
and repeating the steps of determining the number of the registers, writing the data to be written into the registers and updating the write pointer until the writing of the data to be written is completed.
Preferably, the method further comprises:
the empty and full indication control module counts the data storage quantity of the plurality of registers and generates empty and full indication signals according to the data storage quantity, wherein the empty and full indication signals comprise empty signals and full signals;
when the empty-full indication signal is a full signal, the write control module prohibits the data to be written from being written into the register file;
and when the empty and full indication signal is an empty signal, the write control module writes the data to be written into the register file, and writes the data to be written into registers of which the number corresponds to the number of the registers in the register file according to the number of the registers and the current pointing position of the write pointer.
Preferably, the bit width identifier includes B kinds of preset identifiers, and the B kinds of preset identifiers correspond to different bit widths respectively; b is more than or equal to 2;
the generating of the empty and full indication signal according to the data storage quantity specifically includes:
when at least B registers in the register file do not store data, generating an empty full indication signal as an empty signal;
when all registers in the register file store data, generating an empty-full indication signal as a first full signal;
when only 1 register in the register file stores no data, generating an empty-full indication signal as a second full signal.
Preferably, when the empty-full indication signal is a full signal, the writing control module prohibits writing of the data to be written into the register file, specifically including:
when the empty-full indication signal is a first full signal, forbidding to write the data to be written into the register file;
and when the empty-full indication signal is a second full signal, judging whether the number of registers required for storing the data to be written is equal to 1, if so, writing the data to be written into a register which does not store data in the register file according to the current pointing position of a write pointer, and if not, forbidding to write the data to be written into the register file.
Preferably, the method further comprises:
the read data port receives a read request signal;
when the read data port receives the read request signal, the read control module reads data from the register file according to a first-in first-out principle and outputs the read data to the read data port; and updating the read pointer.
The invention has the following beneficial effects:
according to the FIFO device supporting various write bit widths and the data transmission method thereof, when data to be written are input, the bit width identification of the data to be written is input at the same time, the write control module determines the bit width of the data to be written according to the bit width identification of the data to be written, and determines the number (depth) of registers required for storing the data to be written according to the bit width of the data to be written, so that the memory granularity is subdivided in the FIFO device, the writing of the data with various bit widths is supported, the maximum utilization of the space of the FIFO device is ensured, and meanwhile, the writing is not performed precisely to each bit, so that the complex logic cannot be increased.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is within the scope of the present invention for those skilled in the art to obtain other drawings based on the drawings without inventive labor.
FIG. 1 is a diagram of a FIFO device supporting multiple write bit widths according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating the write pointer update before and after writing data in a conventional FIFO device.
FIG. 3 is a schematic diagram of the read pointer updating before and after reading data of the conventional FIFO device.
FIG. 4 is a diagram illustrating update of a write pointer before and after writing data according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating update of read pointers before and after reading data according to an embodiment of the present invention.
Fig. 6 is a main flow chart of a data transmission method according to an embodiment of the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of an embodiment of a FIFO device supporting multiple write bit widths according to the present invention. In this embodiment, the FIFO device supporting a plurality of write bit widths includes: the device comprises a write bit width indicating port, a write data port, an empty and full indicating control module, a write control module and a register file;
the write bit width indication port is used for receiving a bit width identifier of data to be written, and the bit width identifier is used for determining the bit width of the data written at the current time;
the write data port is used for receiving a write request signal and data to be written;
the register file comprises a plurality of registers, and each register is used for storing data with a minimum bit width;
and the write control module is used for writing the data to be written into the register file according to the bit width of the data to be written, the bit width of the data written at the current time, the minimum bit width and the current pointing position of the write pointer, and updating the position of the write pointer.
The write control module is respectively connected with the write bit width indication port, the write data port, the write enable port, the memory stack and the empty and full indication control module, and is used as a control core of the FIFO device to process write-in request signals and write-in data, process bit width identification signals and update a write pointer. One end of the empty and full indication control module is connected with the write control module, the read control module and the register file, and the other end of the empty and full indication control module outputs an empty and full indication signal, namely, the empty and full state of the register file is judged. One end of the reading control module is connected with the register file and the empty and full indication control module, and the other end of the reading control module is connected with the reading data port and the reading enabling port and used for updating a reading pointer and outputting the reading data.
In a specific embodiment, the write control module is specifically configured to determine the number of registers needed for writing data at the current time according to the bit width of the data written at the current time and the minimum bit width of the register file; writing the data to be written into the registers with the number corresponding to the number of the registers in the register file by taking the current pointing position of a write pointer as an initial position; updating the pointing position of the write pointer by taking the number of the registers as the increment of the write pointer; and repeating the steps of determining the number of the registers, writing the data to be written into the registers and updating the write pointer until the writing of the data to be written is completed.
It should be noted that, the depth value of each register in the register file is set to a preset minimum bit width, where the preset minimum bit width specifically refers to the minimum unit in which the depth of each register can be stored in this embodiment. In this embodiment, the bit width identifier specifically indicates that different bit widths are to be written in data identified by a digital formula, for example: the bit width of the data to be written is represented by a bit width identifier 1 as a/2, and the bit width of the data to be written is represented by a bit width identifier 0 as a, which is described in detail in the following contents of the write bit width indication port, and is not described herein again. Fig. 2 is a schematic diagram of updating a write pointer before and after writing data in a conventional FIFO device, and fig. 3 is a schematic diagram of updating a read pointer before and after reading data in a conventional FIFO device, referring to fig. 2-3, a register of the conventional FIFO device has a bit width a and a depth N; on the basis of keeping the total depth of the conventional FIFO device to be N, correspondingly, in the embodiment of the present invention, assuming that the embodiment of the present invention needs to support storage of data with bit width a/2 and bit width a at the same time, 2N registers are correspondingly set, the depth value of each register is set to be a/2, and it needs to occupy 2 depths to store one data with bit width a.
It should be noted that the minimum bit width here may be understood as a/B, and when data is written, the bit width of the written data needs to be an integer multiple of the a/B, where a refers to the minimum bit width set in a conventional FIFO device, B refers to an integer greater than or equal to 2, when B takes 2, a/2 is the minimum bit width in this embodiment, when B takes 3, a/3 is the minimum bit width in this embodiment, and so on, the minimum bit width depends on a specific value of B, and meanwhile, the value of B may be set according to a specific practical application situation. Therefore, the minimum bit width is a/B, which varies with the B value, and there may be a variety of write bit widths, for example: b =3, the writing bit width can be supported to be three bit widths A/3,2A/3,A; b =2, then write bit width a and bit width a/2 may be supported. Fig. 4 is a schematic diagram of updating of the write pointer before and after writing data when B =2, and shows a register storage situation and a write pointer updating situation when the bit width of the write data is a and a/2. Fig. 5 is a schematic diagram of updating of write pointers before and after reading data when B =2, and shows a register storage situation and a read pointer updating situation when the read data bit width is a and a/2.
Further, the FIFO device of the embodiment of the invention further includes:
a read data port to receive a read request signal;
the read control module is used for reading data from the register file according to a first-in first-out principle when the read data port receives the read request signal and outputting the read data to the read data port; updating the read pointer;
a clock port for receiving a clock signal;
the write enable port is used for receiving a write enable signal to activate the data write function of the FIFO device;
the read enable port is used for receiving a read enable signal to activate the data reading function of the FIFO device.
Specifically, the write control module is responsible for controlling the writing of data when a write request exists, and writes the data into the register file according to the write pointer and the identifier of the write bit width indication port; write pointer control is also performed, which is responsible for updating the write pointer, indicating the location where the next write data is written to the register file. When a read request exists, the read control module updates the data quantity stored in the FIFO device and reads the data; and performing read pointer control, namely taking charge of updating the read pointer and pointing to the position of the data read next time in the register. The write data port and the write enable port are used in cooperation, writing is performed only when enabling is effective, and the read data port and the read enable port are the same in the same way and are not described herein again.
In a more specific embodiment, the empty and full indication control module is configured to count a data storage amount of the plurality of registers and generate an empty and full indication signal according to the data storage amount, where the empty and full indication signal includes an empty signal and a full signal.
Specifically, the empty-full indication control module is responsible for indicating how many data are stored in the current FIFO, determining according to the number of actually written data, simultaneously recording the number in units of bit width a/2, and outputting the empty and full states of the FIFO.
The specific process comprises the steps of generating an empty-full indication signal as an empty signal when at least B registers in the register file do not store data; when all registers in the register file store data, generating an empty-full indication signal as a first full signal; when only 1 register in the register file stores no data, generating an empty-full indication signal as a second full signal.
Specifically, for example, B =2 is taken as an example, and when the output empty signal is empty, it indicates that the FIFO device is not full, that is, data can be normally written, regardless of whether the data is data with a/2 bit width or data with a bit width. The full signal is at least 2, the first full signal full _0 indicates that it is fully full and cannot receive any more write data, and the second full signal full _1 indicates that it is also possible to receive one a/2-bit wide data and cannot receive one a-bit wide data. That is, when B =2, there is a case of incomplete full, that is, 1 register does not store data, in addition to a case of complete full, but at this time, if there is one a-bit wide data to be written, it is impossible to write at this time, but one a/2-bit wide data can be written. When the value of B changes, this situation is always present, but the bit width of the data that cannot be written is limited to be different, for example: and when B =3, the writing of three bit widths of A/3,2A/3 and A can be supported, 1 register stores no data and corresponds to the data with the bit width of A/3, and the data with the bit width of 2A/3, A cannot be written at this time. By analogy, when B =4, writing with four bit widths of A/4,A/2,3A/4,A can be supported, but the corresponding data with A/2,3A/4,A bit width cannot be written at this time.
In this embodiment, after the empty/full indication signal is determined, the write control module may determine whether to store data and where to store the data according to a specific storage condition. Specifically, the method comprises the following steps: when the empty-full indication signal is a full signal, forbidding to write the data to be written into the register file; and when the empty and full indication signal is an empty signal, writing the data to be written into the register file, and writing the data to be written into the registers of which the number corresponds to the number of the registers in the register file according to the number of the registers and the current pointing position of a write pointer.
In this embodiment, when determining the bit width of the write data, the write bit width indication port only needs to identify the corresponding indication signal, for example, 0 represents the write bit width a,1 represents the write bit width a/2, only needs to identify 1 or 0 to determine that the write bit width a and the bit width a/2 are supported, and needs a 1-bit indication signal. Corresponding to the identification process, when the write control module updates the write pointer, when different bit width identification signals are received, the increment of the write pointer is determined according to the different bit width identification signals, and the pointing position of the write pointer is updated. As shown in fig. 4, in the FIFO apparatus supporting multiple write bit widths in this embodiment, data of bit width a/2 and data of bit width a need to be simultaneously stored, then 2N registers are correspondingly set, a depth value of each register is set to a/2, and it takes 2 depths to store one data of bit width a. For example: the specification of the FIFO devices with various write bit widths in the embodiment is kept consistent with that of the corresponding traditional FIFO devices, meanwhile, the total depth of the FIFO is set to 4, the bit width of the FIFO is set to a, the minimum bit width of each register in the register file in the embodiment is set to a/2, the support bit widths are a/2 and a, the depth of the register file (the number of registers) is set to 8, 2 times of write operations are continuously performed, the initial position of a write pointer is D0, when data is written for the first time, the bit width is identified as 0, that is, when the bit width of the data is written for the second time is a, the FIFO pointer is incremented by 2, a jump is made from D0 to D2, and when the data is written for the second time, the bit width is identified as 1, that is, when the bit width of the data written for the second time is a/2, the FIFO pointer is incremented by 1, and a jump is made from D2 to D3. That is, each time data is written, the write data is written into the register file according to the identifier of the write bit width indication port and the write pointer, if data with bit width a is written, the write pointer is incremented by 2, and if data with bit width a/2 is written, the write pointer is incremented by 1. It can be understood that, according to the requirement, the minimum bit width a/2 is used as a basic unit to determine the number of steps that the write pointer corresponding to the written data needs to be incremented, when the write pointer corresponding to the bit width a/2 is incremented by 1, the write pointer corresponding to the bit width a is incremented by 2, and so on, the incremented number of the write pointers corresponding to the bit width values of all the written data can be determined. Compared with the conventional FIFO device shown in fig. 2, the total depth of the conventional FIFO is set to 4, the bit width of the conventional FIFO is set to a, when data with the data bit width of a is written, the write pointer is incremented by 1, a jump is made from D0 to D1, and data writing with other bit widths is not supported. In summary, when the total depth is set to 4 and the bit width is set to a, the conventional FIFO device can only support data with the written data bit width supporting only a, whereas the FIFO device in the embodiment writes data with the bit width supporting a/2 and a.
Specifically, after the write control module determines the write pointer, whether data can be written into the memory heap needs to be specifically determined according to an empty/full signal of the memory heap, that is, it needs to be determined according to an empty/full indication signal generated by the empty/full indication control module: when the empty-full indication signal is a first full signal, forbidding to write the data to be written into the register file; and when the empty-full indication signal is a second full signal, judging whether the number of registers required for storing the data to be written is equal to 1, if so, writing the data to be written into the registers which are not stored in the register file according to the number of the registers and the current pointing position of a write pointer, and if not, prohibiting the data to be written from being written into the register file. That is, whether the size of the data can be written and written is determined according to the remaining storage capacity of the specific register file, which is described in detail in the above-mentioned part of the empty-full indication signal generated by the empty-full indication control module, and is not described herein again.
In another embodiment, it is necessary to implement reading of multiple bit width data after writing of multiple bit width data, corresponding to the data writing process of the FIFO device described in the above embodiment, when reading data, taking B =2 as an example for explanation, as shown in fig. 5, it is necessary to support reading of data with bit width a/2 and bit width a at the same time, then 2N registers are correspondingly set, the depth value of each register is set to a/2, and it takes 2 depths to store one data with bit width a. For example: the specification of the FIFO device with various write bit widths in the embodiment is kept consistent with that of the corresponding traditional FIFO device, meanwhile, the total depth of the FIFO device is 4, the bit width of the FIFO device is a, the FIFO device supporting various write bit widths in the embodiment is provided, the minimum bit width of each register in the register file is set to be a/2, the support bit widths are a/2 and a, the depth of the register file is 8, 2 times of reading operation are continuously performed, the initial position of the read pointer is D0, the bit width of the data read for the first time is a, the FIFO pointer is increased by 2, the jump is made from D0 to D2, the bit width of the data read for the second time is a/2, the FIFO pointer is increased by 1, and the jump is made from D2 to D3. When reading data each time, updating the read pointer according to the identification of the data bit width of the position where the read pointer is located, for example: if the read data is the data with the bit width A, adding 2 to the read pointer, and otherwise, adding 1 to the read pointer; the bit width of the read data is read according to the sequence of writing, the FIFO principle is ensured, and only the internal read pointer jump can be updated according to the actual bit width of the data read this time. Compared with the conventional FIFO shown in fig. 3, the total depth of the conventional FIFO is set to 4, the data bit width of the conventional FIFO is a, and when data with the data bit width of a is read, the read pointer is incremented by 1, and the data read with other bit widths is not supported by jumping from D0 to D1. In summary, when the total depth is set to 4, the bit width is set to a, the conventional FIFO device can only support data whose read data bit width only supports a, whereas the FIFO device in the embodiment reads data whose bit width supports a/2 and a, subdivides the storage granularity inside the FIFO device, supports writing of data with multiple bit widths and also supports reading of data with multiple bit widths, and ensures maximum utilization of the space of the FIFO device. The principle of the read pointer update is the same as that of the write pointer update, and is not described herein again.
Fig. 6 is a schematic diagram of an embodiment of a data transmission method for a FIFO device supporting multiple write bit widths according to the present invention, where the method includes the following steps:
the method comprises the following steps that S1, a write data port receives a write request signal and data to be written, a write bit width indication port receives a bit width identification of the data to be written, and the bit width identification is used for determining the bit width of the data to be written at the current time;
and S2, the write control module writes the data to be written into the register file according to the bit width of the data to be written, the bit width of the data written at the current time, the minimum bit width and the current pointing position of the write pointer, and updates the position of the write pointer.
In a specific embodiment, the writing the data to be written into the register file by the bit width of the current write data, the minimum bit width, and the current pointing position of the write pointer, and updating the position of the write pointer specifically includes:
determining the number of registers required by current write-in data according to the bit width of the current write-in data and the minimum bit width of the register file, writing the to-be-written data into the registers with the number corresponding to the number of the registers in the register file by taking the current pointed position of a write pointer as an initial position, updating the pointed position of the write pointer by taking the number of the registers as the increment of the write pointer, repeating the steps of determining the number of the registers, writing the to-be-written data into the registers and updating the write pointer until the write-in of the to-be-written data is completed.
In this embodiment, the method further includes:
the empty and full indication control module counts the data storage quantity of the plurality of registers and generates empty and full indication signals according to the data storage quantity, wherein the empty and full indication signals comprise empty signals and full signals;
when the empty-full indication signal is a full signal, the write control module prohibits the data to be written from being written into the register file;
and when the empty and full indication signal is an empty signal, the write control module writes the data to be written into the register file, and writes the data to be written into the registers, the number of which corresponds to the number of the registers, in the register file according to the number of the registers and the current pointing position of the write pointer.
In this embodiment, the generating an empty-full indication signal according to the data storage quantity specifically includes:
when at least B registers in the register file do not store data, generating an empty-full indication signal as an empty signal;
when all registers in the register file store data, generating an empty-full indication signal as a first full signal;
when only 1 register in the register file does not store data, generating an empty-full indication signal as a second full signal, wherein the bit width identifier comprises B kinds of preset identifiers, and the B kinds of preset identifiers correspond to different bit widths respectively; b is more than or equal to 2.
Specifically, when the empty/full indication signal is a full signal, the writing control module prohibits writing of the data to be written into the register file, and specifically includes:
when the empty-full indication signal is a first full signal, forbidding to write the data to be written into the register file;
and when the empty-full indication signal is a second full signal, judging whether the number of registers required for storing the data to be written is equal to 1, if so, writing the data to be written into the register file which does not store the data according to the number of the registers and the current pointing position of a write pointer, and if not, prohibiting the data to be written from being written into the register file.
In another specific embodiment, the method further comprises:
the read data port receives a read request signal;
when the read data port receives the read request signal, the read control module reads data from the register file according to a first-in first-out principle and outputs the read data to the read data port; and updating the read pointer.
It should be noted that the method described in the foregoing embodiment corresponds to the FIFO device supporting multiple write bit widths described in the foregoing embodiment, and therefore, portions of the method described in the foregoing embodiment that are not described in detail may be obtained by referring to the contents of the FIFO device supporting multiple write bit widths described in the foregoing embodiment, and details are not described here.
In summary, the embodiment of the invention has the following beneficial effects:
the invention provides a FIFO device supporting multiple write bit widths and a data transmission method thereof, when data to be written is input, a bit width identifier of the data to be written is input at the same time, a write control module determines the bit width of the data to be written according to the bit width identifier of the data to be written, and determines the number (depth) of registers required for storing the data to be written according to the bit width of the data to be written, so that the storage granularity is subdivided in the FIFO device, the writing of the data with multiple bit widths is supported, the maximum utilization of the space of the FIFO device is ensured, and meanwhile, the writing is not performed to each bit, so that the complicated logic is not added, which is only a preferred embodiment disclosed above, and certainly, the right range of the invention cannot be limited by the logic, and therefore, the equivalent change made according to the claims of the invention still belongs to the range covered by the invention.
Claims (13)
1. The FIFO device is characterized by comprising a write bit width indicating port, a write data port, a register file and a write control module;
the write bit width indicating port is used for receiving a bit width identifier of data to be written, and the bit width identifier is used for determining the bit width of the data written at the current time;
the write data port is used for receiving a write request signal and data to be written;
the register file comprises a plurality of registers, and each register is used for storing data with a minimum bit width;
and the write control module is used for writing the data to be written into the register file according to the bit width of the data to be written, the bit width of the data written at the current time, the minimum bit width and the current pointing position of the write pointer, and updating the position of the write pointer.
2. The FIFO device of claim 1, wherein the write control module is specifically configured to:
determining the number of registers required by the current write-in data according to the bit width of the current write-in data and the minimum bit width of the register file;
writing the data to be written into the registers with the number corresponding to the number of the registers in the register file by taking the current pointing position of a write pointer as an initial position;
updating the pointing position of the write pointer by taking the number of the registers as the increment of the write pointer;
and repeating the steps of determining the number of the registers, writing the data to be written into the registers and updating the write pointer until the writing of the data to be written is completed.
3. The FIFO apparatus of claim 1 or 2, further comprising: an empty-full indication control module;
the empty and full indication control module is used for counting the data storage quantity of the plurality of registers and generating empty and full indication signals according to the data storage quantity, wherein the empty and full indication signals comprise empty signals and full signals;
the write control module is specifically configured to prohibit writing of the data to be written into the register file when the empty-full indication signal is a full signal; and when the empty and full indication signal is an empty signal, writing the data to be written into the register file, and writing the data to be written into the registers of which the number corresponds to the number of the registers in the register file according to the number of the registers and the current pointing position of the write pointer.
4. The FIFO device of claim 3,
the bit width identification comprises B kinds of preset identifications, and the B kinds of preset identifications correspond to different bit widths respectively; b is more than or equal to 2;
the empty and full indication control module is specifically configured to:
when at least B registers in the register file do not store data, generating an empty full indication signal as an empty signal;
when all registers in the register file store data, generating an empty-full indication signal as a first full signal;
when only 1 register in the register file stores no data, generating an empty-full indication signal as a second full signal.
5. The FIFO device of claim 4, wherein the write control module is specifically configured to:
when the empty-full indication signal is a first full signal, forbidding to write the data to be written into the register file;
and when the empty-full indication signal is a second full signal, judging whether the number of registers required for storing the data to be written is equal to 1, if so, writing the data to be written into a register which does not store data in the register file according to the current pointing position of a write pointer, and if not, forbidding to write the data to be written into the register file.
6. The FIFO device of any one of claims 1-5, further comprising:
a read data port to receive a read request signal;
the read control module is used for reading data from the register file according to a first-in first-out principle when the read data port receives the read request signal and outputting the read data to the read data port; and updating the read pointer.
7. The FIFO device of claim 6, further comprising:
a clock port for receiving a clock signal;
the write enable port is used for receiving a write enable signal to activate a data write function of the FIFO device;
the read enable port is used for receiving a read enable signal to activate the data reading function of the FIFO device.
8. A data transmission method implemented on the basis of the FIFO device of any one of claims 1-7, the method comprising:
the write data port receives a write request signal and data to be written, the write bit width indication port receives a bit width identifier of the data to be written, and the bit width identifier is used for determining the bit width of the data to be written at the current time;
and the write control module writes the data to be written into the register file according to the bit width of the data to be written, the bit width of the current write data, the minimum bit width and the current pointing position of the write pointer, and updates the position of the write pointer.
9. The method according to claim 8, wherein said writing the data to be written into the register file according to the bit width of the data to be written, the bit width of the data being written, the minimum bit width, and the current pointing position of the write pointer, and updating the position of the write pointer specifically includes:
determining the number of registers required by the current write-in data according to the bit width of the current write-in data and the minimum bit width of the register file;
writing the data to be written into the registers with the number corresponding to the number of the registers in the register file by taking the current pointing position of a write pointer as an initial position;
updating the pointing position of the write pointer by taking the number of the registers as the increment of the write pointer;
and repeating the steps of determining the number of the registers, writing the data to be written into the registers and updating the write pointer until the writing of the data to be written is completed.
10. The method of claim 9, wherein the method further comprises:
the empty and full indication control module counts the data storage quantity of the plurality of registers and generates empty and full indication signals according to the data storage quantity, wherein the empty and full indication signals comprise empty signals and full signals;
when the empty-full indication signal is a full signal, the write control module prohibits the data to be written from being written into the register file;
and when the empty and full indication signal is an empty signal, the write control module writes the data to be written into the register file, and writes the data to be written into the registers, the number of which corresponds to the number of the registers, in the register file according to the number of the registers and the current pointing position of the write pointer.
11. The method according to claim 10, wherein the bit width identifier includes B kinds of preset identifiers, and the B kinds of preset identifiers respectively correspond to different bit widths; b is more than or equal to 2;
the generating of the empty and full indication signal according to the data storage quantity specifically includes:
when at least B registers in the register file do not store data, generating an empty-full indication signal as an empty signal;
when all registers in the register file store data, generating an empty-full indication signal as a first full signal;
when only 1 register in the register file does not store data, generating an empty-full indication signal as a second full signal.
12. The method as claimed in claim 11, wherein said writing control module prohibits writing the data to be written into the register file when the empty-full indication signal is a full signal, specifically comprising:
when the empty-full indication signal is a first full signal, forbidding to write the data to be written into the register file;
and when the empty-full indication signal is a second full signal, judging whether the number of registers required for storing the data to be written is equal to 1, if so, writing the data to be written into a register which does not store the data in the register file according to the current pointing position of a write pointer, and if not, forbidding to write the data to be written into the register file.
13. The method of claim 8, wherein the method further comprises:
the read data port receives a read request signal;
when the read data port receives the read request signal, the read control module reads data from the register file according to a first-in first-out principle and outputs the read data to the read data port; and updating the read pointer.
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| CN117111859A (en) * | 2023-10-23 | 2023-11-24 | 北京紫光芯能科技有限公司 | Data writing method, device and equipment |
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| CN117111859A (en) * | 2023-10-23 | 2023-11-24 | 北京紫光芯能科技有限公司 | Data writing method, device and equipment |
| CN117111859B (en) * | 2023-10-23 | 2024-03-19 | 北京紫光芯能科技有限公司 | Data writing method, device and equipment |
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