CN111414148A - Mixed FIFO data storage method and device for high-performance processor - Google Patents
Mixed FIFO data storage method and device for high-performance processor Download PDFInfo
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- CN111414148A CN111414148A CN202010259365.1A CN202010259365A CN111414148A CN 111414148 A CN111414148 A CN 111414148A CN 202010259365 A CN202010259365 A CN 202010259365A CN 111414148 A CN111414148 A CN 111414148A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0647—Migration mechanisms
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Abstract
The invention discloses a mixed FIFO data storage method and device facing a high-performance processor, the device comprises an RAM memory, a selector, a register group and an FIFO controller, a FIFO data writing port is respectively connected with an input end of the RAM memory and an input end of the selector, an output end of the RAM memory is connected with the other input end of the selector, an output end of the selector is connected with a FIFO data reading port through the register group, and control ends of the RAM memory, the selector and the register group are respectively connected with the FIFO controller. The invention has the advantages of both RAM type FIFO and register type FIFO, has the characteristics of high access speed and large storage capacity, can carry out background data transfer by utilizing the channel between the RAM memory and the register group, and hides the access delay of the RAM, so that the invention has the characteristic of high access speed.
Description
Technical Field
The invention relates to the field of integrated circuit chip design, in particular to a high-performance processor-oriented mixed FIFO data storage method and device with high speed, large capacity and low area overhead, and an architecture level and a circuit level.
Background
FIFO (First In and First Out) data queues are widely used circuit structures In integrated circuit chips for buffering data, clock domain isolation, and controlling the order of data access. The FIFO can be divided into two types, a RAM type and a register type, according to memory cells. Because the number of transistors needed for constructing the RAM storage unit is small, but the time delay for accessing the RAM storage unit is high, the RAM type FIFO is suitable for a use scene with large capacity requirement and low access speed requirement; because the access delay of the register is low, but the number of transistors required for constructing the register is large, the register type FIFO is suitable for a use scene with high access speed requirement and small capacity requirement.
However, in a high-performance processor, it is necessary to satisfy both the demand for a high access speed and a large capacity by the FIFO. At this time, the existing RAM type FIFO and register type FIFO cannot satisfy the performance requirement. Therefore, how to realize the fusion of the RAM FIFO and the register FIFO becomes a key technical problem to be solved urgently.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: aiming at the problems in the prior art, the invention provides a high-performance processor-oriented mixed FIFO data storage method and device with architecture level and circuit level, high speed, large capacity and low area overhead.
In order to solve the technical problems, the invention adopts the technical scheme that:
a mixed FIFO data storage device facing a high-performance processor comprises an RAM memory, a selector, a register group and an FIFO controller, wherein FIFO data writing ports of the mixed FIFO data storage device are respectively connected with an input end of the RAM memory and one input end of the selector, an output end of the RAM memory is connected with the other input end of the selector, an output end of the selector is connected with FIFO data reading ports of the mixed FIFO data storage device through the register group, and control ends of the RAM memory, the selector and the register group are respectively connected with the FIFO controller.
Optionally, the selector is a 1-from-2 selector.
In addition, the invention also provides a microprocessor, and the microprocessor comprises the hybrid FIFO data storage device facing the high-performance processor.
In addition, the invention also provides a computer device, and the chip of the computer device comprises the hybrid FIFO data storage device facing the high-performance processor.
In addition, the present invention further provides an application method of the hybrid FIFO data storage device for a high-performance processor, wherein the FIFO controller performs FIFO write control, and the step of performing FIFO write control includes:
A1) judging whether the FIFO full mark is 0 and the FIFO write enable is 1, and if yes, skipping to execute the next step;
A2) judging whether the RAM is empty, the register group is not full, and background data transfer between the RAM and the register group does not exist currently, if so, generating register group write enable by the FIFO controller, selecting external FIFO write data by the selector, and writing the external FIFO write data into the register group after passing through the selector; otherwise, the FIFO controller generates a RAM memory write enable to write the external FIFO write data directly into the RAM memory.
Optionally, the step of performing FIFO read control by the FIFO controller includes:
B1) judging whether the FIFO empty mark is 0 and the FIFO read enable is 1, and if yes, skipping to execute the next step;
B2) judging whether the register set is empty, and if the register set is empty, skipping to execute the step B3); jumping to execute step B4 if the register set is not empty);
B3) waiting for background data transfer between the RAM memory and the register group, and jumping to execute the next step after the background data transfer between the RAM memory and the register group is completed to enable the register group to be non-empty;
B4) the FIFO controller generates a register set read enable to read FIFO read data directly from the register.
Optionally, the step of background data transfer between the RAM memory and the register set includes:
C1) judging whether the register group is not full and the RAM memory is not empty or not, and if so, skipping to execute the next step;
C2) the FIFO controller generates RAM read enable, controls the selector to select RAM read data after the RAM read is valid as 1, generates register group write enable, and carries out background data transfer from the RAM memory to the register group on the FIFO data.
Optionally, the FIFO controller further includes a step of recording read-write pointers of the RAM memory and the register group, and determining an empty-full state of the RAM memory and the register group, and an empty-full state of the entire FIFO, and the detailed steps include: when the RAM memory write enable is generated, adding 1 to a RAM memory write pointer; when the read enable of the RAM memory is generated, adding 1 to a read pointer of the RAM memory after the RAM read data are received to be valid; when the register group write enable is generated, adding 1 to a register group write pointer; when the register group read enable is generated, adding 1 to a register group read pointer; when the read-write pointers of the RAM memories are equal, the RAM memory is judged to be empty; when the read pointer of the RAM memory is equal to the write pointer plus 1, judging that the RAM memory is full; when the read-write pointers of the register group are equal, the register group is judged to be empty; when the register group read pointer is equal to the write pointer plus 1, the register group is judged to be full; when the RAM memory and the register group are both empty, judging that the FIFO is empty, setting the FIFO empty mark as 1 and the FIFO full mark as 0; when the RAM memory and the register group are full, the FIFO is judged to be full, the FIFO empty mark is set to be 0, and the FIFO full mark is set to be 1.
Compared with the prior art, the invention has the following advantages:
1. as is well known, the FIFO can be classified into two types, a RAM type and a register type, in terms of memory cells. The RAM type FIFO is suitable for use scenarios where the capacity requirement is large, but the access speed requirement is low. The register type FIFO is suitable for a use scene with high access speed requirement and small capacity requirement. In some high-performance devices, the FIFO is required to meet the requirements of high access speed and large capacity at the same time. The mixed FIFO data storage device for the high-performance processor comprises the RAM memory, the selector, the register group and the FIFO controller, and can have the advantages of the RAM type FIFO and the register type FIFO at the same time by combining the RAM type FIFO and the register type FIFO. When the data volume is less and smaller than the capacity of the register group, the hybrid FIFO only uses the register group to store data actually, and the FIFO behavior at the moment is equivalent to a register type FIFO, so that the hybrid FIFO has the characteristic of high access speed. When the data volume is larger than the capacity of the register group, the mixed FIFO uses the register group and the RAM memory to store data at the same time, so the mixed FIFO has the characteristic of large storage capacity. At this time, the hybrid FIFO hides the delay of the RAM memory access by background data transfer between the register group and the RAM memory, that is, when the register group is not full and the RAM memory is not empty, the data transfer from the RAM memory to the register group is performed inside the FIFO, so that when there is a FIFO read request, data can be directly read out from the register group, and the access speed at this time is still equivalent to that of a register type FIFO. Only when the data volume is larger than the capacity of the register group and a large number of continuous FIFO reading operations occur, the access speed of the hybrid FIFO is reduced to be equal to the RAM type FIFO speed when the data transfer from the RAM memory to the register group cannot be completed in time in the FIFO, so that the register group with enough depth can be set according to the actual use scene to reduce the occurrence probability of the situation.
2. The mixed FIFO data storage device facing the high-performance processor comprises an RAM memory, a selector, a register group and an FIFO controller, and can carry out background data transfer by utilizing a channel between the RAM memory and the register group and hide RAM access delay, so that the mixed FIFO data storage device has the characteristic of high access speed.
Drawings
FIG. 1 is a schematic diagram of a hybrid FIFO data storage device according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, the hybrid FIFO data storage device for a high-performance processor of this embodiment includes a RAM memory, a selector, a register group, and a FIFO controller, where a FIFO write data port of the hybrid FIFO data storage device is connected to an input end of the RAM memory and an input end of the selector, respectively, an output end of the RAM memory is connected to another input end of the selector, an output end of the selector is connected to a FIFO read data port of the hybrid FIFO data storage device through the register group, and control ends of the RAM memory, the selector, and the register group are connected to the FIFO controller, respectively.
Referring to fig. 1, the hybrid FIFO in the present embodiment is composed of a RAM memory, a register group, and a FIFO controller. The RAM memory and the register group are used for storing data. The RAM memory receives FIFO write data from the outside, the register group selects to receive FIFO write data from the outside or read data of the RAM memory, and the FIFO read data is provided by the register group.
In this embodiment, the selector is a 1-from-2 selector. In addition, other multi-selection selectors can be adopted as required as long as the selection of the input data of the register group and the bypass of the RAM can be realized.
In addition, the present embodiment also provides a microprocessor, which includes the hybrid FIFO data storage device for high performance processor.
In addition, this embodiment also provides a computer device, where a chip of the computer device includes the hybrid FIFO data storage device facing the high-performance processor, and the chip may be a microprocessor Chip (CPU), or may include various hardware processing chips such as a GPU, a DSP, an FPGA, and an ASIC.
The FIFO controller is used for receiving an external read-write request, generating read-write control signals of the RAM memory and the register group according to the current state, and particularly relates to the read-write control under the following three conditions: FIFO write control, FIFO read control, and background data transfer between the RAM memory and the register bank.
In this embodiment, the step of performing FIFO write control by the FIFO controller includes:
A1) judging whether the FIFO full mark is 0 and the FIFO write enable is 1, and if yes, skipping to execute the next step;
A2) judging whether the RAM is empty, the register group is not full, and background data transfer between the RAM and the register group does not exist currently, if so, generating register group write enable by the FIFO controller, selecting external FIFO write data by the selector, and writing the external FIFO write data into the register group after passing through the selector; otherwise, the FIFO controller generates a RAM memory write enable to write the external FIFO write data directly into the RAM memory.
In this embodiment, step a 1) first determines the FIFO full flag, and then determines the FIFO write enable. When the FIFO full flag is 0, FIFO write can be performed, that is, when FIFO write enable is detected to be 1, FIFO write data is written into a RAM memory or a register group. The FIFO controller judges whether to write into the RAM or register group according to the current FIFO state. And when the RAM is empty, the register group is not full, and no background data transfer exists currently (the effective reading mark of the RAM is 0), writing the data into the register group. At this time, the FIFO controller generates a register set write enable, and the selector selects the external FIFO write data. Otherwise, writing into the RAM memory. At this point, the FIFO controller generates a RAM memory write enable.
In this embodiment, the step of performing FIFO read control by the FIFO controller includes:
B1) judging whether the FIFO empty mark is 0 and the FIFO read enable is 1, and if yes, skipping to execute the next step;
B2) judging whether the register set is empty, and if the register set is empty, skipping to execute the step B3); jumping to execute step B4 if the register set is not empty);
B3) waiting for background data transfer between the RAM memory and the register group, and jumping to execute the next step after the background data transfer between the RAM memory and the register group is completed to enable the register group to be non-empty;
B4) the FIFO controller generates a register set read enable to read FIFO read data directly from the register.
Step B1) in this embodiment first determines the FIFO empty flag and then determines the FIFO read enable. When the FIFO empty flag is 0, a FIFO read may be performed, i.e., when a FIFO read enable of 1 is detected, the FIFO read data is read and the FIFO data valid bit is marked as 1. There are two cases where FIFO read data is read directly from the register when the register is not empty. At this point, the FIFO controller generates a register set read enable. When the register is empty, waiting for the completion of the last background data transfer to enable the register group to be non-empty, and then generating register group read enable.
In this embodiment, the background data transfer between the RAM memory and the register set includes:
C1) judging whether the register group is not full and the RAM memory is not empty or not, and if so, skipping to execute the next step;
C2) the FIFO controller generates RAM read enable, controls the selector to select RAM read data after the RAM read is valid as 1, generates register group write enable, and carries out background data transfer from the RAM memory to the register group on the FIFO data.
In this embodiment, the FIFO controller further includes a step of recording read-write pointers of the RAM memory and the register group, and determining empty and full states of the RAM memory and the register group, and an empty and full state of the entire FIFO, and the detailed steps include: when the RAM memory write enable is generated, adding 1 to a RAM memory write pointer; when the read enable of the RAM memory is generated, adding 1 to a read pointer of the RAM memory after the RAM read data are received to be valid; when the register group write enable is generated, adding 1 to a register group write pointer; when the register group read enable is generated, adding 1 to a register group read pointer; when the read-write pointers of the RAM memories are equal, the RAM memory is judged to be empty; when the read pointer of the RAM memory is equal to the write pointer plus 1, judging that the RAM memory is full; when the read-write pointers of the register group are equal, the register group is judged to be empty; when the register group read pointer is equal to the write pointer plus 1, the register group is judged to be full; when the RAM memory and the register group are both empty, judging that the FIFO is empty, setting the FIFO empty mark as 1 and the FIFO full mark as 0; when the RAM memory and the register group are full, the FIFO is judged to be full, the FIFO empty mark is set to be 0, and the FIFO full mark is set to be 1. Referring to fig. 1, the FIFO controller further includes an output pin, to which the FIFO read data is valid, for outputting a control signal whether the FIFO read data is valid.
The hybrid FIFO data storage device for the high performance processor of the embodiment combines the RAM FIFO and the register FIFO, and thus has the advantages of both the RAM FIFO and the register FIFO. When the data volume is less and smaller than the capacity of the register group, the hybrid FIFO only uses the register group to store data actually, and the FIFO behavior at the moment is equivalent to a register type FIFO, so that the hybrid FIFO has the characteristic of high access speed. When the data volume is larger than the capacity of the register group, the mixed FIFO uses the register group and the RAM memory to store data at the same time, so the mixed FIFO has the characteristic of large storage capacity. At this time, the hybrid FIFO hides the delay of the RAM memory access by background data transfer between the register group and the RAM memory, that is, when the register group is not full and the RAM memory is not empty, the data transfer from the RAM memory to the register group is performed inside the FIFO, so that when there is a FIFO read request, data can be directly read out from the register group, and the access speed at this time is still equivalent to that of a register type FIFO. Only when the data volume is larger than the capacity of the register group and a large number of continuous FIFO reading operations occur, the access speed of the hybrid FIFO is reduced to be equal to the RAM type FIFO speed when the data transfer from the RAM memory to the register group cannot be completed in time in the FIFO, so that the register group with enough depth can be set according to the actual use scene to reduce the occurrence probability of the situation.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (8)
1. A hybrid FIFO data storage device for a high-performance processor, characterized by: the mixed FIFO data storage device comprises an RAM memory, a selector, a register group and an FIFO controller, wherein an FIFO data writing port of the mixed FIFO data storage device is respectively connected with an input end of the RAM memory and one input end of the selector, an output end of the RAM memory is connected with the other input end of the selector, an output end of the selector is connected with an FIFO data reading port of the mixed FIFO data storage device through the register group, and control ends of the RAM memory, the selector and the register group are respectively connected with the FIFO controller.
2. The high performance processor-oriented hybrid FIFO data storage device of claim 1, wherein: the selector is a 1-from-2 selector.
3. A microprocessor, characterized by: a hybrid FIFO data storage device oriented to a high performance processor as recited in claim 1 or 2 is included in the microprocessor.
4. A computer device, characterized by: the high performance processor oriented hybrid FIFO data storage device of claim 1 or 2 is included in a chip of the computer apparatus.
5. A method for applying the hybrid FIFO data storage device for a high-performance processor according to claim 1 or 2, wherein the step of performing FIFO write control by the FIFO controller comprises:
A1) judging whether the FIFO full mark is 0 and the FIFO write enable is 1, and if yes, skipping to execute the next step;
A2) judging whether the RAM is empty, the register group is not full, and background data transfer between the RAM and the register group does not exist currently, if so, generating register group write enable by the FIFO controller, selecting external FIFO write data by the selector, and writing the external FIFO write data into the register group after passing through the selector; otherwise, the FIFO controller generates a RAM memory write enable to write the external FIFO write data directly into the RAM memory.
6. The method as claimed in claim 5, wherein the step of performing FIFO read control by the FIFO controller comprises:
B1) judging whether the FIFO empty mark is 0 and the FIFO read enable is 1, and if yes, skipping to execute the next step;
B2) judging whether the register set is empty, and if the register set is empty, skipping to execute the step B3); jumping to execute step B4 if the register set is not empty);
B3) waiting for background data transfer between the RAM memory and the register group, and jumping to execute the next step after the background data transfer between the RAM memory and the register group is completed to enable the register group to be non-empty;
B4) the FIFO controller generates a register set read enable to read FIFO read data directly from the register.
7. The method as claimed in claim 5 or 6, wherein the step of background data migration between the RAM memory and the register set comprises:
C1) judging whether the register group is not full and the RAM memory is not empty or not, and if so, skipping to execute the next step;
C2) the FIFO controller generates RAM read enable, controls the selector to select RAM read data after the RAM read is valid as 1, generates register group write enable, and carries out background data transfer from the RAM memory to the register group on the FIFO data.
8. The method of claim 5, wherein the FIFO controller further comprises the steps of recording the read and write pointers of the RAM memory and the register set, determining the empty/full status of the RAM memory and the register set, and the empty/full status of the entire FIFO, and the detailed steps comprise: when the RAM memory write enable is generated, adding 1 to a RAM memory write pointer; when the read enable of the RAM memory is generated, adding 1 to a read pointer of the RAM memory after the RAM read data are received to be valid; when the register group write enable is generated, adding 1 to a register group write pointer; when the register group read enable is generated, adding 1 to a register group read pointer; when the read-write pointers of the RAM memories are equal, the RAM memory is judged to be empty; when the read pointer of the RAM memory is equal to the write pointer plus 1, judging that the RAM memory is full; when the read-write pointers of the register group are equal, the register group is judged to be empty; when the register group read pointer is equal to the write pointer plus 1, the register group is judged to be full; when the RAM memory and the register group are both empty, judging that the FIFO is empty, setting the FIFO empty mark as 1 and the FIFO full mark as 0; when the RAM memory and the register group are full, the FIFO is judged to be full, the FIFO empty mark is set to be 0, and the FIFO full mark is set to be 1.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113051197A (en) * | 2021-03-31 | 2021-06-29 | 上海阵量智能科技有限公司 | Data transmission device, data processing device, data transmission method, data processing method, computer device, and storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5079693A (en) * | 1989-02-28 | 1992-01-07 | Integrated Device Technology, Inc. | Bidirectional FIFO buffer having reread and rewrite means |
| JPH04192025A (en) * | 1990-11-27 | 1992-07-10 | Canon Inc | Information reproducing device |
| CN102654827A (en) * | 2011-03-02 | 2012-09-05 | 安凯(广州)微电子技术有限公司 | First-in first-out buffer and data caching method |
| CN102819418A (en) * | 2012-07-31 | 2012-12-12 | 中国人民解放军国防科学技术大学 | FIFO data storage method and device of ultrafine particle gated clock |
| CN104407809A (en) * | 2014-11-04 | 2015-03-11 | 盛科网络（苏州）有限公司 | Multi-channel FIFO (First In First Out) buffer and control method thereof |
| CN110442321A (en) * | 2019-07-19 | 2019-11-12 | 南京芯驰半导体科技有限公司 | One kind prefetching fifo circuit and method |
-
2020
- 2020-04-03 CN CN202010259365.1A patent/CN111414148A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5079693A (en) * | 1989-02-28 | 1992-01-07 | Integrated Device Technology, Inc. | Bidirectional FIFO buffer having reread and rewrite means |
| JPH04192025A (en) * | 1990-11-27 | 1992-07-10 | Canon Inc | Information reproducing device |
| CN102654827A (en) * | 2011-03-02 | 2012-09-05 | 安凯(广州)微电子技术有限公司 | First-in first-out buffer and data caching method |
| CN102819418A (en) * | 2012-07-31 | 2012-12-12 | 中国人民解放军国防科学技术大学 | FIFO data storage method and device of ultrafine particle gated clock |
| CN104407809A (en) * | 2014-11-04 | 2015-03-11 | 盛科网络（苏州）有限公司 | Multi-channel FIFO (First In First Out) buffer and control method thereof |
| CN110442321A (en) * | 2019-07-19 | 2019-11-12 | 南京芯驰半导体科技有限公司 | One kind prefetching fifo circuit and method |
Non-Patent Citations (2)
| Title |
|---|
| MX6655: "异步FIFO的设计", 《DOCIN.COM/P-942245573-F2.HTML》 * |
| 张承义; 郭维; 周宏伟: "Cache漏流功耗的自适应优化:动态容量调整", 《国防科技大学学报》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113051197A (en) * | 2021-03-31 | 2021-06-29 | 上海阵量智能科技有限公司 | Data transmission device, data processing device, data transmission method, data processing method, computer device, and storage medium |
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Application publication date: 20200714 |