CN115603894A - Stream cipher reconfigurable accelerator and acceleration method for B5G system - Google Patents

Abstract

The invention provides a reconfigurable accelerator and an acceleration method for a B5G system. The hardware design includes a reconfigurable controller module for generating an algorithm selection signal; the system also comprises a reconfigurable Linear Feedback Shift Register (LFSR) module which is used for circularly generating data used for the operation of the stream cipher algorithm; the system also comprises a Finite State Machine (FSM) module which finally obtains the ciphertext through the cycle calculation in the FSM. The common mode of various stream cipher algorithms can use the LFSR module, and respective calculation feedback units and different tap selection positions are used to adapt to different acceleration scenes, namely different data links and calculation modules are selected according to input algorithm selection signals. The hardware architecture provided by the invention can freely select an algorithm with better encryption effect according to various different scene requirements under a B5G system, and the design of the common mode can better meet the ultra-high-speed encryption requirement of the B5G system.

Description

B5G system-oriented stream cipher reconfigurable accelerator and acceleration method

Technical Field

The invention relates to a 256-bit stream cipher reconfigurable accelerator for a rear 5G (B5G) system, in particular to the technical field of hardware accelerators applying different scene encryption requirements.

Background

Symmetric cryptography plays an important role in security of transmission data in 3GPP (3 rd Generation Partnership Project) mobile phone systems. Stream cipher SNOW 3G is one of the core algorithms for integrity and confidentiality protection in UMTS (Universal Mobile Telecommunications System) and LTE (Long Term Evolution). In a new generation system currently referred to as 5G, the system architecture has changed fundamentally, placing new requirements on security, which pose some challenges to existing cryptographic algorithms.

The 4G system is based on snow3G, AES and ZUC (grand rushing's algorithm), defining three different possible algorithms for integrity (128-EIAx) and confidentiality (128-EEAx). As for the 5G system, the third generation partnership project standardization organization wishes to use a 256-bit key length as a key security level, and for AES this variation is relatively simple, since the 256-bit variant has been well known and used for a long time. For ZUC and SNOW 3G, the situation is different, neither of these ciphers was originally designed for a 256-bit key length; and many network nodes in 5G will be virtualized, the ability to use special hardware (such as IP cores) for encryption primitives is limited, and AES is expected to remain in 5G. However, both SNOW 3G and ZUC, cannot achieve such high rates in a purely software environment.

In order to solve the problems, a ZUC-256 sequence cryptographic algorithm which uses a 256bit secret key and is designed based on a ZUC-128 algorithm is published in 2018 in China. Compared with the ZUC-128 algorithm of a 128bit key. The ZUC-256 algorithm redesigns the initialization. The length of the initialization vector IV is increased to provide enough safety redundancy, and message authentication codes with various lengths can be supported to meet the requirement of 5G potential multiple safety levels.

Ekdahl developed a new member of the SNOW stream cipher family, called SNOW-V, whose design goal was to speed up in a virtualized environment and provide 256-bit security. The algorithm utilizes an AES Instruction and a vectorized SIMD (Single Instruction Multiple Data) Instruction in a CPU to realize an encryption rate of up to 58 Gbps. In addition, SNOW-V may continuously generate a 128-bit keystream.

However, on a CPU with limited vector register width or instruction set, SNOW-V may not perform well. For example, there may be a transitional network deployment scenario where the 5G ciphering layer (PDCP) has not been virtualized, but is handled in software on the base station, we are forced to perform fast ciphering on CPUs with limited vector register width and simpler SIMD instruction sets.

On the basis of SNOW-V, ekdahl therefore again proposes a variant of SNOW-Vi, which addresses the speed requirements in these low-level CPUs. Compared with SNOW-V, the method is different in the updating mode of the LFSR, the selected position of the tap is changed to realize higher safety, and other parts are kept the same as the SNOW-V.

In the current technical development, the encryption application of the ZUC-256 algorithm, the SNOW-V algorithm and the SNOW-Vi algorithm in software is improved, but the operation speed of the algorithm on the software still cannot meet the operation requirement. Currently, none of the three algorithms become the 5G system encryption standard but all have the potential to become the standard for the later 5G (B5G) system, but satisfy the most promising three algorithms of the 5G security standard. Current ASIC designs are directed to only one algorithm, and if the algorithm is excluded from the standard, the chip is also subject to obsolescence. The suitability of the three algorithms for B5G systems in different situations needs to be considered.

Disclosure of Invention

The purpose of the invention is as follows: a stream cipher reconfigurable accelerator for a B5G system is used for overcoming the defects of operation of algorithms in the background technology, supporting three algorithms in a single chip at low cost and meeting the acceleration requirements of the B5G system on application encryption in different scenes.

The technical scheme is as follows: according to one aspect of the application, the stream cipher reconfigurable accelerator oriented to the B5G system comprises:

the reconfigurable linear feedback shifter module comprises two groups of reconfigurable linear feedback shift registers LFSR-A and LFSR-B, and when the reconfigurable linear feedback shifter module works, the two groups of linear feedback shift registers can be spliced into a group of shift registers according to algorithm selection, data can be updated circularly based on update logic, and the update logic is replaced according to an externally input algorithm selection signal;

the FSM is used for receiving data transmitted by the LESR and calculating;

and the linear feedback shift register LFSR is replaced according to an algorithm selection signal input by the reconfigurable controller, generates and transmits different data to be input into the finite state machine FSM for calculation to obtain a ciphertext.

According to one aspect of the application, reconfigurable linear feedback shift registers use the same two sets of shift registers, each linear feedback shift register having a total length of 256 bits, each including 16 cells, each cell having 16 bits of data.

According to one aspect of the application, two 16-bit units in two sets of linear feedback shift registers can be spliced into 31-bit unit data, and one-bit repeated unit is discarded.

According to one aspect of the application, the reconfigurable linear feedback shift register is updated in the same way, wherein the data of the highest bit position is calculated by the feedback calculation unit,

after different feedback calculation units are selected by the reconfigurable linear feedback shift register, the reconfigurable linear feedback shift register calculates to obtain highest bit unit data;

the data of the other units are obtained by the data moving unit, namely the data are moved by the adjacent high-level units, and the data moved by the lowest level unit can directly exit each time; the data moving units of different stream cipher algorithms are the same, and the feedback computing units are different.

According to one aspect of the application, the feedback calculation unit selects different feedback calculation units according to the algorithm selection unit:

the ZUC-256 algorithm selects five tap data to calculate to obtain the updated data of the highest bit unit;

selecting three tap data by a SNOW-V algorithm to calculate to obtain updated data of the highest bit unit;

the SNOW-Vi algorithm selects two tap data to calculate to obtain updated data of the highest bit unit.

According to one aspect of the application, the multiple stream cipher algorithms use different logic combination circuits for data transmission, respectively support different finite field calculations, and select the logic combination circuit according to an algorithm selection signal.

According to one aspect of the application, the reconfigurable linear feedback shift register LFSR extracts the data of 8 units at corresponding positions and transmits the data to the finite state machine FSM for operation, and the data are transmitted by using different combinational logics according to algorithm selection signals;

when the ZUC-256 algorithm is selected, transmitting 8 determined spliced unit data in the spliced register, and entering a finite-state machine module for bit recombination;

when a SNOW-V algorithm is selected, transmitting 8 low-order register units of a linear feedback shift register LFSR-A register and 8 high-order register units of a linear feedback shift register LFSR-B to an FSM module;

and when the SNOW-Vi algorithm is selected, transmitting the 8 high-order register units of the linear feedback shift register LFSR-A, and taking the 8 high-order register units of the linear feedback shift register LFSR-B.

According to another aspect of the present application, the method for accelerating a stream cipher reconfigurable device for a B5G system according to any of the above embodiments includes the following steps:

step 1, selecting an algorithm to be used according to configuration information, outputting an algorithm selection signal to a subsequent module, and initializing initial data of a reconfigurable linear shift register and a Finite State Machine (FSM);

step 2, updating the linear feedback shift register LFSR according to the algorithm selection signal, namely after the required stream cipher algorithm is selected, using different feedback calculation unit modules, updating the highest bit data in the linear feedback shift register LFSR by selecting different feedback calculation units according to the algorithm, and updating other bit data by using the same shift unit;

step 3, updating the finite state machine FSM according to the algorithm selection signal, namely selecting different tap positions in the reconfigurable linear feedback shift register LFSR data after selecting the required stream cipher algorithm, transmitting different data to enter the finite state machine FSM for initialization calculation and key generation;

and 4, repeating the step 2 and the step 3 until a required ciphertext is obtained.

Has the beneficial effects that: the invention provides a B5G system-oriented stream cipher reconfigurable accelerator, which can meet the diversified selection of acceleration algorithms under different conditions by providing a ZUC-256, SNOW-V and SNOW-Vi algorithm common mode design and supporting three algorithms with the maximum potential in a B5G system at lower resource cost, thereby ensuring that any one of the three algorithms becomes the standard of the B5G system, and a produced chip can be used, and ciphertext streams can be quickly obtained no matter which encryption algorithm is adopted. On the other hand, a hardware circuit used by the common mode of the three designed algorithms uses less complex calculation parts, and the hardware is easier to realize, so that the acceleration requirements of encryption in different scenes in a B5G system can be met.

Drawings

Fig. 1 is a schematic diagram of the overall architecture of the stream cipher reconfigurable accelerator.

FIG. 2 is a schematic diagram of a reconfigurable feedback shift computing unit according to the present invention.

FIG. 3 is a schematic diagram of the hardware design of a feedback computing unit of the SNOW-Vi algorithm of the present invention.

Fig. 4 is a schematic diagram of the hardware design of the feedback computing unit of the ZUC-256 algorithm of the present invention.

FIG. 5 is a schematic diagram of the LFSR module selecting different position taps for transmission to the FSM module according to the three algorithms of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention.

In order to solve the problems of the prior art, the applicant has conducted intensive studies and proposed the following technical solutions. For ease of description herein, in part, the finite state machine module or FSM module will be referred to as a finite state machine module, and the linear feedback shift register module will be referred to as a linear feedback shift register module or LFSR module.

A256-bit stream cipher reconfigurable accelerator for a B5G (last 5G, same below) system is provided, and the same data updating unit register is used in three stream cipher algorithms. The accelerator specifically includes: the reconfigurable linear feedback shift register module (LFSR) and the finite state machine module (FSM) select an algorithm common mode according to a selection signal output by the reconfigurable control layer, the linear feedback shift register LFSR module register and the finite state machine FSM module are used, and initial data are obtained through the initialization data module. The LFSR module transmits the generated data to the FSM module of the finite state machine, and the FSM module receives the data and calculates to obtain a ciphertext.

Specifically, the reconfigurable LFSR module is composed of two sets of shift registers, which can cyclically update unit data, and the two sets of shift registers LFSR-a and LFSR-B have the same structure, are 256 bits long, each of which includes 16 sets of unit data, and each set of data is 16 bits. In hardware design, two groups of registers can be spliced into one group of registers with the bit length of 512 bits, wherein 16 groups of unit data are included, each group of data is 31 bits, one repeated data is abandoned, and 16 bits of data are totally abandoned.

Different from the existing patent, after the reconfigurable control layer selects different feedback calculation units, the reconfigurable LFSR module performs calculation to obtain the highest bit unit data. The generation of data of the lower bit positions is not regulated by the algorithm selection signal, the data of each unit is obtained by using the data moving unit, and the lower bit position unit directly exits every time the updating is carried out.

The feedback computing unit is designed to be a simple combinational logic circuit, and is the same as the existing patent, and multiplication of different finite fields is realized by combination of an AND gate and an XOR gate.

In the three algorithms, the reconfigurable LFSR module respectively transmits data at different positions in two registers to enter FSM module operation. The location of the transmitted data is controlled in accordance with the algorithm selection signal.

The FSM module needs two shift registers in the LFSR module to respectively take 8 unit data to input, wherein the ZUC-256 algorithm transmits spliced unit data; different from the prior design, when a SNOW-Vi algorithm is selected, the linear feedback shift register LFSR-A transfers 8 high-order unit data to a finite state machine FSM module, and the LFSR-B register transfers 8 high-order unit data to the FSM module; when the ZUC-256 algorithm is selected, 8 fixed spliced unit data in the spliced register are transmitted to the FSM module.

Under the condition of three algorithms, the FSM module receives data of the reconfigurable shift register and calculates to obtain a ciphertext.

In some implementations of the first aspect, the design of the common mode algorithm also requires data initialization, i.e., a data initialization module is designed to provide initial data required for the operation of the reconfigurable LFSR and FSM.

The 256-bit stream cipher reconfigurable accelerator for the B5G (rear 5G) system can not only realize the high-speed operation of the stream cipher algorithm on hardware, but also meet the encryption requirement in various application scenes in the B5G system at lower cost, avoid the chip from being eliminated due to the unicity, and support the three 256-bit algorithms with the most potential.

In the prior art, a 256-bit stream cipher algorithm is operated in software, the speed still cannot meet the actual requirement, and at present, none of the three algorithms becomes the standard of a 5G system, but all algorithms have the potential to become the standard of a B5G system, and a 256-bit stream cipher reconfigurable accelerator facing a rear 5G (B5G) system is provided, as shown in fig. 1, the 256-bit stream cipher reconfigurable accelerator provided by the embodiment includes a linear feedback shift register module and a finite state machine module which are shared by two algorithms. Wherein, the left half part of fig. 1 is a linear feedback shift register module, and the right half part is a finite state machine module. The reconfigurable LFSR module consists of two shift registers which are named as LFSR-A and LFSR-B respectively, and the module can be updated in an internal cycle. The ZUC-256, SNOW-V and SNOW-Vi algorithms use the register portion and cell data transfer design of the LFSR module and the FSM module, and the difference of the three algorithms is that the calculation feedback cells for updating the data inside the LFSR are different from the data sets calculated by the LFSR module extraction tap transfer FSM, and the design selects the calculation feedback cells and tap positions corresponding to the algorithm according to the selection signals input from the outside.

As shown in FIG. 2, a reconfigurable hardware design feedback shift cell is described in detail, in which the linear feedback shift register LFSR-A is composed of 16-bit shift registers a ₁₅ ,a ₁₄ ,…,a ₀ The linear feedback shift register LFSR-B consists of 16 shift registers B with 16 bits ₁₅ ,b ₁₄ ,…,b ₀ And (4) forming. Therefore, the total length of the shift registers in each group is 256 bits.

Further, as shown in FIG. 2, the 31-bit registers of the LFSR of the ZUC-256 algorithm are formed by splicing 16-bit registers used by 2 SNOW algorithms, (b) _i ,a _i ) Are spliced into S _i ，i∈[0,15]，b _i Is S _i High 16bit of (a) _i Is S _i Low by 16 bits.

Further, the fine real line part shown in fig. 2 is a data link and feedback calculation operation when the algorithm selection signal is input to the algorithm SNOW-V, the coarse real line part shown in fig. 2 is a data link and feedback calculation operation when the algorithm selection signal is input to the algorithm SNOW-V, and the dotted line part shown in fig. 2 is a data link and feedback calculation operation when the algorithm selection signal is input to the algorithm SNOW-Vi.

Further, when the linear feedback shift is registeredThe memory LFSR is configured to be operated by SNOW algorithm logic, and all bits of all registers participate in operation; when the LFSR is configured to ZUC-256 logic operation, at register (b) _i ,a _i ) There will be 1-bit reset between them, the LFSR update logic of ZUC-256 will discard 1-bit reset by means of bit concatenation, and only 16 bits of the whole 512-bit LFSR will be discarded.

In a further embodiment, the linear feedback shift register LFSR feedback logic of all three algorithms comprises modulo operations in finite fields, the finite fields of the three being of different types. The multistage modular operation in the ZUC-256 algorithm comprises 5 times of modular multiplication operation and 5 times of modular addition operation, and the feedback calculation operation structure is as follows:

S ¹⁶ ＝(2 ¹⁵ ·s ₁₅ +2 ¹⁷ ·s ₁₃ +2 ²¹ ·s ₁₀ +2 ²⁰ ·s ₄ +2 ⁸ ·s ₀ +s ₀ )mod(2 ³¹ -1)

the result S obtained ₁₆ Is updated to S ₁₅ And S is ₁₅ The original value will be updated to S ₁₄ And so on, i.e. (S) ₁₆ ,S ₁₅ ,···,S ₂ ,S ₁ )→(S ₁₅ ,S ₁₄ ,···,S ₁ ,S ₀ ). In each update operation, the register is moved one step forward.

Further, the method is different from the SNOW-V algorithm design of the prior patent, namely the SNOW-Vi algorithm, wherein the LFSR-A and the LFSR-B have different primitive polynomials and are different from the SNOW-V algorithm design of the prior patent. Specifically, the primitive polynomial of LFSR-a is:

g ^A (x)＝x ¹⁶ +x ¹⁴ +x ¹¹ +x ⁹ +x ⁶ +x ⁵ +x ³ +x ² +1，g ^A (x)∈F _2[x]

the primitive polynomial for LFSR-B is:

g ^B (x)＝x ¹⁶ +x ¹⁵ +x ¹⁴ +x ¹¹ +x ¹⁰ +x ⁷ +x ² +x+1，g ^B (x)∈F ₂ [x]

with SNOW-V shift in the prior patentThe feedback calculation modes of the data updating of the high-bit units of the bit registers are different, a SNOW-Vi needs a dedicated feedback calculation mode, the feedback calculation units used by the two shift registers are different, and specifically, the feedback formula of the linear feedback shift register LFSR-A is as follows

In the formula (I), the compound is shown in the specification,

is represented by g ^A (x) The root of (a); the feedback formula of LFSR-B is

In the formula (I), the compound is shown in the specification,

is represented by g ^B (x) The root of (2). The shift registers A and B update the data of the high bit units through the different feedback calculation units.

The result obtained a ₁₅ Is updated to a ₁₅ A and a ₁₅ Original value will be updated to a ₁₄ And so on, i.e. (a) ₁₅ ,···,a ₂ ,a ₁ )→(a ₁₄ ,···,a ₁ ,a ₀ ) (ii) a The result obtained b ₁₅ Is updated to b ₁₅ And b is ₁₅ Original value will be updated to b ₁₄ And so on, i.e. (b) ₁₅ ,···,b ₂ ,b ₁ )→(b ₁₄ ,···,b ₁ ,b ₀ )。

The feedback formula is operated in a finite field, a special calculation unit is designed for the feedback formula, a SNOW calculation unit is simple in composition and can be realized only by one MUX and multi-stage XOR, hardware of an LFSR-A feedback calculation unit designed by a SNOW-Vi algorithm is shown in figure 3, hardware of a linear feedback shift register LFSR-B feedback calculation unit is the same in design, only input data are different, and description is omitted.

The multistage modular operation of the ZUC-256 algorithm is a key path of the algorithm, and 6 numbers are totally obtained after modular multiplication is realized through cyclic shift and modular addition operationModulo addition is required. Considering the W fed back by the FSM in the initialization phase, the added number is 7, the length of the result is 34 bits at most, and then the modulus 2 of 7 31-bit numbers is 2 ³¹ 1 addition, i.e. adding the highest 3 bits of the 34bit result to the lower 31 bits of the result. After improvement, the original calculation steps of multi-stage modulo addition are reduced, and the hardware design of the feedback unit of the ZUC-256 algorithm design is shown in FIG. 4.

In further operations, such as fig. 1 having a finite state machine module in addition to the shift register module, the three stream cipher algorithms use FSM modules that receive LFSR data to compute the ciphertext z.

For example, fig. 1 also designs a data initialization module in addition to the shift register and the finite-state machine module, and the three kinds of stream cipher algorithms design to initialize the operation data required by the two kinds of algorithms by using the data initialization module, and when the initialization signal is valid, the shift register module and the finite-state machine module receive the initialized data and perform calculation and flow of the data. After initialization is completed, the initialization signal is invalid, the initialization mode is exited, the common mode accelerator starts to work normally, and the calculated ciphertext z is output.

The updating processes of the three stream cipher algorithms are different, namely, the data of the highest bit position is updated by using a feedback computing unit unique to each algorithm, the data is updated once in each clock period, the data is designed to select different feedback computing units according to different algorithm selection signals output by the reconfigurable control layer, and meanwhile, the data is irrelevant to the algorithm selection signals, and the data of other low-bit position units are moved by the data of the adjacent high-bit position.

I.e. for the ZUC-256 algorithm, S ₁₆ Update to S ₁₅ And S is ₁₅ The original value will be updated to S ₁₄ And so on, i.e. (S) ₁₆ ,S ₁₅ ,···,S ₂ ,S ₁ )→(S ₁₅ ,S ₁₄ ,···,S ₁ ,S ₀ ). In each updating operation, the register is moved forward by one step; for the SNOW-Vi algorithm, a ₁₅ Is updated to a ₁₅ A and a ₁₅ Original value will be updated to a ₁₄ And so on, i.e. (a) ₁₅ ,···,a ₂ ,a ₁ )→(a ₁₄ ,···,a ₁ ,a ₀ ) (ii) a The result obtained b ₁₅ Update to b ₁₅ And b is a ₁₅ Original value will be updated to b ₁₄ And so on, i.e. (b) ₁₅ ,···,b ₂ ,b ₁ )→(b ₁₄ ,···,b ₁ ,b ₀ ). That is, half of the data can be updated every eight clock cycles, and after the data change, the taps at different positions are selected according to the algorithm selection signal, specifically, the SNOW-Vi algorithm selects different taps to be transmitted to the FSM module, that is, the FSM selects T1= (b) ₁₅ ,b ₁₄ ,…,b ₈ ) And T2= (a) ₁₅ ,a ₁₄ ,…,a ₈ ) Calculating; ZUC-256 Algorithm selection s ₁₅ ,s ₁₄ ,s ₁₁ ,s ₉ ,s ₇ ,s ₅ ,s ₂ ,s ₀ And the 8 spliced 31-bit unit data enter an FSM module to be subjected to bit recombination. The schematic diagram of the selection of the different tap positions for the three algorithms is shown in fig. 5, wherein the thin solid lines represent the data streams for selecting ZUC-256 algorithm, the thick solid lines represent the data streams for selecting SNOW-V algorithm, and the thick dashed lines represent the data streams for selecting SNOW-Vi algorithm.

In further operation, the whole reconfigurable algorithm accelerator also comprises initialization operation when starting operation, specifically, any algorithm is selected to run according to an algorithm selection signal, different data are assigned to 16 modules of two registers when the initialization is started, so that the initialization process needs to be carried out 16 times to realize complete initialization, and the specific initialization steps are as follows:

step a, updating input data of an FSM module, selecting a stream cipher algorithm according to an input selection signal, and further selecting different taps to update the FSM module;

b, selecting different stream cipher algorithms according to the input selection signal and selecting different feedback calculation units to update the LFSR module;

and c, initializing data by calculating through an initialization data module and an FSM module.

After the initialization is finished, the reconfigurable accelerator starts to work normally.

In one embodiment, a 256-bit stream cipher reconfigurable accelerator for a rear 5G (B5G) system is provided, which is characterized by specifically including the following steps:

step 1, a reconfigurable controller selects an algorithm to be used according to configuration information, outputs an algorithm selection signal to a subsequent module, and initializes initial data of a reconfigurable linear shift register and an FSM module;

step 2, updating an LFSR module according to the algorithm selection signal, namely after the required stream cipher algorithm is selected, using different feedback calculation unit modules, updating the highest bit data in the LFSR by selecting different feedback calculation units through the algorithm, and updating other bit data by using the same shifting unit;

step 3, updating the FSM module according to the algorithm selection signal, namely selecting different tap positions in the data of the reconfigurable LFSR module after selecting the required stream cipher algorithm, and transmitting different data to the FSM module for initialization calculation and key generation;

and 4, repeating the step 2 and the step 3 until a required ciphertext is obtained.

In a word, under the condition that an encryption standard is not determined in a B5G system, the reconfigurable linear feedback shift register is designed according to the characteristic that different stream ciphers have the same cipher text generation structure, particularly the design that two groups of feedback shift registers are combined into one group, the design of supporting ZUC-256,SNOW-V and SNOW-Vi algorithms with potential under the condition of low resource overhead is realized, different stream cipher algorithms can be switched according to different finite field calculation requirements and scene requirements, and the richness of the accelerator function is enhanced.

As noted above, while the present invention has been shown and described with reference to certain preferred embodiments, it is not to be construed as limited to the invention itself. Various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (9)

1. A stream cipher reconfigurable accelerator oriented to a B5G system is characterized by comprising:

the reconfigurable linear feedback shifter module comprises two groups of reconfigurable linear feedback shift registers LFSR-A and LFSR-B, and when the reconfigurable linear feedback shifter module works, the two groups of linear feedback shift registers can be spliced into a group of shift registers according to algorithm selection, data can be updated circularly based on update logic, and the update logic is replaced according to an externally input algorithm selection signal;

the finite state machine FSM used by the common mode is used for receiving and calculating data transmitted by the linear feedback shift register LESR;

and the linear feedback shift register LFSR is replaced according to an algorithm selection signal input by the reconfigurable controller, generates and transmits different data to be input into the finite state machine FSM for calculation to obtain a ciphertext.

2. The accelerator of claim 1, wherein the reconfigurable linear feedback shift registers use two identical sets of shift registers, each linear feedback shift register has a total length of 256 bits and comprises 16 cells, and data of each cell is 16 bits.

3. The accelerator of claim 2, wherein two 16-bit units in two sets of linear feedback shift registers can be spliced into 31-bit unit data, and one-bit repeated unit is discarded.

4. The B5G system oriented stream cipher reconfigurable accelerator of claim 3,

the reconfigurable linear feedback shift register has the same data updating mode, wherein the data of the highest bit position is calculated by the feedback calculating unit,

after different feedback calculation units are selected by the reconfigurable linear feedback shift register, the reconfigurable linear feedback shift register performs calculation to obtain highest bit unit data;

the data of the other units are obtained by the data moving unit, namely the data are moved by the adjacent high-level units, and the data of the lowest-level unit are directly withdrawn each time; different stream cipher algorithm data mobile units are the same, and feedback computing units are different.

5. The accelerator of claim 4, wherein the feedback computing unit selects different feedback computing units according to the algorithm selection unit:

the ZUC-256 algorithm selects five tap data to calculate to obtain the updated data of the highest bit unit;

selecting three tap data by a SNOW-V algorithm to calculate to obtain updated data of the highest bit unit;

the SNOW-Vi algorithm selects two tap data to calculate to obtain the updated data of the highest bit position.

6. The accelerator of claim 2, wherein the plurality of stream cipher algorithms use different logic combination circuits for data transmission, support different finite field calculations respectively, and select a logic combination circuit according to an algorithm selection signal.

7. The accelerator for reconfigurable stream cipher oriented to B5G system of claim 6,

taking out data of 8 units at corresponding positions from a reconfigurable linear feedback shift register LFSR, transmitting the data to a Finite State Machine (FSM) for operation, and transmitting the data by using different combinational logics according to algorithm selection signals;

when the ZUC-256 algorithm is selected, transmitting 8 determined spliced unit data in the spliced register, and entering a finite-state machine module for bit recombination;

when the SNOW-V algorithm is selected, transmitting 8 low-order register units of the linear feedback shift register LFSR-A register, and transmitting 8 high-order register units of the linear feedback shift register LFSR-B to the FSM module;

and when the SNOW-Vi algorithm is selected, transmitting the 8 high-order register units of the linear feedback shift register LFSR-A, and taking the 8 high-order register units of the linear feedback shift register LFSR-B.

8. An acceleration method of a stream cipher reconfigurable device facing to a B5G system based on any one of claims 1 to 7, characterized in that the method comprises the following steps:

step 1, selecting an algorithm to be used according to configuration information, outputting an algorithm selection signal to a subsequent module, and initializing initial data of a reconfigurable linear shift register and a Finite State Machine (FSM);

step 2, updating the linear feedback shift register LFSR according to the algorithm selection signal, namely after the required stream cipher algorithm is selected, using different feedback calculation unit modules, selecting different feedback calculation units by the algorithm to update the highest bit data in the linear feedback shift register LFSR, and using the same shift unit to update other bit data;

step 3, updating the finite state machine FSM according to the algorithm selection signal, namely selecting different tap positions in the reconfigurable linear feedback shift register LFSR data after selecting the required stream cipher algorithm, transmitting different data to enter the finite state machine FSM for initialization calculation and key generation;

and 4, repeating the step 2 and the step 3 until a required ciphertext is obtained.

9. The method of claim 8, further comprising the steps of:

any algorithm is selected to operate according to the algorithm selection signal, different data are assigned to 16 modules of the two registers when initialization is started, so that the initialization process needs to be carried out 16 times to realize complete initialization, and the specific initialization steps are as follows:

step a, updating input data of a finite state machine FSM module, selecting a stream cipher algorithm according to an input selection signal, and further selecting different taps to update the finite state machine FSM module;

b, selecting different stream cipher algorithms according to the input selection signal and selecting different feedback calculation units to update the LFSR module;

and c, initializing data by calculating through an initialization data module and a Finite State Machine (FSM) module.

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