KR100667189B1 - Apparatus for aes encryption in mobile device and method thereby - Google Patents

Abstract

An apparatus and a method for AES(Advanced Encryption Standard) encryption in a mobile device are provided to reduce power consumption and enhance a degree of integration by simplifying a composition of hardware. An integrated block(320) performs an operation by using a look-up table. A shift row block(420) moves rows of a data matrix outputted from the integrated block. A mix column block(430) changes linearly the data processed by the shift row block. A first MUX(440) receives selectively the data to be transmitted to the shift row block, the mix column block, or a data input unit. A key management unit(470) receives selectively a round key and shifts the stored round key to the integrated block. A second MUX(310) transfers selectively the encryption data or the round key to the integrated block. A round key processing block(450) receives selectively the data and the round key from the first MUX and the key management unit and performs an encryption key operation.

Description

Apparatus for AES Encryption in Mobile Device and Method

1 is a hardware configuration diagram illustrating a conventionally used AES encryption algorithm;

2a and 2b is a table for explaining the function of the subbyte block of the conventional AES encryption device,

3 is a diagram schematically illustrating a method of integrating a subbyte block and a subword block of a key management unit respectively configured according to an embodiment of the present invention;

4 is a hardware configuration diagram of an AES encryption device according to an embodiment of the present invention;

5 is a circuit diagram illustrating in detail an integrated block according to an embodiment of the present invention;

6 is a diagram illustrating an initial round processing procedure of an AES encryption apparatus according to an embodiment of the present invention;

7 is a diagram for describing a repetitive round processing process of an AES encryption device according to an embodiment of the present invention;

8 is a view for explaining the last round processing of the AES encryption apparatus according to an embodiment of the present invention;

9 is a diagram illustrating timing used for AES encryption according to an embodiment of the present invention.

The present invention relates to an AES (Advanced Encryption Standard) encryption apparatus and method for a portable device. More specifically, the present invention relates to an AES encryption device and method that can be easily applied to a small, low power portable device by reducing hardware capacity while maintaining the encryption performance of a conventional AES encryption device.

As electronic payments using the Internet and mobile communication networks become active, security of personal information is considered to be very important. Accordingly, encryption and decryption processes are required for security of personal information, and DES (Data Encryption Standard), which is an encryption method using 56 bits, is used.

However, with the technological development of the Internet and mobile communication networks, hacking techniques for impure purposes such as personal information leakage have also developed, which threatens the safety of the DES method using 56 bits. Accordingly, a more secure encryption algorithm is required, and an AES block algorithm using a key of 128 bits or more has been proposed.

1 is a hardware configuration diagram illustrating a conventionally used AES encryption algorithm.

The AES encryption algorithm is composed of an initial round processing unit 110, a repetitive round processing unit 120 and the last round processing unit 130.

The initial round processing unit 110 is composed of a round key processing (AddRoundKey) block for the operation of processing the round key for encryption, and the repetitive round processing unit 120 is a subbyte block for performing a substitution operation on each byte. (122), in the matrix of each data component of the AES, a ShiftRows block 124 for shifting rows, and a MixColumn for performing additional linear transformation of the matrix shifted by the shiftrow block 124. Block 126 and round key processing (AddRoundKey) block 128. The last round processor 130 includes a subbyte block, a shift row block, and a round key processing block.

Here, the round key processing block included in each of the initial round processing unit 110, the repetitive round processing unit 120, and the last round processing unit 130 receives an encryption round key from the key management unit 140 for encryption. Perform key operations.

The key manager 140 includes a plurality of key generation blocks 142, and the key generation block 142 includes a rotation word block 144 for shifting an input word. A subword block 146 for applying a look-up table (S-box) to the byte at the position corresponding to the word and replacing it as an output word, an Rcon block 148 for round constant processing, and a plurality of XOR logic circuits. Consists of.

When a plain text to be encrypted is input to the AES encryption algorithm configured as described above, the plain text to be encrypted is passed through the encryption algorithms of the initial round processing unit 110, the repetitive round processing unit 120, and the last round processing unit 130.

In this encryption algorithm configured as described above, a table as shown in FIGS. 2A and 2B is used to perform a substitution operation of the subbyte block 122.

2A and 2B are tables for explaining the functions of the subbyte blocks of the conventional AES encryption apparatus.

The subbyte block 122 arranges the input bits in the form of 4 × 4 bytes as shown in FIG. 2A, and then divides each byte into upper 4 bits (x) and lower 4 bits (y), and the look-up table of FIG. 2B. Substitute a value using. For example, if the value of 2 rows 2 columns is '0x63 (= x: 6 y: 3)' in hexadecimal, '0xFB' is replaced based on the look-up table. In this way, when 128 bits are input to the subbyte block 122, 128 bits of data substituted using the look-up table are output, and the look-up table used at this time is 256x8 bits of ROM (ROM). Is implemented as

Here, the same look-up table as the subbyte block 122 is used not only in the subbyte block 122 but also in the subword block 146 of the key generation block 142. Here, the subbyte block 122 uses 128 bits, but the subword block 146 uses only 32 bits, and only the number of bits processed differs, and the output result by the look-up table is the same.

As described above, in implementing the conventional AES algorithm in hardware, the ratio of the look-up table to the entire hardware is 40% or more. However, since the sub-byte block 122 and the subword block 146 using the same look-up table are separately implemented, there is a problem in that hardware consumption is high. In addition, since the conventional AES algorithm is implemented in hardware, multiple clocks are used for one round calculation and key generation, and thus, high-speed processing is difficult.

In this regard, there is a domestic patent application 2001-0085502 'Round processing circuit and online round key generation circuit for hardware implementation of AES Rijndael (Linedal) encryption algorithm' (December 18, 2001), but using a plurality of selectors and It provides only a method of reducing hardware resources by sharing a decoding block with a shared module, and there is a domestic patent application 2002-0027236 'AES Rijndael round key generation circuit having a modular structure having an online calculation function of round key' (2002.05.09). It only provides a way to modularize key generation blocks into a pipeline. As such, both inventions provide a method of reducing the look-up table, which occupies the largest proportion of hardware, but the hardware of other parts, so that there is no significant savings on the size of the hardware, making it difficult to easily apply to mobile devices. It still contains the problem.

In order to solve this problem, the present invention integrates a subbyte block and a subword block using different look-up tables but using the same look-up table in an AES encryption device, while maintaining the conventional encryption performance. Provided are an AES encryption apparatus and method for reducing hardware capacity.

In order to achieve the above technical problem, the present invention provides a device for encrypting input data according to an AES algorithm, which is an AES algorithm encryption device, and replaces plain text input for encryption using a look-up table. An integration block for performing an operation or performing a substitution operation for generating a key; A ShiftRows block for moving a row in a matrix of data on which a substitution operation is performed by an integration block; MixColums blocks for further linearly changing data processed by the shift row block unit; A first mux for selectively receiving data transferred from a shift row block, a mix column block, or a data input unit according to a round processing step for encryption; A key management unit which selectively receives a round key processed by an initial round key or an integrated block input through a key input unit and shifts the stored round key to the integrated block; A second mux to selectively receive the data delivered for encryption or the round key delivered from the key management unit and deliver the selected round key to the integrated block; And a round key processing (AddRoundKey) block for receiving the selected data through the first mux, receiving the selected round key through the key manager, and performing a key operation for encryption.

In order to achieve the second technical problem, the present invention provides an encryption method of the AES algorithm, which is an encryption method for input data according to the AES (Advanced Encryption Standard) algorithm. Key processing initial data using an initial round key; (b) replacing the initial round key using a look-up table to generate a repeat round key for repeat round processing; (c) key-processing the keyed initial data using a repeating round key; (d) substituting a repeating round key using the look-up table to generate a last round key for the last round processing; And (e) outputting a cipher text generated by keying the data keyed by the recursive round key using the last round key.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

In addition, when a part is said to "include" a certain component, it means that it may further include other components, except to exclude other components unless otherwise stated.

In addition, the term module described herein refers to a unit for processing a specific function or operation, which may be implemented in hardware or software, or a combination of hardware and software.

FIG. 3 is a diagram schematically illustrating a method of integrating a subbyte block and a subword block of a key management unit respectively configured according to an exemplary embodiment of the present invention.

The conventional subbyte block 122 and the subword block 146 are simply displayed as 3A. Here, logics A, B, and C are parts for performing separate algorithms before or after the subbyte block 122 or the subword block 146 for subbyte processing and subword processing.

Although configured separately as described above, the conventional subbyte block 122 and the subword block 146 using the same look-up table may be configured as shown in 3B by integrating according to the present invention.

In addition, a mux 310 is further included for the integrated configuration of the subbyte block 122 and the subword block 146.

In addition, the subbyte block 122 and the subword block 146 that perform the same function are configured as one block 320. In the following description, for the convenience of description, this will be referred to as an "integrated block". In addition, the mux 310 selects the data transferred from the cyclic word block 144 of the key manager 140 and the data transferred from the logic B to the integrated block 320.

In addition, the data processed by the integration block 320 is passed to both logic A and logic C, and the key generated by logic A is input to logic C.

An AES encryption apparatus incorporating the subbyte block 122 and the subword block 146 through such a configuration method is illustrated in FIG. 4.

4 is a hardware configuration diagram of an AES encryption apparatus according to an embodiment of the present invention.

The AES encryption apparatus according to the present invention is largely composed of the encryption block 400 and the key management unit 470.

The encryption block 400 is common for the initial round processing, the repeat round processing, and the last round processing in the initial round processing unit 110, the repeat round processing unit 120, and the last round processing unit 130 to simplify the AES encryption device structure. Integrate hardware that is used as

Accordingly, the encryption block 400 includes an integrated block unit 410, a shift row block 420, a mix column block 430, a first mux 440, a round key processing block 450, and a data buffer 460. It includes. The integrated block unit 410 includes a second mux 310 and an integrated block 320 as described with reference to FIG. 3.

The first mux 440 of the encryption block 400 may input data input from the data input unit, mix-column values from the mix column block 430, and shift-low values in the shift row block 420. Selectively receives and forwards the round key processing block 450.

At this time, the first mux 460 selects and receives data according to the round processing step being executed. That is, in the initial round processing step, '0' is selected to receive data transmitted from the data input unit and transmitted to the round key processing block 450, and in the repetitive round processing step, '1' is selected to mix column block 430 The value transmitted from the group is transmitted to the round key processing block 450, and in the final round processing step, '2' is selected to transfer the shifted value to the round key processing block 450.

As described with reference to FIG. 3, the second mux 310 receives a data input from the data buffer by selecting '0' in the iterative round processing step and the last round processing step, and transfers the received data to the integration block 320. Subbyte processing is performed, and in the key generation step, '1' is selected to receive data input from the cyclic word block 144 and transfer the data to the aggregation block 320, thereby using a key using the look-up table. It is responsible for the creation.

The data buffer 460 temporarily stores the data initially rounded and the data repeatedly processed in the initial round processing step and the repeated round processing step.

The key manager 470 includes a cyclic word block 144, an Rcon block 148, a third mux 480, a key buffer 490, and a plurality of XOR logic circuits.

The third mux 480 includes an initial round key input through a key input unit, a key included in the key buffer 490, and a look-up table of the cyclic word block 144 and the integrated block 320. A part of selecting a round key to be transmitted to the round key processing block 450 from among the round keys processed through the Rcon block 148 and the XOR logic circuit. The third mux 480 is set to '0' in the initial round processing step to transmit the initial round key input through the key input unit to the round key processing block 450, and in the repeat round key processing step and the last round processing step Set to '1' to transfer the processed roundkey to roundkey processing block 450 through cyclic word block 144, look-up table of integration block 320, Rcon block 148 and XOR logic circuitry. do.

5 is a circuit diagram illustrating in detail an integrated block according to an exemplary embodiment of the present invention.

The integrated block unit 410 replaces the 128-bit input input from the data buffer 460 using the stored look-up table in order to perform the substitution operation that was processed through the conventional subbyte block 122. The result is the 128-bit result.

At this time, the 128-bit data input to the look-up table is input by being divided by 32 bits, and the second mux 310 is set to receive the upper 32 bits of the 32-bit data divided into four. In addition, the second mux 310 is configured to receive 32-bit key generation data from the cyclic word block 144 for key generation.

When the second mux 310 is set to '0', the upper 32 bits of data input from the data buffer 460 are selected and used as an input of the look-up table. The upper 32 bits of data replaced by the look-up table are combined with the other 96 bits of data replaced by the look-up table and output to the shift row block 122 as 128 bits of data.

Through this process, the substitution operation, which was processed through the conventional subbyte block 122, is performed.

The integrated block unit 410 outputs a value obtained by substituting a 32-bit input input from the cyclic word block 144 using the stored look-up table in order to perform a function of a conventional subword block. To this end, the second mux 310 of the integrated block unit 410 is set to '1' and receives 32-bit key generation data transmitted from the cyclic word block 144. When the input 32-bit key generation data is replaced by the look-up table, the 32-bit key generation data is transferred to the XOR logic circuit of the key manager 470.

Here, the AES encryption and key generation according to the present invention will be described in more detail for each processing step as follows.

6 is a diagram illustrating an initial round processing procedure of an AES encryption apparatus according to an embodiment of the present invention.

For the initial round processing in the AES encryption apparatus, the first mux 440 and the third mux 480 are set to '0', so that the initial round key input through the data input unit and the initial round key input through the key input unit are set. Enter the round key processing block 450. Accordingly, an initial round processing effect may appear, and the initial round processing result by the round key processing block 450 is stored in the data buffer 460 and used as an input value of the repetitive round processing step. Here, the setting value selection period of the first mux 440 and the third mux 480 is activated only by the rising level portions of the first clock and the second clock. Accordingly, the clock required for the initial round processing only takes one clock.

Here, the first clock and the second clock are configured such that the rising level and the falling level are alternated, so that when the first clock is the rising level, the second clock becomes the falling level, and when the first clock is the falling level, the second clock is The level rises. Accordingly, the sum of the time when the first clock has one rising level and the time when the second clock has one rising level results in one clock in the encryption apparatus.

When the initial round processing is completed through this process, the repeat round processing step is performed.

7 is a diagram illustrating a repetitive round processing process of an AES encryption device according to an embodiment of the present invention.

In order to calculate the round key to be used in the repetitive round processing step, during the rising level of the first clock, the second mux 310 is set to '1' to use the integrated block 320 as a subword block function. Then, the third mux 480 is set to '1' to round the round key processed through the cyclic word block 144, the look-up table of the integration block 320, the Rcon block 148, and the XOR logic circuit. It is maintained as an input of the key processing block 450.

In addition, a key buffer may be used to use the round key processed through the cyclic word block 144, the look-up table of the integrated block 320, the Rcon block 148, and the XOR logic circuit as the input of the next round key. 490).

During the rising level of the second clock, the second mux 310 is set to '0' to enable the integration block 320 as a subbyte block function, and the first mux 440 is set to '1' to integrate. The result processed by the block 320, the shift row block 420, and the mix column block 430 is transmitted to the round key processing block 450. Then, the round key processing block 450 is calculated along with the round key input through the third mux 480 and then stored in the data buffer 460 for use as an input of the last round processing step.

Through this method, iterative round processing is performed for one clock. When the iterative round process is completed through this process, the last round process step is performed.

8 is a diagram illustrating a final round processing procedure of an AES encryption apparatus according to an embodiment of the present invention.

In order to calculate the round key to be used in the last round processing step, during the rising level of the first clock, the second mux 310 is set to '1' to use the integrated block 320 as a subword block function. The third mux 480 is set to '1' to set the round key processed through the cyclic word block 144, the look-up table of the integrated block 320, the Rcon block 148, and the XOR logic circuit. Maintained as an input of the round key processing block 450.

Then, during the rising level of the second clock, the second mux 310 is set to '0' to use the integrated block 320 as a subbyte block function, and the first mux 440 is set to '2'. By calculating and outputting the data not processed by the mix column block 430 together with the round key, encryption is completed. In this way, the calculation of the last round step is performed during one clock.

In the above description of FIGS. 3 to 8, the set values (0, 1, 2) of each mux may be set in various ways.

9 is a diagram illustrating timing used for AES encryption according to an embodiment of the present invention.

Here, the shaded portions of the round data and the round key are timings used by the integration block 320.

AES encryption requires 10 rounds for 128-bit round data and round key processing. As shown in FIG. 9, since only one clock is required for one round processing, hardware for this may be significantly reduced as shown in FIG. 4, but the performance is not degraded and the resulting value may be output. It becomes possible.

The embodiments of the present invention described above are not implemented only through the apparatus and the method, but may be implemented through a program for realizing a function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded. Implementation may be easily implemented by those skilled in the art from the description of the above-described embodiments.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

By the above-described configuration, the hardware requirement is reduced as compared with the conventional AES encryption device, while miniaturization and low-power integration is possible by implementing the AES encryption device that can maintain the same performance as the conventional, it can be applied to portable devices You can expect.

Claims (15)

An apparatus for encrypting input data according to AES (Advanced Encryption Standard) algorithm, An integrated block that performs a substitution operation of a plain text input for encryption or a substitution operation for key generation using a look-up table; A ShiftRows block for moving a row in a matrix of data on which a substitution operation is performed by the integration block; A MixColums block for further linearly changing data processed by the shift row block unit; A first mux for selectively receiving data transmitted from the shift row block, the mix column block, or the data input unit according to the round processing step for encryption; A key management unit which selectively receives an initial round key input through a key input unit or a round key processed by the integration block, and shifts the stored round key to the integrated block; A second mux for selectively receiving the data transmitted for the encryption or the round key delivered from the key manager and delivering the selected round key to the integrated block; And A round key processing (AddRoundKey) block for receiving the selected data through the first mux, receiving the selected round key through the key manager, and performing a key operation for the encryption. AES algorithm encryption device comprising a. The method of claim 1, wherein the integration block, When receiving the data for encryption from the second mux, it performs a sub-bytes block function to perform the substitution operation of the data to transfer to the shift block, And receiving a round key for generating the key from the second mux, performing a subword block function for performing a substitution operation of the round key and transferring the round key to the key manager. The method of claim 1, wherein the key management unit, A third mux for selectively receiving the initial round key or the round key that has been replaced by the integrated block; A key buffer for receiving and storing the round key transmitted from the third mux; A rotation word block for shifting the round key stored in the key buffer to the third mux; An Rcon block for generating a round constant that is XOR-operated on the round key computed from the integrated block; And A plurality of XOR logic circuits for performing an XOR operation on the round key delivered from the key buffer and the round key delivered from the integrated block AES algorithm encryption apparatus comprising a. The method of claim 1, wherein the first mux, In the initial round processing step, the initial data transmitted from the data input unit is received, in the repetitive round processing step, the data transmitted from the mix column block is received, and in the last round processing step, the data transmitted from the shift row block is received. AES algorithm encryption apparatus, characterized in that. The method of claim 1, A data buffer for storing the data on which the key operation for encryption is performed from the round key processing block and providing the data input to the second mux when the round processing step for encryption is performed. AES algorithm encryption apparatus further comprises. In the encryption method of the input data according to the AES (Advanced Encryption Standard) algorithm, (a) key processing initial data in plain text format input for the encryption using an initial round key; (b) replacing the initial round key using a look-up table to generate a repeat round key for repeat round processing; (c) key processing the keyed initial data using the iterative round key; (d) substituting the iterative round key using the look-up table to generate a last round key for the last round processing; And (e) outputting a cipher text generated by keying the data keyed by the repetitive round key using the last round key; Encryption method of the AES algorithm comprising a. The method of claim 6, wherein step (a) is (a1) receiving the initial round key via a first mux; And (a2) receiving initial data in the plain text format through a second mux and performing key processing using the initial round key Encryption method of the AES algorithm, characterized in that it comprises a. The method of claim 6, The encryption method of the AES algorithm, characterized in that the encryption according to the step (a) to the step (e) is performed according to the first clock and the second clock are composed of a rising level and a falling level. The method according to claim 7 or 8, The step (a1) is executed in the rising level portion of the first clock and the step (a2) is executed in the rising level portion of the second clock, so that the initial round processing according to the step (a) is performed for one clock. The encryption method of the AES algorithm, characterized in that executed. The method of claim 8, wherein step (b) and step (c) The step (b) is performed in the rising level portion of the first clock and the step (c) is executed in the rising level portion of the second clock, thereby performing the steps (b) and (c) for one clock. Iterative round processing according to, characterized in that the encryption method of the AES algorithm. The method of claim 8, wherein step (d) and step (e) The step (d) is executed in the rising level portion of the first clock and the step (e) is executed in the rising level portion of the second clock, thereby performing the steps (d) and (e) for one clock. The encryption method of the AES algorithm, characterized in that the last round processing according to. The method of claim 6, wherein step (b) (b1) performing a shift operation of moving the initial round key; (b2) replacing the shifted initial round key using the look-up table; And (b3) generating the repeating round key by performing an XOR operation on the replaced initial round key and the round constant generated by the Rcon block; Encryption method of the AES algorithm, characterized in that it comprises a. The method of claim 6, wherein step (c) comprises: (c1) replacing the keyed initial data using the look-up table; (c2) performing a shift operation of moving a row in the matrix of the substituted initial data; (c3) linearly converting the data on which the shift operation is performed; And (c4) key processing the linearly transformed data using the iterative round key Encryption method of the AES algorithm, characterized in that it comprises a. The method of claim 6, wherein step (d) (d1) performing a shift operation of moving the repeating round key; (d2) replacing the shifted iterative round key using the look-up table; And (d3) generating the last round key by performing an XOR operation on the replaced round key and the round constant generated by the Rcon block; Encryption method of the AES algorithm, characterized in that it comprises a. The method of claim 6, wherein step (e) (e1) replacing the data keyed by the iterative round key using the look-up table; (e2) performing a shift operation of moving rows in the matrix of substituted data; And (e3) outputting the ciphertext generated by key processing the data on which the shift operation is performed using the last round key; Encryption method of the AES algorithm, characterized in that it comprises a.

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