CN115174802B - Image acquisition card and image acquisition method - Google Patents
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- CN115174802B CN115174802B CN202210641667.4A CN202210641667A CN115174802B CN 115174802 B CN115174802 B CN 115174802B CN 202210641667 A CN202210641667 A CN 202210641667A CN 115174802 B CN115174802 B CN 115174802B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
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Abstract
The application provides an image acquisition card and an image acquisition method, wherein the image acquisition card comprises: the FPGA chip comprises a GPIO module, a packet module and an Ethernet MAC module; wherein: the GPIO module is used for collecting external hard trigger signals and sending the collected hard trigger signals to the packet module; and the packet grouping module is used for assembling a specific network data packet according to the hard trigger signal under the condition of receiving the hard trigger signal, and sending the specific network data packet to an industrial camera through the Ethernet MAC module and the Ethernet PHY chip so as to enable the industrial camera to perform graph processing according to the specific network data packet. The image acquisition card can improve the control efficiency of the industrial camera drawing, reduce the time delay of the industrial camera drawing and improve the stability of the industrial camera drawing control.
Description
Technical Field
The application relates to the field of robot vision perception, in particular to an image acquisition card and an image acquisition method.
Background
Gigabit ethernet industrial cameras using GigE Vision (a standard for gigabit ethernet-based image transmission initiated by automated Vision association AIA (Automated Imaging Association)) protocols are currently common machine Vision solutions. The TOE (Trigger Over Ethernet, ethernet triggering) connects the hardware IO (Input Output) triggering signal to the IO module of the network card, converts the IO signal into a specific Ethernet data packet, sends the specific Ethernet data packet to the industrial camera, and completes the function of triggering the graph of the industrial camera.
In the existing implementation manner, an external hard trigger signal firstly enters a GPIO (General Purpose Input/Output) module in an FPGA (Field ProgrammableGate Array ) to identify the trigger signal, then the FPGA sends the trigger signal to an industrial personal computer (Personal Computer ) through a PCIe (Peripheral Component Interconnect Express, peripheral component interconnect express) Switch and a PCIe interface, then a CPU (Center Process Unit, central processing unit) in the industrial personal computer checks the signal, assembles a specific network packet, sends the packet to the PCIe Switch through the PCIe interface, then sends the packet to a gigabit network special chip, and finally sends the packet to an industrial camera end to complete the function of triggering a graph.
Practice finds that in the scheme, the hard trigger signal is required to be acquired through the FPGA and transmitted to the CPU of the industrial personal computer, then the industrial personal computer assembles a specific network data packet and sends the specific network data packet to the industrial camera, the whole network data packet sending link is too long, and the delay of the industrial camera for receiving the trigger signal is larger. Meanwhile, when the CPU occupation of the industrial PC is relatively high, the problems of blocking, untimely processing and the like exist, so that the industrial camera receives a trigger signal and shakes seriously, and the diagram is influenced.
Disclosure of Invention
In view of this, the present application provides an image capturing card and an image capturing method.
According to a first aspect of embodiments of the present application, there is provided an image capture card, including: the system comprises an FPGA chip and an Ethernet port physical layer PHY chip, wherein the FPGA chip comprises a general purpose input/output signal module GPIO module, a packet module and an Ethernet media intervention control layer MAC module; wherein:
the GPIO module is used for collecting external hard trigger signals and sending the collected hard trigger signals to the packet module;
and the packet grouping module is used for assembling a specific network data packet according to the hard trigger signal under the condition of receiving the hard trigger signal, and sending the specific network data packet to an industrial camera through the Ethernet MAC module and the Ethernet PHY chip so as to enable the industrial camera to perform graph processing according to the specific network data packet.
According to a second aspect of the present application, there is provided an image acquisition method, comprising:
collecting external hard trigger signals through a GPIO module, and sending the collected hard trigger signals to the packet-forming module;
and under the condition that the packet grouping module receives a hard trigger signal, assembling a specific network data packet according to the hard trigger signal, and sending the specific network data packet to an industrial camera through the Ethernet MAC module and the Ethernet PHY chip so as to enable the industrial camera to perform graph processing according to the specific network data packet.
According to the image acquisition card, the FPGA chip and the Ethernet PHY chip are deployed, the FPGA chip can comprise the GPIO module, the packet forming module and the Ethernet MAC module, the FPGA chip can acquire external hard trigger signals through the GPIO module and send the acquired hard trigger signals to the packet forming module, the packet forming module can assemble specific network data packets according to the hard trigger signals under the condition of receiving the hard trigger signals, and the specific network data packets are sent to the industrial camera through the Ethernet MAC module and the Ethernet PHY chip, so that the industrial camera performs drawing processing according to the specific network data packets.
Drawings
Fig. 1 is a schematic structural diagram of an image acquisition card according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of another image capturing card according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of an image acquisition card based on TOE triggering according to an embodiment of the present application;
fig. 4 is a flowchart of an image acquisition method according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
In order to better understand the technical solutions provided by the embodiments of the present application and make the above objects, features and advantages of the embodiments of the present application more obvious, the technical solutions in the embodiments of the present application are described in further detail below with reference to the accompanying drawings.
It should be noted that, the sequence number of each step in the embodiment of the present application does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.
Referring to fig. 1, a schematic structural diagram of an image capturing card provided in an embodiment of the present application, as shown in fig. 1, the image capturing card may include: an FPGA chip 110 and an ethernet PHY (port physical layer) chip 120, the FPGA110 including a GPIO module 111, a packet module 112, and an ethernet MAC (Media Access Control, media access control layer) module 113; wherein:
the GPIO module 111 is configured to collect an external hard trigger signal, and send the collected hard trigger signal to the packet module 112;
the packet grouping module 112 is configured to assemble a specific network data packet according to the hard trigger signal when the hard trigger signal is received, and send the specific network data packet to the industrial camera through the ethernet MAC module 113 and the ethernet PHY chip 120, so that the industrial camera performs a mapping process according to the specific network data packet.
In the embodiment of the application, in order to improve the efficiency and stability of the industrial camera image control, the industrial camera image can be controlled by an image acquisition card including the FPGA chip 110 and the ethernet PHY chip 120.
The image acquisition card can acquire external hard trigger signals through the GPIO module 111 in the FPGA chip 110, and send the acquired hard trigger signals to the packet grouping module 112 so as to trigger the packet grouping module 112 to assemble specific network data packets.
In this embodiment of the present application, when the FPGA chip 110 collects the external hard trigger signal through the GPIO module, the specific network data packet is not required to be assembled and sent through the external PC, but the specific network data packet may be assembled through the packet assembling module 112 according to the hard trigger signal.
The specific network data packet is used for triggering the industrial camera to perform graphic processing.
Illustratively, in the case where the packet grouping module 112 assembles a specific network packet, the specific network packet may be transmitted to the ethernet MAC module 113, and transmitted to the ethernet PHY chip 120 through the ethernet MAC module 113, and transmitted to the industrial camera by the ethernet PHY chip 120.
The industrial camera may perform a mapping process upon receiving the particular network data packet.
It can be seen that, based on the image acquisition card shown in fig. 1, by disposing the FPGA chip and the ethernet PHY chip, the FPGA chip may include a GPIO module, a packet module and an ethernet MAC module, where the FPGA chip may collect an external hard trigger signal through the GPIO module and send the collected hard trigger signal to the packet module, and the packet module may assemble a specific network data packet according to the hard trigger signal and send the specific network data packet to the industrial camera through the ethernet MAC module and the ethernet PHY chip when receiving the hard trigger signal, so that the industrial camera performs a mapping process according to the specific network data packet.
In some embodiments, the GPIO module 111 may be specifically configured to collect an external hard trigger signal, perform signal adjustment on the external hard trigger signal, and send the adjusted hard trigger signal to the packet module 112.
For example, considering that the external hard trigger signal collected by the GPIO module 111 may have unstable conditions such as jitter, and the packet grouping module 112 generally needs to trigger the assembly of the specific network data packet by the rising edge or the falling edge of the hard trigger signal, in order to improve the accuracy of the graph control, when the GPIO module 111 collects the external hard trigger signal, the external hard trigger signal may be subjected to signal adjustment, and the adjusted hard trigger signal is sent to the packet grouping module 112.
For example, the GPIO module 111 may perform jitter filtering on the collected hard trigger signal to remove the glitch of the hard trigger signal.
In some embodiments, the number of ethernet PHY chips 120, packet modules 112, and ethernet MAC modules 113 are all multiple (fig. 1 is a single schematic diagram);
the GPIO module 111 is specifically configured to send the hard trigger signal to part or all of the plurality of packet modules 112 synchronously, so that the packet module that receives the hard trigger signal assembles a specific network data packet, and sends the specific network data packet to the corresponding industrial camera synchronously through the corresponding ethernet MAC module 113 and the ethernet PHY chip 120 respectively.
For example, considering that there may be a situation that a plurality of industrial cameras need to synchronize the pictures in an actual scene, for example, a plurality of industrial cameras with different angles in the same scene, in the conventional scheme, the implementation scheme of assembling the specific network data packet by the industrial control PC can only serially send the plurality of specific network data packets to each industrial camera, which cannot ensure that each industrial camera synchronously pictures.
Thus, in order to realize synchronous drawing of multiple working cameras, the image acquisition card may include multiple (two or more) ethernet PHY chips 120, and the fpga chip 110 may also include multiple packet modules 112 and multiple ethernet MAC modules 113.
The plurality of ethernet PHY chips 120 may be used to transmit specific network packets to different industrial cameras, respectively, and the plurality of packet grouping modules 112 may be used to assemble specific network packets to different industrial cameras, and transmit the specific network packets to corresponding industrial cameras synchronously through different ethernet MAC modules 113 and ethernet PHY chips 120, respectively.
For example, in the case that an external hard trigger signal is acquired by the GPIO module 111, the hard trigger signal may be simultaneously transmitted to some or all of the plurality of packet modules 112.
Illustratively, the FPGA chip 110 may send the hard trigger signal to the corresponding packet module 112 synchronously through the GPIO module 111 according to the industrial camera having the graphic requirement.
For example, the image acquisition card includes 4 ethernet PHY chips 120, which respectively correspond to 4 different industrial cameras, and the FPGA chip 110 includes 4 packet modules 112 and 4 ethernet MAC modules 113, where in the case that synchronous graphics requirements exist for all the 4 industrial cameras, the FPGA chip 110 may send the acquired hard trigger signal to the 4 packet modules 112 synchronously through the GPIO module 111 when the GPIO module 111 acquires the external hard trigger signal, the packet modules assemble specific network data packets, and send the specific network data packets to the corresponding industrial cameras synchronously through the corresponding ethernet MAC modules 113 and the ethernet PHY chips 120 respectively.
Illustratively, the GPIO module 111 may include a plurality of hard trigger input ports;
in one example, the GPIO module 111 may be specifically configured to, when an external hard trigger signal is collected through any hard trigger input port, send the external hard trigger signal to part or all of the plurality of packet grouping modules 112 synchronously, so that the packet grouping module 112 that receives the hard trigger signal assembles a specific network data packet, and send the specific network data packet to a corresponding industrial camera synchronously through the corresponding ethernet MAC module 113 and the ethernet PHY chip 120, respectively.
Illustratively, the GPIO module 111 may include a plurality of hard trigger input ports (IO ports), each of which may be used for hard trigger signal acquisition by the plurality of packet modules 112.
Accordingly, in the case that the GPIO module 111 collects an external hard trigger signal through any hard trigger input port, the external hard trigger signal may be synchronously sent to part or all of the plurality of packet grouping modules 112, so that the packet grouping modules 112 that receive the hard trigger signal assemble a specific network data packet, and synchronously send the specific network data packet to the corresponding industrial camera through the corresponding ethernet MAC module 113 and the ethernet PHY chip 120, respectively.
Illustratively, the FPGA chip 110 may send the hard trigger signal to the corresponding packet module 112 synchronously through the GPIO module 111 according to the industrial camera having the graphic requirement.
In another example, the GPIO module 111 may be specifically configured to determine, when an external hard trigger signal is collected through any hard trigger input port, a packet grouping module 112 corresponding to the hard trigger input port, send the hard trigger signal to the packet grouping module 112, so that the packet grouping module 112 assembles a specific network data packet according to the hard trigger signal, and send the specific network data packet to a corresponding industrial camera through a corresponding ethernet MAC module 113 and an ethernet PHY chip 120.
For example, the GPIO module 111 may include a plurality of hard trigger input ports (IO ports), where each hard trigger input port may respectively correspond to a different packet module 112 and be used to perform hard trigger signal acquisition for the different packet modules 112.
Accordingly, in the case that the GPIO module 111 collects an external hard trigger signal through any hard trigger input port, the corresponding relationship between the hard trigger input port and the packet grouping module 112 may determine the packet grouping module 112 (may be referred to as a target packet grouping module) corresponding to the hard trigger input port that collects the external hard trigger signal, and send the hard trigger signal to the target packet grouping module.
When the target packet module receives the hard trigger signal, it can assemble the specific network data packet according to the hard trigger signal, and send the specific network data packet to the corresponding industrial camera through the corresponding ethernet MAC module 113 and the ethernet PHY chip 120.
Illustratively, in the embodiment of the present application, the GPIO module 111 may implement the correspondence between the hard trigger input port and the packet module through the multiplexer.
For example, the GPIO module 111 may include a multiplexer, where inputs of the multiplexer correspond to different hard trigger input ports, and for hard trigger signals collected from the different hard trigger input ports, the signals may be output to the corresponding packet grouping module 112 through the multiplexer.
Alternatively, the GPIO module 111 may include a plurality of multiplexers, one multiplexer may correspond to one packet module 112, inputs of the plurality of multiplexers may be multiplexed and correspond to a plurality of hard trigger input ports, and accordingly, a hard trigger signal collected from any hard trigger input port may be output to the corresponding packet module 112 through the multiplexer, that is, a hard trigger signal collected from any hard trigger input port may be output to each packet module 112 in the plurality of packet modules 112.
In some embodiments, as depicted in fig. 2, FPGA chip 110 may further include: a CPU (Center Process Unit, central processing unit) soft core (which may also be referred to as soft CPU, software reconfigurable processor) 114; wherein:
the CPU soft core 114 may be configured to receive a configuration instruction of an external PC, and configure a structural parameter of a specific network packet according to the configuration instruction;
the packet assembling module 112 is specifically configured to assemble the specific network data packet according to the structural parameter of the specific network data packet.
For example, the configuration instruction may be sent to the image capture card by an external PC, such as an industrial personal computer, to implement configuration of the configuration parameters of the specific network data packet.
Illustratively, the configuration parameters may include, but are not limited to, a MAC address, an IP address, and a particular packet key (e.g., a protocol field in a particular network packet).
Accordingly, the FPGA chip 110 of the image acquisition card may further include a CPU soft core 114, and the CPU soft core 114 may communicate with an external PC.
For example, the CPU soft core 114 may communicate with an external PC over a PCIe interface.
Illustratively, the FPGA chip 110 may receive a configuration instruction of the external PC through the CPU soft core 114, and configure the structural parameters of the specific network packet according to the configuration instruction.
Illustratively, the CPU soft core 114 may configure the structural parameters of a particular network packet in the registers of the FPGA chip 110.
For example, the packet grouping module 112 may assemble a specific network packet according to the structural parameters of the specific network packet in case of receiving the hard trigger signal.
In one example, the CPU soft core 114 may also be used to configure the type of target hard trigger signal in accordance with the configuration instructions;
the packet module 112 may be specifically configured to assemble a specific network packet if it is determined that the type of the received hard trigger signal matches the type of the target hard trigger signal.
For example, considering that in an actual scenario, the FPGA chip 110 may collect different types of external hard trigger signals through the GPIO module 111, and the roles of the different types of hard trigger signals are generally different, in order to improve the accuracy of industrial camera map control, the types of hard trigger signals (herein referred to as target hard trigger signals) used for triggering industrial camera maps may also be preconfigured.
For example, the configuration of the type of the target hard trigger signal may be achieved by the external PC sending a configuration instruction to the image capture card.
Accordingly, the FPGA chip 110 may receive a configuration instruction of the external PC through the CPU soft core 114, and configure the type of the target hard trigger signal according to the configuration instruction.
The packet grouping module 112 may determine whether the type of the received hard trigger signal matches the type of the target hard trigger signal when the hard trigger signal is received, and assemble a specific network data packet and transmit the specific network data packet to the industrial camera through the ethernet MAC module 113 and the ethernet PHY chip 120 in case that the type of the received hard trigger signal matches the type of the target hard trigger signal, so that the industrial camera performs the graph processing according to the specific network data packet.
It should be noted that, in the case where the type of the received hard trigger signal is determined not to match the type of the target hard trigger signal, the packet module 112 may not respond to the hard trigger signal, or may process according to other policies, which is not limited in the embodiment of the present application.
In order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application, the technical solutions provided by the embodiments of the present application are described below in connection with specific application scenarios.
Referring to fig. 3, a schematic structural diagram of an image acquisition card based on TOE (Trigger Over Ethernet, ethernet triggering) triggering is provided in this embodiment of the present application, as shown in fig. 3, a hardware architecture of the image acquisition card may be a single acquisition card board, and the card board integrates a FGPA chip (may be referred to as a high-performance FPGA chip), a 4-way gigabit ethernet PHY chip, and a PCIe interface, where the FPGA chip includes a GPIO module, a packet module, an ethernet MAC module, a soft CPU, and a PCIe controller. The FPGA chip can realize the operation configuration of the acquisition card through a soft CPU, and is communicated with an external PC (such as an industrial personal computer) through a PCIe (peripheral component interconnect express) interface by using a PCIe (peripheral component interconnect express) controller to build a passage of the industrial camera and a PC upper computer.
In this embodiment, in order to implement transmission of a specific network data packet, the 4 packet modules may be initialized according to an ethernet protocol, and network data packet structure parameters such as a MAC address, an IP address, and a specific data packet key value may be configured.
The FPGA chip can detect external hard trigger signals (such as trigger pulse signals) through the GPIO module, adjust the detected hard trigger signals, such as jitter filtering, send the adjusted hard trigger signals to the packet module, assemble specific network data packets through the packet module, and transmit the specific network data packets to the industrial camera end through the Ethernet MAC module and the Ethernet PHY chip.
The number of the packet modules and the Ethernet MAC modules in the FPGA chip is 4, the packet modules, the Ethernet modules and the Ethernet PHY chips are in one-to-one correspondence, and each network port is mutually independent.
The 4 packet-forming modules can synchronously transmit the assembled specific network data packets to the industrial camera through the corresponding Ethernet MAC module and the Ethernet PHY chip, namely, after an external hard trigger signal is transmitted to the FPGA, the external hard trigger signal can be synchronously issued to the Ethernet MAC module and the Ethernet PHY chip and transmitted to the industrial camera, so that the low delay and low jitter of the industrial camera picture are ensured.
Referring to fig. 4, a flowchart of an image capturing method provided in an embodiment of the present application is shown, where the image capturing method may be applied to an FPGA chip in an image capturing card in the foregoing embodiment, and as shown in fig. 4, the image capturing method may include:
and step 400, collecting an external hard trigger signal through the GPIO module, and sending the collected hard trigger signal to the packet-forming module.
In step S410, under the condition that the hard trigger signal is received by the packet grouping module, a specific network data packet is assembled according to the hard trigger signal, and the specific network data packet is sent to the industrial camera by the ethernet MAC module and the ethernet PHY chip, so that the industrial camera performs the graph processing according to the specific network data packet.
In the embodiment of the application, when the FPGA chip collects the external hard trigger signal through the GPIO module, the specific network data packet is not required to be assembled and sent through the external PC, but the specific network data packet can be assembled through the packet assembling module according to the hard trigger signal.
When the packet-forming module assembles the specific network data packet, the specific network data packet may be sent to the ethernet MAC module, and the specific network data packet may be sent to the ethernet PHY chip by the ethernet MAC module, and the specific network data packet may be sent to the industrial camera by the ethernet PHY chip.
The industrial camera may perform a mapping process upon receiving the particular network data packet.
In some embodiments, the sending the collected hard trigger signal to the packet module may include:
and carrying out signal adjustment on the acquired hard trigger signals, and sending the adjusted hard trigger signals to a packet grouping module.
For example, considering that the external hard trigger signal collected by the GPIO module may have unstable conditions such as jitter, and the packet grouping module generally needs to trigger the assembly of the specific network data packet by the rising edge or the falling edge of the hard trigger signal, in order to improve the accuracy of the graph control, the GPIO module may perform signal adjustment on the external hard trigger signal when collecting the external hard trigger signal, and send the adjusted hard trigger signal to the packet grouping module.
For example, the GPIO module may perform jitter filtering on the collected hard trigger signal to remove the glitch of the hard trigger signal.
In some embodiments, the number of the ethernet PHY chips, the packet-forming modules, and the ethernet MAC modules is plural, and the number of the ethernet PHY chips, the packet-forming modules, and the ethernet MAC modules are matched;
the sending the collected hard trigger signal to the packet grouping module may include:
synchronously transmitting the acquired hard trigger signals to part or all of the plurality of packet forming modules;
the above-mentioned assembling the specific network data packet by the packet assembling module under the condition of receiving the hard trigger signal, and transmitting the specific network data packet to the industrial camera by the ethernet MAC module and the ethernet PHY chip may include:
and assembling the specific network data packet through a packet assembly module which receives the hard trigger signal, and synchronously transmitting the specific network data packet to the corresponding industrial camera through the corresponding Ethernet MAC module and the Ethernet PHY chip respectively.
For example, considering that there may be a situation that a plurality of industrial cameras need to synchronize the pictures in an actual scene, for example, a plurality of industrial cameras with different angles in the same scene, in the conventional scheme, the implementation scheme of assembling the specific network data packet by the industrial control PC can only serially send the plurality of specific network data packets to each industrial camera, which cannot ensure that each industrial camera synchronously pictures.
Therefore, in order to realize synchronous drawing of a plurality of working cameras, the image acquisition card can comprise a plurality of (two or more) Ethernet PHY chips, and the FPGA chip can also comprise a plurality of packet modules and a plurality of Ethernet MAC modules.
The plurality of Ethernet PHY chips can be respectively used for sending specific network data packets to different industrial cameras, and the plurality of packet grouping modules can be respectively used for assembling the specific network data packets sent to the different industrial cameras and synchronously sending the specific network data packets to the corresponding industrial cameras through the different Ethernet MAC modules and the Ethernet PHY chips.
For example, in the case that the GPIO module collects an external hard trigger signal, the hard trigger signal may be synchronously sent to some or all of the plurality of packet modules.
For example, the FPGA chip may send the hard trigger signal to the corresponding packet module synchronously through the GPIO module according to the industrial camera with the graphic requirement.
In one example, the GPIO module may include a plurality of hard trigger input ports;
the sending the collected hard trigger signal to the packet grouping module may include:
under the condition that an external hard trigger signal is acquired through any hard trigger input port, the external hard trigger signal is synchronously transmitted to part or all of a plurality of packet-forming modules;
or alternatively, the first and second heat exchangers may be,
under the condition that an external hard trigger signal is acquired through any hard trigger input port, determining a packet module corresponding to the hard trigger input port, and sending the hard trigger signal to the packet module.
Illustratively, the GPIO module 111 may include a plurality of hard trigger input ports (IO ports), each of which may be used for hard trigger signal acquisition by the plurality of packet modules 112.
In one implementation, each hard trigger input port may be used for hard trigger signal acquisition by the plurality of packet modules. Under the condition that the GPIO module collects external hard trigger signals through any hard trigger input port, the external hard trigger signals can be synchronously sent to part or all of the plurality of packet grouping modules, so that the packet grouping modules receiving the hard trigger signals assemble specific network data packets, and the specific network data packets are synchronously sent to corresponding industrial cameras through corresponding Ethernet MAC modules and Ethernet PHY chips respectively.
In another implementation manner, each hard trigger input port may correspond to a different packet module, and is configured to perform hard trigger signal acquisition for the different packet modules. Under the condition that the GPIO module collects external hard trigger signals through any hard trigger input port, the corresponding relation between the hard trigger input port and the packet grouping module can be used for determining the packet grouping module (which can be called as a target packet grouping module) corresponding to the hard trigger input port which collects the external hard trigger signals, and sending the hard trigger signals to the target packet grouping module.
When the target packet module receives the hard trigger signal, the specific network data packet can be assembled according to the hard trigger signal, and the specific network data packet is sent to the corresponding industrial camera through the corresponding Ethernet MAC module and the Ethernet PHY chip.
Illustratively, in the embodiment of the present application, the GPIO module may implement the correspondence between the hard trigger input port and the packet module through the multiplexer.
For example, the GPIO module may include a multiplexer, where inputs of the multiplexer correspond to different hard trigger input ports, and for hard trigger signals collected from different hard trigger input ports, the hard trigger signals may be output to the corresponding packet-forming module through the multiplexer.
Alternatively, the GPIO module may include a plurality of multiplexers, one multiplexer may correspond to one packet module, inputs of the plurality of multiplexers may be multiplexed, and the multiplexers respectively correspond to the plurality of hard trigger input ports, and accordingly, the hard trigger signal collected from any hard trigger input port may be output to the corresponding packet module through the multiplexer, that is, the hard trigger signal collected by any hard trigger input port may be output to each packet module in the plurality of packet modules.
In some embodiments, the image acquisition method provided in the embodiments of the present application may further include:
receiving a configuration instruction of an external PC through a CPU soft core, and configuring structural parameters of a specific network data packet according to the configuration instruction;
the assembling, by the packet assembling module, the specific network data packet when the hard trigger signal is received may include:
and under the condition that the hard trigger signal is received by the packet grouping module, the specific network data packet is assembled according to the structural parameters of the specific network data packet.
For example, the configuration instruction may be sent to the image capture card by an external PC, such as an industrial personal computer, to implement configuration of the configuration parameters of the specific network data packet.
Illustratively, the configuration parameters may include, but are not limited to, a MAC address, an IP address, and a particular packet key (e.g., a protocol field in a particular network packet).
Correspondingly, the FPGA chip of the image acquisition card can also comprise a CPU soft core, and the CPU soft core can be communicated with an external PC.
For example, the CPU soft core may communicate with an external PC over a PCIe interface.
The FPGA chip may receive a configuration instruction of the external PC through the CPU soft core, and configure the structural parameters of the specific network packet according to the configuration instruction.
For example, the CPU soft core may configure the configuration parameters of a particular network packet in the registers of the FPGA chip.
For example, the packet grouping module may assemble a specific network packet according to a structural parameter of the specific network packet in case of receiving the hard trigger signal.
In an example, the image acquisition method provided in the embodiment of the present application may further include:
configuring the type of the target hard trigger signal according to the configuration instruction through the CPU soft core;
the assembling, by the packet assembling module, the specific network data packet when the hard trigger signal is received may include:
and assembling the specific network data packet by a packet assembling module under the condition that the type of the received hard trigger signal is matched with the type of the target hard trigger signal.
For example, considering that in an actual scenario, the FPGA chip may collect different types of external hard trigger signals through the GPIO module, and the roles of the different types of hard trigger signals are generally different, in order to improve accuracy of industrial camera map control, the types of hard trigger signals (herein referred to as target hard trigger signals) used for triggering industrial camera maps may also be preconfigured.
For example, the configuration of the type of the target hard trigger signal may be achieved by the external PC sending a configuration instruction to the image capture card.
Correspondingly, the FPGA chip can receive a configuration instruction of an external PC through the CPU soft core, and configures the type of the target hard trigger signal according to the configuration instruction.
When the packet grouping module receives the hard trigger signal, the packet grouping module can determine whether the type of the received hard trigger signal is matched with the type of the target hard trigger signal, and when the type of the received hard trigger signal is matched with the type of the target hard trigger signal, the packet grouping module assembles a specific network data packet and sends the specific network data packet to the industrial camera through the Ethernet MAC module and the Ethernet PHY chip so that the industrial camera performs graph processing according to the specific network data packet.
It should be noted that, in the case that the type of the received hard trigger signal is determined to be not matched with the type of the target hard trigger signal, the packet grouping module may not respond to the hard trigger signal, or may process according to other policies, which is not limited in the embodiment of the present application.
It is noted that relational terms such as target and object, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing description of the preferred embodiments of the present invention is not intended to limit the invention to the precise form disclosed, and any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (12)
1. An image acquisition card, comprising: the system comprises an FPGA chip and an Ethernet port physical layer PHY chip, wherein the FPGA chip comprises a general purpose input/output signal module GPIO module, a packet module and an Ethernet media intervention control layer MAC module; wherein:
the GPIO module is used for collecting external hard trigger signals and sending the collected hard trigger signals to the packet module;
the packet grouping module is used for assembling a specific network data packet according to the hard trigger signal and the structural parameters of the specific network data packet under the condition that the hard trigger signal is received, and sending the specific network data packet to an industrial camera through the Ethernet MAC module and the Ethernet PHY chip so that the industrial camera performs graph processing according to the specific network data packet; wherein, the packet grouping module is configured with the structural parameters of the specific network data packet; the structure parameters include a MAC address, an IP address, and a specific packet key.
2. The image capture card of claim 1, wherein the image capture card is configured to capture the image of the object,
the GPIO module is specifically used for collecting external hard trigger signals, carrying out signal adjustment on the external hard trigger signals, and sending the adjusted hard trigger signals to the packet module.
3. The image capture card of claim 1, wherein the number of ethernet PHY chips, the packetizing modules, and the ethernet MAC modules are all plural;
the GPIO module is specifically configured to synchronously send the hard trigger signal to part or all of the plurality of packet grouping modules, so that the packet grouping module that receives the hard trigger signal assembles a specific network data packet, and synchronously sends the specific network data packet to the corresponding industrial camera through the corresponding Ethernet MAC module and the Ethernet PHY chip.
4. The image acquisition card of claim 3 wherein the GPIO module comprises a plurality of hard trigger input ports;
the GPIO module is specifically configured to synchronously send an external hard trigger signal to part or all of the plurality of packet grouping modules when the external hard trigger signal is acquired through any hard trigger input port, so that the packet grouping module that receives the hard trigger signal assembles a specific network data packet, and synchronously sends the specific network data packet to a corresponding industrial camera through a corresponding Ethernet MAC module and the Ethernet PHY chip respectively;
or alternatively, the first and second heat exchangers may be,
the GPIO module is specifically configured to determine a packet module corresponding to the hard trigger input port when an external hard trigger signal is acquired through any hard trigger input port, send the hard trigger signal to the packet module, so that the packet module assembles a specific network data packet according to the hard trigger signal, and send the specific network data packet to a corresponding industrial camera through a corresponding Ethernet MAC module and the Ethernet PHY chip.
5. The image capture card of any of claims 1-4, wherein the FPGA chip further comprises: a central processing unit CPU soft core; wherein:
the CPU soft core is used for receiving a configuration instruction of an external Personal Computer (PC) and configuring structural parameters of a specific network data packet according to the configuration instruction;
the packet assembling module is specifically configured to assemble the specific network data packet according to the structural parameter of the specific network data packet.
6. The image capture card of claim 5, wherein the image capture card is configured to capture the image of the object,
the CPU soft core is also used for configuring the type of the target hard trigger signal according to the configuration instruction;
the packet assembling module is specifically configured to assemble a specific network data packet when it is determined that the type of the received hard trigger signal matches the type of the target hard trigger signal.
7. An image acquisition method, characterized in that it is applied to the FPGA chip in the image acquisition card according to any one of claims 1 to 6, and the method includes:
collecting external hard trigger signals through a GPIO module, and sending the collected hard trigger signals to the packet-forming module;
under the condition that the packet grouping module receives a hard trigger signal, a specific network data packet is assembled according to the hard trigger signal and the structural parameters of the specific network data packet, and the specific network data packet is sent to an industrial camera through the Ethernet MAC module and the Ethernet PHY chip, so that the industrial camera performs drawing processing according to the specific network data packet; wherein, the packet grouping module is configured with the structural parameters of the specific network data packet; the structure parameters include a MAC address, an IP address, and a specific packet key.
8. The method of claim 7, wherein the sending the collected hard trigger signal to the group package module comprises:
and carrying out signal adjustment on the acquired hard trigger signals, and sending the adjusted hard trigger signals to the packet grouping module.
9. The method of claim 7, wherein the number of ethernet PHY chips, the packetizing modules, and the ethernet MAC modules are all plural, and the number of ethernet PHY chips, the packetizing modules, and the ethernet MAC modules are matched;
the sending the collected hard trigger signal to the packet grouping module includes:
synchronously transmitting the acquired hard trigger signals to part or all of the plurality of packet-forming modules;
the step of assembling the specific network data packet by the packet assembling module under the condition of receiving the hard trigger signal, and sending the specific network data packet to the industrial camera by the Ethernet MAC module and the Ethernet PHY chip comprises the following steps:
and assembling a specific network data packet through a packet assembly module which receives the hard trigger signal, and synchronously transmitting the specific network data packet to a corresponding industrial camera through a corresponding Ethernet MAC module and the Ethernet PHY chip respectively.
10. The method of claim 9, wherein the GPIO module comprises a plurality of hard trigger input ports;
the sending the collected hard trigger signal to the packet grouping module includes:
under the condition that an external hard trigger signal is acquired through any hard trigger input port, the external hard trigger signal is synchronously transmitted to part or all of a plurality of packet-forming modules;
or alternatively, the first and second heat exchangers may be,
under the condition that an external hard trigger signal is acquired through any hard trigger input port, determining a packet module corresponding to the hard trigger input port, and sending the hard trigger signal to the packet module.
11. The method according to any one of claims 7-10, further comprising:
receiving a configuration instruction of an external Personal Computer (PC) through a CPU soft core, and configuring structural parameters of a specific network data packet according to the configuration instruction;
the assembling, by the packet assembling module, a specific network data packet when receiving a hard trigger signal, including:
and under the condition that the packet grouping module receives the hard trigger signal, assembling the specific network data packet according to the structural parameters of the specific network data packet.
12. The method of claim 11, wherein the method further comprises:
configuring the type of the target hard trigger signal according to the configuration instruction through the CPU soft core;
the assembling, by the packet assembling module, a specific network data packet when receiving a hard trigger signal, including:
and assembling a specific network data packet by the packet assembling module under the condition that the type of the received hard trigger signal is matched with the type of the target hard trigger signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210641667.4A CN115174802B (en) | 2022-06-07 | 2022-06-07 | Image acquisition card and image acquisition method |
| PCT/CN2023/092204 WO2023236696A1 (en) | 2022-06-07 | 2023-05-05 | Image acquisition card and image acquisition method |
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| CN202210641667.4A CN115174802B (en) | 2022-06-07 | 2022-06-07 | Image acquisition card and image acquisition method |
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| WO2023236696A1 (en) | 2023-12-14 |
| CN115174802A (en) | 2022-10-11 |
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