CN115174802A - Image acquisition card and image acquisition method - Google Patents
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- H—ELECTRICITY
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Abstract
The application provides an image acquisition card and an image acquisition method, wherein the image acquisition card comprises: the FPGA chip comprises a GPIO module, a group packaging module and an Ethernet MAC module; wherein: the GPIO module is used for acquiring an external hard trigger signal and sending the acquired hard trigger signal to the group package module; the group package module is used for assembling a specific network data package according to the hard trigger signal under the condition that the hard trigger signal is received, and sending the specific network data package to an industrial camera through the Ethernet MAC module and the Ethernet PHY chip, so that the industrial camera carries out image processing according to the specific network data package. The image acquisition card can improve the control efficiency of the image drawing of the industrial camera, reduce the time delay of the image drawing of the industrial camera and improve the stability of the image drawing control of the industrial camera.
Description
Technical Field
The application relates to the field of robot visual perception, in particular to an image acquisition card and an image acquisition method.
Background
The gigabit ethernet industrial camera using GigE Vision (a standard for image transmission over gigabit ethernet initiated by Automated Imaging Association (AIA)) protocol is currently a common machine Vision solution. The TOE (Trigger Over Ethernet, ethernet Trigger) connects a hardware IO (Input Output ) Trigger signal to an IO module of the network card, converts the IO signal into a specific Ethernet packet, and sends the Ethernet packet to the industrial camera, thereby completing a Trigger map function of the industrial camera.
In an existing implementation manner, an external hard trigger signal first enters a General Purpose Input/Output (GPIO) module in a Field Programmable Gate Array (FPGA) to recognize a trigger signal, then the FPGA sends the trigger signal to a Personal Computer (PC) through a Peripheral Component Interconnect Express (PCIe) Switch (Switch) and a PCIe interface, and then a Central Processing Unit (CPU) in the PC checks the trigger signal, assembles a specific network packet, sends the network packet to the PCIe Switch through the PCIe interface, sends the network packet to a gigabit network dedicated chip, and sends the network packet to an industrial camera end, thereby completing triggering a graph function.
Practice shows that in the above scheme, the hard trigger signal needs to be acquired by the FPGA and transmitted to the CPU of the industrial PC, and then the industrial PC assembles the specific network data packet and transmits the network data packet to the industrial camera, the transmission link of the whole network data packet is too long, and the industrial camera has a large delay when receiving the trigger signal. Meanwhile, when the CPU of the industrial PC occupies a relatively high area, the problems of jamming, untimely processing and the like exist, so that the jitter of the trigger signal received by the industrial camera end is serious, and the output is influenced.
Disclosure of Invention
In view of the above, the present application provides an image capturing card and an image capturing method.
According to a first aspect of embodiments of the present application, there is provided an image acquisition card comprising: the FPGA chip comprises a general input/output signal (GPIO) module, a group packaging module and an Ethernet media intervention control layer (MAC) module; wherein:
the GPIO module is used for acquiring an external hard trigger signal and sending the acquired hard trigger signal to the group package module;
the group packaging module is used for packaging a specific network data packet according to the hard trigger signal under the condition that the hard trigger signal is received, and sending the specific network data packet to an industrial camera through the Ethernet MAC module and the Ethernet PHY chip so that the industrial camera can carry out image processing according to the specific network data packet.
According to a second aspect of the present application, there is provided an image acquisition method comprising:
acquiring an external hard trigger signal through a GPIO (general purpose input/output) module, and sending the acquired hard trigger signal to the group package module;
and under the condition that the group package module receives a hard trigger signal, a specific network data package is assembled according to the hard trigger signal, and the specific network data package is sent to the industrial camera through the Ethernet MAC module and the Ethernet PHY chip, so that the industrial camera carries out map processing according to the specific network data package.
According to the image acquisition card, the FPGA chip and the Ethernet PHY chip are deployed, the FPGA chip can comprise a GPIO module, a group package module and an Ethernet MAC module, the FPGA chip can acquire external hard trigger signals through the GPIO module and sends the acquired hard trigger signals to the group package module, the group package module can assemble specific network data packets according to the hard trigger signals under the condition that the hard trigger signals are received, and the specific network data packets are sent to an industrial camera through the Ethernet MAC module and the Ethernet PHY chip, so that the industrial camera can carry out plotting processing according to the specific network data packets.
Drawings
FIG. 1 is a schematic structural diagram of an image acquisition card according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of another image acquisition card according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of an image acquisition card based on TOE triggering according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart of an image acquisition method according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
In order to make the technical solutions provided in the embodiments of the present application better understood and make the above objects, features and advantages of the embodiments of the present application more comprehensible, the technical solutions in the embodiments of the present application are described in further detail below with reference to the accompanying drawings.
It should be noted that, the sequence numbers of the steps in the embodiments of the present application do not mean the execution sequence, and the execution sequence of each process should be determined by the function and the inherent logic of the process, and should not constitute any limitation to the implementation process of the embodiments of the present application.
Referring to fig. 1, a schematic structural diagram of an image acquisition card according to an embodiment of the present disclosure is shown in fig. 1, where the image acquisition card may include: the FPGA chip 110 and the ethernet PHY (port physical layer) chip 120, the fpga110 includes a GPIO module 111, a group package module 112, and an ethernet MAC (Media Access Control) module 113; wherein:
the GPIO module 111 is configured to acquire an external hard trigger signal and send the acquired hard trigger signal to the group packet module 112;
the group package module 112 is configured to, in a case that the hard trigger signal is received, package the specific network data packet according to the hard trigger signal, and send the specific network data packet to the industrial camera through the ethernet MAC module 113 and the ethernet PHY chip 120, so that the industrial camera performs an image process according to the specific network data packet.
In the embodiment of the present application, in order to improve the efficiency and stability of the map output control of the industrial camera, the map output of the industrial camera may be controlled by an image acquisition card including the FPGA chip 110 and the ethernet PHY chip 120.
The image acquisition card can acquire an external hard trigger signal through the GPIO module 111 in the FPGA chip 110, and send the acquired hard trigger signal to the group package module 112, so as to trigger the group package module 112 to perform specific network packet assembly.
In the embodiment of the present application, under the condition that the FPGA chip 110 acquires the external hard trigger signal through the GPIO module, the specific network data packet does not need to be assembled and sent through the external PC, but the specific network data packet may be assembled according to the hard trigger signal through the group assembly module 112.
Wherein, the special network data packet is used for triggering the industrial camera to carry out the drawing processing.
For example, in a case that the group packaging module 112 assembles a specific network packet, the specific network packet may be sent to the ethernet MAC module 113, and sent to the ethernet PHY chip 120 through the ethernet MAC module 113, and the ethernet PHY chip 120 sends the specific network packet to the industrial camera.
The industrial camera can perform the plotting process upon receiving the specific network packet.
It can be seen that, based on the image acquisition card shown in fig. 1, by deploying the FPGA chip and the ethernet PHY chip, the FPGA chip may include a GPIO module, a group packet module, and an ethernet MAC module, the FPGA chip may acquire an external hard trigger signal through the GPIO module and transmit the acquired hard trigger signal to the group packet module, and the group packet module may assemble a specific network data packet according to the hard trigger signal under the condition that the hard trigger signal is received, and transmit the specific network data packet to the industrial camera through the ethernet MAC module and the ethernet PHY chip, so that the industrial camera performs an image output process according to the specific network data packet.
In some embodiments, the GPIO block 111 may be specifically configured to acquire an external hard trigger signal, perform signal adjustment on the external hard trigger signal, and send the adjusted hard trigger signal to the group packet block 112.
For example, considering that there may be unstable conditions such as jitter and the like in the external hard trigger signal collected by the GPIO module 111, the group packet module 112 generally needs to trigger the assembly of a specific network data packet by a rising edge or a falling edge of the hard trigger signal, and in order to improve the accuracy of graph control, when the external hard trigger signal is collected by the GPIO module 111, the external hard trigger signal may be signal-adjusted, and the adjusted hard trigger signal is sent to the group packet module 112.
For example, the GPIO block 111 may perform jitter filtering on the collected hard trigger signal to remove glitches of the hard trigger signal.
In some embodiments, the number of ethernet PHY chips 120, group packet modules 112, and ethernet MAC modules 113 is multiple (fig. 1 is a single schematic);
the GPIO module 111 is specifically configured to synchronously send the hard trigger signal to part or all of the plurality of group packet modules 112, so that the group packet modules that receive the hard trigger signal assemble specific network packets, and synchronously send the specific network packets to corresponding industrial cameras through the corresponding ethernet MAC modules 113 and the ethernet PHY chips 120, respectively.
For example, considering that there may be a situation in which multiple industrial cameras need to be synchronously plotted in an actual scene, for example, multiple industrial cameras from different angles in the same scene, an implementation scheme for assembling a specific network data packet through an industrial control PC in a conventional scheme can only send multiple specific network data packets to each industrial camera in series, and cannot guarantee that each industrial camera is synchronously plotted.
Therefore, in order to achieve the synchronous drawing of a plurality of working cameras, the image acquisition card may include a plurality of (two or more) ethernet PHY chips 120, and the fpga chip 110 may also include a plurality of group packet modules 112 and a plurality of ethernet MAC modules 113.
The ethernet PHY chips 120 may be respectively configured to send specific network data packets to different industrial cameras, and the group packet modules 112 may be respectively configured to assemble specific network data packets sent to different industrial cameras, and synchronously send the specific network data packets to corresponding industrial cameras through different ethernet MAC modules 113 and the ethernet PHY chips 120, respectively.
Illustratively, the GPIO module 111 may transmit the external hard trigger signal to all or part of the plurality of group packet modules 112 in synchronization when the hard trigger signal is acquired.
Illustratively, the FPGA chip 110 may send the hard trigger signal to the corresponding group packet module 112 synchronously through the GPIO module 111 according to the industrial camera with the drawing requirement.
For example, the image acquisition card includes 4 ethernet PHY chips 120, which respectively correspond to 4 different industrial cameras, and the FPGA chip 110 includes 4 group packet modules 112 and 4 ethernet MAC modules 113, where all of the 4 industrial cameras have a requirement for synchronization map, the FPGA chip 110 may synchronously send the acquired hard trigger signal to the 4 group packet modules 112 through the GPIO module 111 under the condition that the GPIO module 111 acquires an external hard trigger signal, and the group packet modules assemble specific network data packets, and synchronously send the specific network data packets to the corresponding industrial cameras through the corresponding ethernet PHY chips 120 and the ethernet PHY modules 113.
Illustratively, the GPIO block 111 may include a plurality of hard-trigger input ports;
in one example, the GPIO module 111 may be specifically configured to, when an external hard trigger signal is collected through any one of the hard trigger input ports, synchronously send the external hard trigger signal to some or all of the group packet modules 112, so that the group packet module 112 that receives the hard trigger signal assembles a specific network data packet, and synchronously sends the specific network data packet to a corresponding industrial camera through a corresponding ethernet MAC module 113 and an ethernet PHY chip 120, respectively.
Illustratively, the GPIO module 111 may include a plurality of hard trigger input ports (IO ports), each of which may be used for the group packet modules 112 to perform hard trigger signal acquisition.
Accordingly, when the GPIO module 111 acquires the external hard trigger signal through any hard trigger input port, the external hard trigger signal may be synchronously transmitted to all or part of the plurality of group packet modules 112, so that the group packet module 112 that receives the hard trigger signal assembles a specific network packet, and synchronously transmits the specific network packet to the corresponding industrial camera through the corresponding ethernet MAC module 113 and the ethernet PHY chip 120, respectively.
Illustratively, the FPGA chip 110 may synchronously send the hard trigger signal to the corresponding group packet module 112 through the GPIO module 111 according to the industrial camera with the drawing requirement.
In another example, the GPIO module 111 may be specifically configured to determine, when an external hard trigger signal is collected through any one of the hard trigger input ports, the group packet module 112 corresponding to the hard trigger input port, send the hard trigger signal to the group packet module 112, so that the group packet module 112 assembles a specific network packet according to the hard trigger signal, and sends the specific network packet to the corresponding industrial camera through the corresponding ethernet MAC module 113 and the ethernet PHY chip 120.
For example, the GPIO module 111 may include a plurality of hard trigger input ports (IO ports), and each hard trigger input port may correspond to a different group packet module 112, respectively, and is configured to perform hard trigger signal acquisition for the different group packet modules 112.
Accordingly, when the GPIO module 111 acquires an external hard trigger signal through any hard trigger input port, the corresponding relationship between the hard trigger input port and the group packet module 112 may be used to determine the group packet module 112 (which may be referred to as a target group packet module) corresponding to the hard trigger input port that acquires the external hard trigger signal, and send the hard trigger signal to the target group packet module.
When the target group package module receives the hard trigger signal, it may assemble a specific network data package according to the hard trigger signal, and send the specific network data package to the corresponding industrial camera through the corresponding ethernet MAC module 113 and the ethernet PHY chip 120.
For example, in the embodiment of the present application, the GPIO module 111 may implement the hard-trigger input port corresponding to the group packet module through a multiplexer.
For example, the GPIO block 111 may include a multiplexer, inputs of the multiplexer respectively correspond to different hard trigger input ports, and the hard trigger signals collected from the different hard trigger input ports may be output to the corresponding group packet block 112 through the multiplexer.
Or, the GPIO module 111 may include a plurality of multiplexers, one multiplexer may correspond to one group packet module 112, inputs of the plurality of multiplexers may be multiplexed and respectively correspond to a plurality of hard trigger input ports, and accordingly, the hard trigger signal collected from any hard trigger input port may be output to the corresponding group packet module 112 through the multiplexers, that is, the hard trigger signal collected by any hard trigger input port may be output to each group packet module 112 in the plurality of group packet modules 112.
In some embodiments, as illustrated in fig. 2, the FPGA chip 110 may further include: a CPU (central processing Unit) soft core (may also be referred to as soft CPU, software reconfigurable processor) 114; wherein:
the CPU soft core 114 may be configured to receive a configuration instruction from an external PC, and configure the configuration parameters of the specific network data packet according to the configuration instruction;
the packaging module 112 is specifically configured to assemble the specific network data packet according to the structural parameter of the specific network data packet.
For example, the configuration instruction may be sent to the image acquisition card by an external PC, such as an industrial PC, to implement configuration of the configuration parameters of the specific network data packet.
Illustratively, the configuration parameters may include, but are not limited to, a MAC address, an IP address, and a specific packet key (e.g., a protocol field in a specific network packet).
Correspondingly, the FPGA chip 110 of the image acquisition card may further include a CPU soft core 114, and the CPU soft core 114 may communicate with an external PC.
For example, the CPU soft core 114 may communicate with an external PC over a PCIe interface.
Illustratively, the FPGA chip 110 may receive a configuration instruction of an external PC through the CPU soft core 114, and configure the configuration parameters of a specific network packet according to the configuration instruction.
Illustratively, the CPU soft core 114 may configure the configuration parameters of a particular network packet in registers of the FPGA chip 110.
For example, the group packing module 112 may pack the specific network data packet according to the structure parameter of the specific network data packet when receiving the hard trigger signal.
In one example, the CPU soft core 114 may also be configured to configure the type of target hard trigger signal according to the configuration instruction;
the group packaging module 112 may be specifically configured to assemble a specific network packet if it is determined that the type of the received hard trigger signal matches the type of the target hard trigger signal.
For example, considering that in an actual scenario, the FPGA chip 110 may acquire different types of external hard trigger signals through the GPIO module 111, and the different types of hard trigger signals generally have different roles, therefore, in order to improve the accuracy of the industrial camera image control, the type of hard trigger signal (referred to as a target hard trigger signal herein) for triggering the industrial camera image may be preconfigured.
For example, the type of the target hard trigger signal can be configured in a manner that an external PC sends a configuration instruction to the image acquisition card.
Accordingly, the FPGA chip 110 may receive a configuration instruction of an external PC through the CPU soft core 114, and configure the type of the target hard trigger signal according to the configuration instruction.
The group package module 112 may determine whether the type of the received hard trigger signal matches the type of the target hard trigger signal when receiving the hard trigger signal, and assemble a specific network data packet and transmit the specific network data packet to the industrial camera through the ethernet MAC module 113 and the ethernet PHY chip 120 in case that the type of the received hard trigger signal matches the type of the target hard trigger signal, so that the industrial camera performs an image processing according to the specific network data packet.
It should be noted that, when determining that the type of the received hard trigger signal does not match the type of the target hard trigger signal, the group package module 112 may not respond to the hard trigger signal, or may process the received hard trigger signal according to another policy, which is not limited in this embodiment of the present invention.
In order to enable those skilled in the art to better understand the technical solutions provided in the embodiments of the present application, the following describes the technical solutions provided in the embodiments of the present application with reference to specific application scenarios.
Referring to fig. 3, a schematic structural diagram of an image acquisition card triggered based on TOE (Trigger Over Ethernet) is provided in an embodiment of the present invention, as shown in fig. 3, a hardware architecture of the image acquisition card may be a single acquisition card board, the board integrates an FGPA chip (which may be referred to as a high performance FPGA chip), a 4-way gigabit Ethernet PHY chip, and a PCIe interface, and the FPGA chip includes a GPIO module, a group packaging module, an Ethernet MAC module, a soft CPU, and a PCIe controller. The FPGA chip can realize the operation configuration of the acquisition card through the soft CPU, and can communicate with an external PC (such as an industrial PC) through a PCIe controller by using a high-speed PCIe interface to build a channel between the industrial camera and the PC upper computer.
In this embodiment, in order to implement sending of a specific network packet, 4 packet group modules may be initialized according to an ethernet protocol, and network packet structure parameters such as a MAC address, an IP address, and a specific packet key value may be configured.
The FPGA chip can detect an external hard trigger signal (such as a trigger pulse signal) through the GPIO module, adjust the detected hard trigger signal, such as jitter filtering, send the adjusted hard trigger signal to the packet module, assemble a specific network data packet by the packet module, and transmit the specific network data packet to an industrial camera terminal through the Ethernet MAC module and the Ethernet PHY chip.
Illustratively, the number of the group package modules and the number of the ethernet MAC modules in the FPGA chip are 4, and the group package modules, the ethernet modules and the ethernet PHY chips are in one-to-one correspondence, and each network port is independent.
The 4 group packet modules can synchronously transmit the assembled specific network data packet to the industrial camera through the corresponding Ethernet MAC module and the corresponding Ethernet PHY chip, namely, after an external hard trigger signal is sent to the interior of the FPGA, the external hard trigger signal can be synchronously issued to the Ethernet MAC module and the Ethernet PHY chip and transmitted to the industrial camera, and therefore low delay and low jitter of the industrial camera are guaranteed.
Referring to fig. 4, a schematic flow chart of an image capturing method provided in an embodiment of the present application is shown, where the image capturing method may be applied to an FPGA chip in an image capturing card in the foregoing embodiment, and as shown in fig. 4, the image capturing method may include:
and S400, acquiring an external hard trigger signal through the GPIO module, and sending the acquired hard trigger signal to the packet module.
Step S410, assembling a specific network data packet according to the hard trigger signal under the condition that the hard trigger signal is received by the group packaging module, and sending the specific network data packet to the industrial camera through the ethernet MAC module and the ethernet PHY chip, so that the industrial camera performs the map process according to the specific network data packet.
In the embodiment of the application, under the condition that the FPGA chip acquires the external hard trigger signal through the GPIO module, the specific network data packet does not need to be assembled and sent through an external PC, but the specific network data packet can be assembled according to the hard trigger signal through the group packaging module.
When the group packet module assembles the specific network packet, the specific network packet may be sent to the ethernet MAC module, and sent to the ethernet PHY chip by the ethernet MAC module, and sent to the industrial camera by the ethernet PHY chip.
The industrial camera can perform the plotting process upon receiving the specific network packet.
In some embodiments, the sending the collected hard trigger signal to the packet grouping module may include:
and adjusting the acquired hard trigger signal, and sending the adjusted hard trigger signal to the packet module.
For example, considering that there may be unstable conditions such as jitter and the like in the external hard trigger signal collected by the GPIO module, the group packet module generally needs to trigger the assembly of a specific network data packet by a rising edge or a falling edge of the hard trigger signal, and in order to improve the accuracy of the graph control, when the external hard trigger signal is collected by the GPIO module, the external hard trigger signal may be signal-adjusted, and the adjusted hard trigger signal is sent to the group packet module.
For example, the GPIO module may perform jitter filtering on the collected hard trigger signal to remove glitches of the hard trigger signal.
In some embodiments, the number of the ethernet PHY chips, the number of the group packaging modules, and the number of the ethernet MAC modules are all plural, and the numbers of the ethernet PHY chips, the number of the group packaging modules, and the number of the ethernet MAC modules are matched;
the sending the collected hard trigger signal to the packet grouping module may include:
synchronously sending the collected hard trigger signals to part or all of the plurality of group packet modules;
the assembling a specific network data packet by the group packaging module under the condition of receiving the hard trigger signal, and sending the specific network data packet to the industrial camera by the ethernet MAC module and the ethernet PHY chip may include:
and assembling the specific network data packet through the group packaging module which receives the hard trigger signal, and synchronously sending the specific network data packet to the corresponding industrial camera through the corresponding Ethernet MAC module and the Ethernet PHY chip respectively.
For example, considering that a plurality of industrial cameras may need to be synchronously plotted in an actual scene, for example, a plurality of industrial cameras in different angles in the same scene, in the conventional scheme, the implementation scheme of assembling a specific network data packet by an industrial PC can only send a plurality of specific network data packets to each industrial camera in series, and cannot guarantee that each industrial camera is synchronously plotted.
Therefore, in order to realize the synchronous drawing of a plurality of working cameras, the image acquisition card may include a plurality of (two or more) ethernet PHY chips, and the FPGA chip may also include a plurality of group packet modules and a plurality of ethernet MAC modules.
The plurality of Ethernet PHY chips can be respectively used for sending specific network data packets to different industrial cameras, and the plurality of group packaging modules can be respectively used for assembling the specific network data packets sent to different industrial cameras and synchronously sending the specific network data packets to the corresponding industrial cameras through different Ethernet MAC modules and the Ethernet PHY chips.
Illustratively, the GPIO module may transmit the hard trigger signal to all or part of the plurality of packetization modules in synchronization when an external hard trigger signal is acquired.
Illustratively, the FPGA chip may send the hard trigger signal to the corresponding group packet module synchronously through the GPIO module according to the industrial camera having the drawing requirement.
In one example, the GPIO module may include a plurality of hard-trigger input ports;
the sending the collected hard trigger signal to the packet grouping module may include:
under the condition that an external hard trigger signal is acquired through any hard trigger input port, the external hard trigger signal is synchronously sent to part or all of the group package modules;
or the like, or, alternatively,
and under the condition that an external hard trigger signal is acquired through any hard trigger input port, determining a group package module corresponding to the hard trigger input port, and sending the hard trigger signal to the group package module.
Illustratively, the GPIO block 111 may include a plurality of hard-trigger input ports (IO ports), each of which may be used for the group packet block 112 to perform hard-trigger signal acquisition.
In one implementation, each hard trigger input port may be used for the group packet modules to perform hard trigger signal acquisition. Under the condition that the GPIO module acquires an external hard trigger signal through any hard trigger input port, the external hard trigger signal can be synchronously sent to part or all of the plurality of group package modules, so that the group package modules receiving the hard trigger signal assemble specific network data packages, and synchronously send the specific network data packages to the corresponding industrial cameras through the corresponding Ethernet MAC modules and the corresponding Ethernet PHY chips.
In another implementation manner, each hard trigger input port may correspond to a different group package module, and is configured to perform hard trigger signal acquisition for the different group package modules. Under the condition that the GPIO module collects an external hard trigger signal through any hard trigger input port, the corresponding relation between the hard trigger input port and the group package module can be used for determining the group package module (which can be called as a target group package module) corresponding to the hard trigger input port collecting the external hard trigger signal, and sending the hard trigger signal to the target group package module.
When the target group package module receives the hard trigger signal, specific network data package assembly can be carried out according to the hard trigger signal, and the specific network data package is sent to the corresponding industrial camera through the corresponding Ethernet MAC module and the Ethernet PHY chip.
For example, in the embodiment of the present application, the GPIO module may implement the hard-trigger input port corresponding to the group packet module through the multiplexer.
For example, the GPIO module may include a multiplexer, inputs of the multiplexer respectively correspond to different hard trigger input ports, and the hard trigger signals collected from the different hard trigger input ports may be output to corresponding group packet modules through the multiplexer.
Or, the GPIO module may include multiple multiplexers, one multiplexer may correspond to one group packet module, inputs of the multiple multiplexers may be multiplexed and respectively correspond to multiple hard trigger input ports, and accordingly, a hard trigger signal collected from any hard trigger input port may be output to a corresponding group packet module through the multiplexers, that is, a hard trigger signal collected by any hard trigger input port may be output to each group packet module in the group packet modules.
In some embodiments, the image capturing method provided in the embodiments of the present application may further include:
receiving a configuration instruction of an external PC through a CPU soft core, and configuring the structural parameters of a specific network data packet according to the configuration instruction;
the assembling, by the group packaging module, a specific network data packet under the condition of receiving the hard trigger signal may include:
and assembling the specific network data packet according to the structural parameter of the specific network data packet by the group packaging module under the condition of receiving the hard trigger signal.
Illustratively, the configuration instruction may be sent to the image acquisition card by an external PC, such as an industrial PC, so as to implement configuration of the structural parameters of the specific network data packet.
Illustratively, the configuration parameters may include, but are not limited to, a MAC address, an IP address, and a specific packet key (e.g., a protocol field in a specific network packet).
Correspondingly, the FPGA chip of the image acquisition card can also comprise a CPU soft core, and the CPU soft core can be communicated with an external PC.
For example, the CPU soft core may communicate with an external PC over a PCIe interface.
Illustratively, the FPGA chip may receive a configuration instruction of an external PC through the CPU soft core, and configure a configuration parameter of a specific network packet according to the configuration instruction.
For example, the CPU soft core may configure the configuration parameters of a particular network packet in a register of the FPGA chip.
For example, the group packaging module may assemble the specific network data packet according to the structural parameter of the specific network data packet when receiving the hard trigger signal.
In an example, the image capturing method provided in the embodiment of the present application may further include:
configuring the type of a target hard trigger signal through a CPU soft core according to the configuration instruction;
the assembling, by the group packaging module, a specific network data packet under the condition of receiving the hard trigger signal may include:
and assembling the specific network data packet by the group packaging module under the condition that the type of the received hard trigger signal is determined to be matched with the type of the target hard trigger signal.
For example, considering that in a practical scenario, the FPGA chip may acquire different types of external hard trigger signals through the GPIO module, and the roles of the different types of hard trigger signals are usually different, in order to improve the accuracy of the graph control of the industrial camera, the type of the hard trigger signal (referred to as a target hard trigger signal herein) for triggering the graph of the industrial camera may also be configured in advance.
For example, the type of the target hard trigger signal can be configured by sending a configuration instruction to the image acquisition card through an external PC.
Correspondingly, the FPGA chip can receive a configuration instruction of an external PC through the CPU soft core and configure the type of the target hard trigger signal according to the configuration instruction.
When receiving the hard trigger signal, the group package module can determine whether the type of the received hard trigger signal is matched with the type of the target hard trigger signal, and under the condition that the type of the received hard trigger signal is matched with the type of the target hard trigger signal, a specific network data package is assembled and sent to the industrial camera through the Ethernet MAC module and the Ethernet PHY chip, so that the industrial camera performs graph processing according to the specific network data package.
It should be noted that, when determining that the type of the received hard trigger signal does not match the type of the target hard trigger signal, the group package module may not respond to the hard trigger signal, or may perform processing according to other policies, which is not limited in this embodiment of the present invention.
It is noted that, in this document, relational terms such as target and target, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (12)
1. An image acquisition card, comprising: the FPGA chip comprises a general input/output signal (GPIO) module, a group packaging module and an Ethernet media intervention control layer (MAC) module; wherein:
the GPIO module is used for acquiring an external hard trigger signal and sending the acquired hard trigger signal to the group package module;
the group packaging module is used for packaging a specific network data packet according to the hard trigger signal under the condition that the hard trigger signal is received, and sending the specific network data packet to an industrial camera through the Ethernet MAC module and the Ethernet PHY chip so that the industrial camera can carry out image processing according to the specific network data packet.
2. The image acquisition card according to claim 1,
the GPIO module is specifically used for acquiring an external hard trigger signal, adjusting the external hard trigger signal, and sending the adjusted hard trigger signal to the group package module.
3. The image acquisition card according to claim 1, wherein the number of said ethernet PHY chips, said group package modules, and said ethernet MAC modules is plural;
the GPIO module is specifically configured to send the hard trigger signal to part or all of the plurality of group packet modules in synchronization, so that the group packet modules that receive the hard trigger signal assemble specific network packets, and send the specific network packets to corresponding industrial cameras in synchronization through corresponding ethernet MAC modules and the ethernet PHY chips, respectively.
4. The image acquisition card of claim 3, wherein the GPIO module comprises a plurality of hard-trigger input ports;
the GPIO module is specifically used for synchronously sending the external hard trigger signal to part or all of the group package modules under the condition that the external hard trigger signal is acquired through any hard trigger input port, so that the group package modules receiving the hard trigger signal assemble specific network data packets, and synchronously sending the specific network data packets to corresponding industrial cameras through corresponding Ethernet MAC modules and the Ethernet PHY chips respectively;
or the like, or, alternatively,
the GPIO module is specifically configured to determine a group packet module corresponding to any one of the hard trigger input ports when an external hard trigger signal is acquired through the hard trigger input port, and send the hard trigger signal to the group packet module, so that the group packet module assembles a specific network packet according to the hard trigger signal, and sends the specific network packet to a corresponding industrial camera through a corresponding ethernet MAC module and the ethernet PHY chip.
5. The image acquisition card according to any one of claims 1 to 4, wherein the FPGA chip further comprises: a Central Processing Unit (CPU) soft core; wherein:
the CPU soft core is used for receiving a configuration instruction of an external Personal Computer (PC) and configuring the structural parameters of a specific network data packet according to the configuration instruction; the structure parameters comprise MAC addresses, IP addresses and specific data packet key values;
the group packaging module is specifically used for assembling the specific network data packet according to the structural parameters of the specific network data packet.
6. The image acquisition card according to claim 5,
the CPU soft core is also used for configuring the type of a target hard trigger signal according to the configuration instruction;
the group package module is specifically configured to assemble a specific network data packet when it is determined that the type of the received hard trigger signal matches the type of the target hard trigger signal.
7. An image acquisition method applied to the FPGA chip in the image acquisition card according to any one of claims 1 to 6, the method comprising:
acquiring an external hard trigger signal through a GPIO (general purpose input/output) module, and sending the acquired hard trigger signal to the group package module;
and under the condition that a hard trigger signal is received through the group packaging module, a specific network data packet is assembled according to the hard trigger signal, and the specific network data packet is sent to an industrial camera through the Ethernet MAC module and the Ethernet PHY chip, so that the industrial camera carries out image processing according to the specific network data packet.
8. The method of claim 7, wherein sending the acquired hard trigger signal to the group package module comprises:
and performing signal adjustment on the acquired hard trigger signal, and sending the adjusted hard trigger signal to the group package module.
9. The method of claim 7, wherein the number of the ethernet PHY chips, the group package modules, and the ethernet MAC modules are all plural and match;
the sending the collected hard trigger signal to the group package module includes:
synchronously sending the acquired hard trigger signals to part or all of the group package modules;
the assembling a specific network data packet by the group packaging module under the condition of receiving a hard trigger signal, and sending the specific network data packet to an industrial camera by the ethernet MAC module and the ethernet PHY chip includes:
and assembling a specific network data packet through the group packaging module which receives the hard trigger signal, and synchronously sending the specific network data packet to the corresponding industrial camera through the corresponding Ethernet MAC module and the Ethernet PHY chip respectively.
10. The method of claim 9, wherein the GPIO module includes a plurality of hard-trigger input ports;
the sending the collected hard trigger signal to the group package module includes:
under the condition that an external hard trigger signal is acquired through any hard trigger input port, the external hard trigger signal is synchronously sent to part or all of the group package modules;
or the like, or a combination thereof,
and under the condition that an external hard trigger signal is acquired through any hard trigger input port, determining a group package module corresponding to the hard trigger input port, and sending the hard trigger signal to the group package module.
11. The method according to any one of claims 7-10, further comprising:
receiving a configuration instruction of an external Personal Computer (PC) through a CPU soft core, and configuring structural parameters of a specific network data packet according to the configuration instruction; the structure parameters comprise MAC addresses, IP addresses and specific data packet key values;
the assembling module assembles a specific network data packet under the condition that a hard trigger signal is received, and the assembling comprises the following steps:
and assembling the specific network data packet according to the structural parameter of the specific network data packet by the group packaging module under the condition of receiving the hard trigger signal.
12. The method of claim 11, further comprising:
configuring the type of a target hard trigger signal through the CPU soft core according to the configuration instruction;
the assembling a specific network data packet by the group assembling module under the condition of receiving the hard trigger signal comprises:
assembling, by the group packaging module, a particular network data packet if it is determined that the type of the received hard trigger signal matches the type of the target hard trigger signal.
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| CN202210641667.4A CN115174802B (en) | 2022-06-07 | 2022-06-07 | Image acquisition card and image acquisition method |
| PCT/CN2023/092204 WO2023236696A1 (en) | 2022-06-07 | 2023-05-05 | Image acquisition card and image acquisition method |
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| CN202210641667.4A CN115174802B (en) | 2022-06-07 | 2022-06-07 | Image acquisition card and image acquisition method |
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Cited By (1)
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| WO2023236696A1 (en) | 2023-12-14 |
| CN115174802B (en) | 2023-12-29 |
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