CN115145642A

CN115145642A - Software starting method and system

Info

Publication number: CN115145642A
Application number: CN202210669245.8A
Authority: CN
Inventors: 李辉; 谢实海
Original assignee: Advanced Institute of Information Technology AIIT of Peking University; Hangzhou Weiming Information Technology Co Ltd
Current assignee: Advanced Institute of Information Technology AIIT of Peking University; Hangzhou Weiming Information Technology Co Ltd
Priority date: 2022-06-14
Filing date: 2022-06-14
Publication date: 2022-10-04
Anticipated expiration: 2042-06-14
Also published as: CN115145642B

Abstract

The embodiment of the application discloses a software starting method and a system, wherein the method comprises the following steps: performing cross compiling on the target started software to obtain an algorithm program running on the logic gate array FPGA; loading an algorithm program running on the FPGA to a memory with a fixed address through a CPU; configuring a wake-up register on the FPGA so that the FPGA enters an operating state after the loading of the algorithm program is finished; configuring a program entry register on the FPGA so that the FPGA obtains an operation instruction according to the fixed address obtained in the memory; and configuring a calculation result register on the FPGA so as to send a result to a CPU after the FPGA finishes running. The debugging of the FPGA is more convenient, and the power consumption of the system can be reduced by configuring the running state of the FPGA.

Description

Software starting method and system

Technical Field

The embodiment of the application relates to the technical field of computers, in particular to a software starting method and system.

Background

In recent years, the performance of general-purpose processors such as CPUs has been increasing at a slow speed, and heterogeneous algorithms represented by FPGAs, GPUs, DSPs, NPUs, and the like have been increasingly used in order to continuously meet the increasing demands for energy-efficient computing in various industries. Under the heterogeneous scene, a general CPU is usually responsible for processing such as control and interaction of a user interface, deep learning online prediction is completed by hardware such as an FPGA (field programmable gate array), and the FPGA needs to load different algorithm programs online for debugging. Currently, loading FGPA programs online generally loads algorithm programs to be debugged onto the FPGA through hardware by connecting a JTAG emulator.

In the heterogeneous scene of the CPU and the FPGA, in the debugging stage of the system, an algorithm program to be run on the FPGA is generally loaded onto the FPGA through the JTAG emulator, which increases the cost for system debugging.

Disclosure of Invention

Therefore, the embodiment of the application provides a software starting method and system, so that the debugging of the FPGA is more convenient, and the power consumption of the system can be reduced by configuring the running state of the FPGA.

In order to achieve the above object, the embodiments of the present application provide the following technical solutions:

according to a first aspect of embodiments of the present application, there is provided a software boot method, including:

performing cross compiling on the target started software to obtain an algorithm program running on the logic gate array FPGA;

loading the algorithm program running on the FPGA to a memory with a fixed address through a CPU;

configuring a wake-up register on the FPGA so that the FPGA enters an operating state after the loading of the algorithm program is finished;

configuring a program entry register on the FPGA so that the FPGA obtains an operation instruction according to the fixed address obtained in the memory;

and configuring a calculation result register on the FPGA so as to send a result to a CPU after the FPGA finishes running.

Optionally, the method further comprises:

and the wake-up register is configured on the FPGA again so that the FPGA enters a sleep state again.

Optionally, the method further comprises:

performing cross compiling on target upgrading software to obtain an upgrading algorithm program running on the FPGA;

loading an upgrading algorithm program running on the FPGA to a memory with a fixed address through a CPU;

configuring a program entry register on the FPGA so that the FPGA obtains an upgrading instruction according to the fixed address obtained in the memory;

and configuring a calculation result register on the FPGA so as to send a result to a CPU after the FPGA is upgraded.

Optionally, the CPU loads the algorithm program running on the FPGA into a fixed-address memory, the method comprises the following steps:

and a driver is loaded on the CPU to verify a binary algorithm program running on the FPGA, and the binary algorithm program is loaded to a memory with a fixed address without errors.

According to a second aspect of embodiments of the present application, there is provided a software startup system, the system including:

the cross compiling module is used for cross compiling the target started software to obtain an algorithm program running on the logic gate array FPGA;

the loading module is used for loading the algorithm program operated on the FPGA to a memory with a fixed address through a CPU;

the first register configuration module is used for configuring a wakeup register on the FPGA so that the FPGA enters an operation state after the algorithm program is loaded;

the second register configuration module is used for configuring a program entry register on the FPGA so that the FPGA obtains an operation instruction according to the fixed address obtained in the memory;

and the third register configuration module is used for configuring a calculation result register on the FPGA so as to send a result to the CPU after the FPGA finishes running.

Optionally, the first register configuration module is further configured to:

Optionally, the system further comprises:

the cross compiling module is also used for cross compiling the target upgrading software to obtain an upgrading algorithm program running on the FPGA;

the loading module is also used for loading the upgrading algorithm program running on the FPGA to a memory with a fixed address through a CPU;

the second register configuration module is further configured to configure a program entry register on the FPGA, so that the FPGA obtains an upgrade instruction according to the fixed address obtained in the memory;

and the third register configuration module is also used for configuring a calculation result register on the FPGA so as to send a result to the CPU after the FPGA is upgraded.

Optionally, the loading module is specifically configured to:

According to a third aspect of embodiments of the present application, there is provided an electronic apparatus, including: a memory, a processor and a computer program stored on the memory and executable on the processor, the processor executing the computer program to implement the method of the first aspect.

According to a fourth aspect of embodiments herein, there is provided a computer readable storage medium having computer readable instructions stored thereon, the computer readable instructions being executable by a processor to implement the method of the first aspect.

In summary, the embodiments of the present application provide a software starting method and system, where an algorithm program running on a logic gate array FPGA is obtained by cross-compiling target-started software; loading the algorithm program running on the FPGA to a memory with a fixed address through a CPU; configuring a wake-up register on the FPGA so that the FPGA enters an operating state after the loading of the algorithm program is finished; configuring a program entry register on the FPGA so that the FPGA obtains an operation instruction according to the fixed address obtained in the memory; and configuring a calculation result register on the FPGA so as to send a result to a CPU after the FPGA finishes running. The debugging of the FPGA is more convenient, and the power consumption of the system can be reduced by configuring the running state of the FPGA.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.

The structures, ratios, sizes, and the like shown in the present specification are only used for matching with the contents disclosed in the specification, so that those skilled in the art can understand and read the present invention, and do not limit the conditions for implementing the present invention, so that the present invention has no technical significance, and any structural modifications, changes in the ratio relationship, or adjustments of the sizes, without affecting the functions and purposes of the present invention, should still fall within the scope of the present invention.

Fig. 1 is a schematic flowchart of a software boot method according to an embodiment of the present application;

fig. 2 is a block diagram of a software boot system according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

fig. 4 shows a schematic diagram of a computer-readable storage medium provided by an embodiment of the present application.

Detailed Description

The present invention is described in terms of particular embodiments, other advantages and features of the invention will become apparent to those skilled in the art from the following disclosure, and it is to be understood that the described embodiments are merely exemplary of the invention and that it is not intended to limit the invention to the particular embodiments disclosed. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Because the FPGA has the characteristics of programmability and high-performance computing, AI computing based on FPGA hardware is accelerated and is being widely applied to the field of computer vision processing. One of the most representative deployment ways is to use the FPGA and the CPU to form a heterogeneous computing system.

The embodiment of the application mainly provides a new method for replacing hardware to load an FPGA program in a CPU + FPGA scene, so that the debugging of the FPGA is more convenient, and the power consumption of a system can be reduced by configuring the running state of the FPGA. By using the method, the algorithm program of the FPGA can be upgraded under the condition of not interrupting the service.

Fig. 1 illustrates a software starting method provided in an embodiment of the present application, where the method includes:

step 101: performing cross compiling on the target started software to obtain an algorithm program running on a logic gate array FPGA;

step 102: loading an algorithm program running on the FPGA to a memory with a fixed address through a CPU;

step 103: configuring a wake-up register on the FPGA so that the FPGA enters an operating state after the loading of the algorithm program is finished;

step 104: configuring a program entry register on the FPGA so that the FPGA obtains an operation instruction according to the fixed address obtained in the memory;

step 105: and configuring a calculation result register on the FPGA so as to send a result to a CPU after the FPGA finishes running.

In one possible embodiment, the method further comprises: and the wake-up register is configured on the FPGA again so that the FPGA enters a sleep state again.

In one possible embodiment, the method further comprises: performing cross compiling on target upgrading software to obtain an upgrading algorithm program running on the FPGA; loading an upgrading algorithm program running on the FPGA to a memory with a fixed address through a CPU; configuring a program entry register on the FPGA so that the FPGA obtains an upgrading instruction according to the fixed address obtained in the memory; and configuring a calculation result register on the FPGA so as to send a result to a CPU after the FPGA is upgraded.

In a possible implementation manner, the loading, by the CPU, the algorithm program running on the FPGA into the memory with a fixed address includes: and a driver is loaded on the CPU to verify a binary algorithm program running on the FPGA, and the binary algorithm program is loaded to a memory with a fixed address without errors.

Under the heterogeneous scene of the CPU and the FPGA, a general CPU is usually responsible for processing such as control and interaction of a user interface, and the functions of deep learning online prediction, picture compression and decompression and the like which need a large amount of calculation are completed by hardware such as the FPGA. In the development and debugging stage of the heterogeneous architecture, the FPGA needs to load different algorithm programs on line for debugging.

To sum up, the embodiment of the present application provides a new method to replace hardware to load and start an FPGA program, and the specific flow is as follows:

in the first aspect, an algorithm program running on the FPGA is compiled through cross-compiling.

In the second aspect, a binary program file running on the FPGA is loaded to a memory with a fixed address by implementing a driver on the general-purpose CPU.

In the third aspect, an efficient control protocol is realized between the CPU and the FPGA: the CPU communicates with the FPGA through register operation. The concrete implementation is as follows:

the FPGA is configured as a peripheral of the CPU, so that the CPU can complete the control and interaction of the FPGA through a register on the FPGA. The following functional registers are defined:

(1) An FPGA wake-up register: after the FPGA is electrified, the FPGA is in a sleep state, so that the power consumption can be reduced;

(2) An FPGA program entry register: after the FPGA wakes up, the starting address of the program is obtained from the register, and the instruction is executed from the address.

(3) FPGA calculation result register: after the FPGA completes a large number of parallel computing functions, the result is returned to the CPU through the register.

The specific implementation process is as follows:

after the program is loaded, the CPU wakes up the FPGA by configuring an FPGA wake-up register so that the FPGA enters a normal running state. The CPU informs the FPGA of the initial address of the program in the memory by configuring an FPGA program entry register, and the FPGA takes out an instruction from the initial address to start running. Thus, the function of loading the FPGA program on line is completed. After the FPGA completes the calculation, the operation result is informed to the CPU by configuring an FPGA calculation result register, and the CPU completes the storage and post-processing of the calculation result. And finally, the CPU enables the FPGA to enter the sleep state again by configuring the FPGA wake-up register again, so that the power consumption of the system is reduced.

It should be noted that the functional registers configured in the method provided in the embodiment of the present application are not limited to the above-mentioned ones, and registers with corresponding functions are configured according to needs during specific implementation.

Under the condition of not interrupting the service, the algorithm program of the FPGA can be upgraded on line by the scheme, and the specific flow is as follows:

firstly, an algorithm program running on the FPGA is compiled through cross compiling. After the CPU loads the program into the memory, the CPU informs the FPGA of the initial address of the program in the memory by configuring an FPGA program entry register, and the FPGA takes out an instruction from the initial address and starts to operate. Therefore, the function of upgrading the FPGA program on line is completed. After the FPGA completes the calculation, the operation result is informed to the CPU by configuring an FPGA calculation result register, and the CPU completes the storage and post-processing of the calculation result.

Therefore, under the heterogeneous scene of the CPU + FPGA, the algorithm program on the FPGA is loaded and started through the CPU, and the FPGA is upgraded on line. The debugging of the FPGA is more convenient, and the power consumption of the system can be reduced by configuring the running state of the FPGA. And upgrading the algorithm program of the FPGA under the condition of not interrupting the service.

In summary, the embodiment of the present application provides a software starting method, which performs cross-compiling on target-started software to obtain an algorithm program running on a logic gate array FPGA; loading the algorithm program running on the FPGA to a memory with a fixed address through a CPU; configuring a wake-up register on the FPGA so that the FPGA enters a running state after the loading of the algorithm program is finished; configuring a program entry register on the FPGA so that the FPGA obtains an operation instruction according to the fixed address obtained in the memory; and configuring a calculation result register on the FPGA so as to send a result to a CPU after the FPGA finishes running. The debugging of the FPGA is more convenient, and the power consumption of the system can be reduced by configuring the running state of the FPGA.

Based on the same technical concept, an embodiment of the present application further provides a software starting system, as shown in fig. 2, the system includes:

the cross compiling module 201 is used for cross compiling the target started software to obtain an algorithm program running on the logic gate array FPGA;

a loading module 202, configured to load, by using a CPU, an algorithm program running on the FPGA to a memory with a fixed address;

the first register configuration module 203 is configured to configure a wake-up register on the FPGA, so that the FPGA enters a running state after the algorithm program is loaded;

a second register configuration module 204, configured to configure a program entry register on the FPGA, so that the FPGA obtains an operation instruction according to the fixed address obtained in the memory;

a third register configuration module 205, configured to configure a calculation result register on the FPGA, so that the result is sent to the CPU after the FPGA finishes operating.

In a possible implementation, the first register configuration module 203 is further configured to:

In one possible embodiment, the system further comprises:

the cross compiling module 201 is further configured to cross compile the target upgraded software to obtain an upgrade algorithm program running on the FPGA;

the loading module 202 is further configured to load the upgrade algorithm program running on the FPGA to a memory with a fixed address through the CPU;

the second register configuration module 204 is further configured to configure a program entry register on the FPGA, so that the FPGA obtains an upgrade instruction according to the fixed address obtained in the memory;

the third register configuration module 205 is further configured to configure a calculation result register on the FPGA, so that the result is sent to the CPU after the FPGA is upgraded.

In a possible implementation manner, the loading module 202 is specifically configured to:

The embodiment of the application also provides electronic equipment corresponding to the method provided by the embodiment. Please refer to fig. 3, which illustrates a schematic diagram of an electronic device according to some embodiments of the present application. The electronic device 20 may include: the system comprises a processor 200, a memory 201, a bus 202 and a communication interface 203, wherein the processor 200, the communication interface 203 and the memory 201 are connected through the bus 202; the memory 201 stores a computer program that can be executed on the processor 200, and the processor 200 executes the computer program to perform the method provided by any of the foregoing embodiments of the present application.

The Memory 201 may include a high-speed Random Access Memory (RAM) and may further include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. The communication connection between the network element of the system and at least one other network element is realized through at least one physical port 203 (which may be wired or wireless), and the internet, a wide area network, a local network, a metropolitan area network, and the like can be used.

Bus 202 can be an ISA bus, PCI bus, EISA bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. The memory 201 is used for storing a program, and the processor 200 executes the program after receiving an execution instruction, and the method disclosed by any of the foregoing embodiments of the present application may be applied to the processor 200, or implemented by the processor 200.

The processor 200 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 200. The Processor 200 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in the memory 201, and the processor 200 reads the information in the memory 201 and completes the steps of the method in combination with the hardware thereof.

The electronic equipment provided by the embodiment of the application and the method provided by the embodiment of the application are based on the same inventive concept, and have the same beneficial effects as the method adopted, operated or realized by the electronic equipment.

Referring to fig. 4, the computer-readable storage medium is an optical disc 30, on which a computer program (i.e., a program product) is stored, and when the computer program is executed by a processor, the computer program performs the method of any of the foregoing embodiments.

It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, a phase change memory (PRAM), a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), other types of Random Access Memories (RAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, or other optical and magnetic storage media, which are not described in detail herein.

The computer-readable storage medium provided by the above-mentioned embodiments of the present application and the method provided by the embodiments of the present application have the same advantages as the method adopted, executed or implemented by the application program stored in the computer-readable storage medium.

It should be noted that:

the algorithms and displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus. Various general purpose devices may be used with the teachings herein. The required structure for constructing such a device will be apparent from the description above. In addition, this application is not directed to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present application as described herein, and any descriptions of specific languages are provided above to disclose the best modes of the present application.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the application, various features of the application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the application and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.

Various component embodiments of the present application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the creation apparatus of a virtual machine according to embodiments of the present application. The present application may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present application may be stored on a computer readable medium or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.

It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means can be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

The above description is only for the preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for software boot, the method comprising:

performing cross compiling on the target started software to obtain an algorithm program running on a logic gate array FPGA;

2. The method of claim 1, wherein the method further comprises:

3. The method of claim 1, wherein the method further comprises:

4. The method of claim 1, wherein said loading, by a CPU, an algorithmic program running on said FPGA into a fixed address memory comprises:

and a driver is loaded on the CPU, a binary algorithm program running on the FPGA is verified, and the binary algorithm program is loaded to a memory with a fixed address without errors.

5. A software startup system, characterized in that the system comprises:

the second register configuration module is used for configuring a program entry register on the FPGA so that the FPGA obtains an operation instruction according to the fixed address obtained from the memory;

6. The system of claim 5, wherein the first register configuration module is further to:

7. The system of claim 5, wherein the system further comprises:

8. The system of claim 5, wherein the loading module is specifically configured to:

9. An electronic device, comprising: memory, processor and computer program stored on the memory and executable on the processor, characterized in that the processor executes when executing the computer program to implement the method according to any of claims 1-4.

10. A computer-readable storage medium having computer-readable instructions stored thereon, the computer-readable instructions being executable by a processor to implement the method of any one of claims 1-4.