CN112463244B

CN112463244B - CPU starting method and device, electronic equipment and computer readable storage medium

Info

Publication number: CN112463244B
Application number: CN202011186759.5A
Authority: CN
Inventors: 孙秀强; 黄家明; 班华堂; 乔英良; 李道童; 李勋堂; 艾山彬; 姚藩益
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2020-10-29
Filing date: 2020-10-29
Publication date: 2022-12-27
Anticipated expiration: 2040-10-29
Also published as: CN112463244A

Abstract

The invention provides a CPU starting method, a CPU starting device, electronic equipment and a computer readable storage medium, belongs to the technical field of computers, and solves the problem that hardware and firmware need to be researched and developed again due to upgrading of a CPU processor by an AMD manufacturer. The method comprises the following steps: compiling the Rome firmware image and the Naples firmware image, and combining the Rome firmware image and the Naples firmware image to form a BIOS image; judging the type of the CPU; when the CPU is a Rome processor, a Rome firmware image in the BIOS image is executed, and the CPU is started and guided; and when the CPU is a Naples processor, executing a Naples firmware image in the BIOS image and starting and booting the CPU. According to the invention, the state value of the EFS is read by the BootROM in the CPU when the mainboard is powered on to determine which part of the 16M mirror image of the 32M BIOS mirror image is loaded for loading, starting and guiding, so that one BIOS mirror image and one mainboard hardware can be compatible with a 2-generation CPU processor of an AMD manufacturer, and the development period and the labor cost are saved for a server manufacturer to research and develop new products.

Description

CPU starting method and device, electronic equipment and computer readable storage medium

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a method and an apparatus for starting a CPU, an electronic device, and a computer-readable storage medium.

Background

In the chip industry, each chip company can comprehensively consider various factors such as development of science and technology, updating of technology, market demand and the like, and a new chip product is timely released and updated, which accords with the development trend and the requirement of the science and technology, but for a product developer, the upgrading brings about the updating of research and development design, and causes heavy burden on the research and development labor cost of the company.

With the rapid development of the internet, more and more data centers are built, servers of the data centers are almost monopolized by the united states chip major intel, but with the rapid development of science and technology and the rapid increase of data streams, the server chips developed and designed previously cannot meet the performance requirements, and the new chip products will increase the research and development cost, so that the intel introduces a microcode concept, namely, the capability of a hardware design compatible with a 2-generation processor can be realized only through firmware upgrade. For example, an intel Purley platform is developed and designed in 2017, the chip is greatly required in a data center client, but a Cascade processor is developed and designed along with the improvement of performance requirements, the performance is greatly improved compared with the Purley processor, and pins among CPUs are compatible, so that the problem can be solved only by reserving a hardware design independent firmware upgrading microcode, namely, one firmware can support 2 processors, and the client requirements can be met without additional design of manufacturers. The solution is simply to upgrade the microcode associated with the CPU. However, AMD manufacturers have also designed multiple processors, the performance of Naples is extremely high when they just release, but AMD has released a Rome chip with the development of technology, AMD has considered compatibility when developing and upgrading the chip, although hardware meets stitch compatibility, because software is greatly different from intel design and does not support upgrading microcode as intel, i.e. 2 generation processors can be met, server developers need to consider how to implement a BIOS mirror compatible 2-processor, and therefore the invention discloses a CPU starting method, device, electronic device and computer readable storage medium which can solve the above problems well.

Disclosure of Invention

The invention aims to provide a CPU starting method, a device, electronic equipment and a computer readable storage medium, in order to solve the problem that hardware and firmware are required to be re-researched and developed due to upgrading of a CPU processor by AMD manufacturers, the invention reads the state value of EFS through BootROM in the CPU when a mainboard is powered on to determine which part of 16M image of a 32M BIOS image is loaded for loading starting guidance, and by the mode, the requirement that one BIOS image and one mainboard hardware can be compatible with the 2-generation CPU processor of the AMD manufacturers can be met, the development period and labor cost are saved for a server manufacturer to research and develop new products, and the new products can be quickly marketed and deployed in batches in a very short time.

In a first aspect, the present invention provides a CPU starting method, including:

compiling the Rome firmware image and the Naples firmware image, and combining the Rome firmware image and the Naples firmware image to form a BIOS image;

judging the type of the CPU;

when the CPU is a Rome processor, executing a Rome firmware image in the BIOS image and starting and guiding the CPU;

and when the CPU is a Naples processor, executing a Naples firmware image in the BIOS image and starting and booting the CPU.

Further, the BIOS mirror image is stored in the SPI Flash.

Further, the size of the Rome firmware image and the size of the Naples firmware image are both 16M.

Further, the step of determining the type of the CPU includes:

reading the EFS status bit of the CPU register;

and judging the type of the CPU according to the value of the EFS state bit.

Further, the step of reading the EFS status bit of the CPU register includes:

and reading the EFS status bit of the CPU register through BootROM mirror image of the CPU.

Further, the method also comprises the following steps:

and updating the BIOS mirror image.

In a second aspect, the present invention further provides a CPU starting apparatus, including:

the compiling module is used for compiling the Rome firmware image and the Naples firmware image and combining the Rome firmware image and the Naples firmware image to form a BIOS image;

the judging module is used for judging the type of the CPU;

the starting module is used for executing the Rome firmware image in the BIOS image and starting and guiding the CPU when the CPU is a Rome processor; and when the CPU is a Naples processor, executing the Naples firmware image in the BIOS image and starting and booting the CPU.

In a third aspect, the present invention further provides an electronic device, which includes a memory and a processor, where the memory stores therein a computer program operable on the processor, and the processor implements the steps of the CPU starting method when executing the computer program.

In a fourth aspect, the present invention also provides a computer readable storage medium having stored thereon machine executable instructions which, when invoked and executed by a processor, cause the processor to execute a CPU boot method.

The invention provides a CPU starting method, a device, an electronic device and a computer readable storage medium, a BIOS mirror image of a Rome processor 16M and a BIOS mirror image of a Naples processor 16M are synthesized into a 32M BIOS mirror image in a BIOS compiling process, a TOP16M space of an SPI Flash is the Rome processor BIOS mirror image, a Bottom16M space of the SPI Flash is the Naples processor BIOS mirror image, when a mainboard is started, an EFS state value of the CPU is read by a CPU internal Bootrom, which type of a processor on the mainboard is judged according to the read EFS state value, then loading and executing the BIOS image file of the corresponding processor to realize the purpose that one BIOS image file can support two types of CPUs of AMD manufacturers, meanwhile, by adopting the scheme, the independent updating function can be carried out on the BIOS images of the Rome processor and the Naples processor, because the BIOS images belong to different address spaces of the SPI Flash respectively, the CPU type supported currently can be checked through a system or other modes, the unused BIOS image is independently updated, because the traditional updating mode is the updating of the whole BIOS image file, the invention can independently update the BIOS images supporting different types of CPUs, thereby being more beneficial to the operation and the stability of the system, reducing the problem that hardware and firmware are required to be re-developed and designed because AMD manufacturers upgrade CPU processors, the state value of EFS is read by BootROM in CPU when the mainboard is powered on to decide which part of 16M image of BIOS image of 32M is loaded for loading and starting up the boot, by the mode, the requirement that one BIOS mirror image and one mainboard hardware can be compatible with the 2-generation CPU processor of the AMD manufacturer can be met, the development period and the labor cost are saved for new product development of server manufacturers, and the new products can be quickly listed and deployed in batches in a very short time.

Accordingly, the electronic device and the computer-readable storage medium provided by the embodiments of the present invention also have the above technical effects.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a flowchart of a CPU startup method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating BIOS mirror image components according to an embodiment of the present invention;

FIG. 3 is a flowchart of boot-up provided by an embodiment of the present invention;

fig. 4 is a schematic diagram of an electronic device according to an embodiment of the present invention.

In the figure: 800 electronic device, 801 memory, 802 processor, 803 bus, 804 communication interface.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "comprising" and "having," and any variations thereof, as used in connection with the present embodiments, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Referring to fig. 1-4, a method for starting a CPU according to an embodiment of the present invention includes:

judging the type of the CPU;

when the CPU is a Rome processor, the Rome firmware image in the BIOS image is executed, and the CPU is started and guided;

and when the CPU is a Naples processor, executing the Naples firmware image in the BIOS image and starting and booting the CPU.

A BIOS mirror image of a Rome processor 16M and a BIOS mirror image of a Naples processor 16M are synthesized into a 32M BIOS mirror image in a BIOS compiling process, a TOP16M space of an SPI Flash is the Rome processor BIOS mirror image, a Bottom16M space of the SPI Flash is the Naples processor BIOS mirror image, when a mainboard is started, a Bootrom in the CPU reads an EFS state value of the CPU first, judges which type of a processor on the mainboard is according to the read EFS state value, and loads and executes a BIOS mirror image file of a corresponding processor, so that the purpose that the BIOS mirror image file can support two types of CPUs of AMD manufacturers is achieved, and meanwhile, the scheme can carry out an independent updating function aiming at the BIOS mirror image and the Naples processor mirror image which support the Rome processor BIOS mirror image and can check the type of the CPU which is currently supported by a system or other modes because the BIOS mirror images respectively belong to different address spaces of the SPI, the method is characterized in that the unused BIOS mirror image is independently updated, the traditional updating mode is the updating of the whole BIOS mirror image file, the method can be used for independently updating the BIOS mirror images supporting different types of CPUs, so that the operation, the maintenance and the stability of the system are better facilitated, in order to solve the problem that hardware and firmware are required to be newly researched and developed due to the fact that AMD manufacturers upgrade CPU processors, the state value of EFS is read by BootROM in the CPU when a mainboard is powered on to determine which part of the 32M BIOS mirror image is loaded to carry out loading starting and guiding, the method can meet the requirement that one BIOS mirror image and one mainboard hardware can be compatible with the 2-generation CPU processor of the AMD manufacturers, the development period and the labor cost are saved for new product research and development of server manufacturers, and the new products can be quickly marketed and deployed in batches in extremely short time.

In the embodiment of the invention, the BIOS mirror image is stored in the SPI Flash.

In the embodiment of the invention, the size of the Rome firmware image and the size of the Naples firmware image are both 16M.

In the embodiment of the present invention, the step of determining the type of the CPU includes:

reading the EFS status bit of the CPU register;

and judging the type of the CPU according to the value of the EFS state bit.

In the embodiment of the present invention, the step of reading the EFS status bit of the CPU register includes:

reading the EFS status bit of the CPU register through BootROM mirror image of the CPU.

In the embodiment of the present invention, the method further includes:

and updating the BIOS mirror image.

An embodiment of the present invention further provides a CPU starting apparatus, including:

the judging module is used for judging the type of the CPU;

the starting module is used for executing the Rome firmware image in the BIOS image and starting and guiding the CPU when the CPU is a Rome processor; and when the CPU is a Naples processor, executing a Naples firmware image in the BIOS image and starting and booting the CPU.

The embodiment of the invention also provides electronic equipment, which comprises a memory and a processor, wherein the memory is stored with a computer program capable of running on the processor, and the step of starting the CPU is realized when the processor executes the computer program.

The embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium stores machine executable instructions, and when the computer executable instructions are called and run by a processor, the computer executable instructions cause the processor to run the CPU starting method.

The embodiment of the invention realizes that a BIOS mirror image is a 32M File, the front 16M mirror image content is a firmware mirror image of a Rome processor, the back 16M mirror image content is a firmware mirror image of a Naples processor, the 32M BIOS ROM mirror image is burnt and written into a 32M SPI Flash chip, when the BIOS mirror image is started, the EFS (encryption File System) bit of a CPU register is read to judge whether the current processor is Rome or Naples, if the EFS bit is read to be 1, the current processor is confirmed to be a Rome processor, at the moment, the BIOS mirror image supports the front 16M mirror image File of the 32M mirror image according to the judgment result of the EFS, the Rome processor is booted, if the EFS read value judgment result is 0, the current processor is confirmed to be a Naples processor, the back 16M mirror image content of the 32M mirror image is booted to boot the Naples processor, and the EFS state bit of the CPU is read to realize that the 32M mirror image File supports booting of different boot processors of 2.

The CPU starting method of the invention is realized by the following steps:

1) When the BIOS codes are compiled, the BIOS mirror image 16M of the Naples processor and the BIOS mirror image 16M of the Rome processor are combined into a 32M BIOS mirror image, the first 16M is the BIOS mirror image of the Naples processor, and the second 16M is the BIOS mirror image of the Rome processor.

2) The BIOS image components are shown in figure 2.

3) When the server mainboard is started, the BootROM mirror image in the CPU reads the EFS bit of the register of the CPU to judge the read numerical value, if the read numerical value is 1, the 16M BIOS mirror image is confirmed to carry out system configuration and boot starting after the Naples processor is executed, and if the read numerical value is 0, the 16M BIOS mirror image is confirmed to carry out system configuration and boot starting before the Rome processor is executed.

4) The boot is initiated as shown in figure 3.

The system has strong reproducibility and expansibility, each internet company and the data center are gradually updating, purchasing and deploying the AMD server along with the upgrading of an AMD architecture in recent years, AMD manufacturers update and iterate CPU processors along with the improvement of the performance requirements of clients, and old processors and new processors need to realize soft-hard compatibility.

As shown in fig. 4, an electronic device 800 according to an embodiment of the present invention includes a memory 801 and a processor 802, where the memory stores a computer program that is executable on the processor, and the processor executes the computer program to implement the steps of the method according to the above embodiment.

As shown in fig. 4, the electronic device further includes: a bus 803 and a communication interface 804, the processor 802, the communication interface 804 and the memory 801 being connected by the bus 803; the processor 802 is used to execute executable modules, such as computer programs, stored in the memory 801.

The Memory 801 may include a Random Access Memory (RAM), and may further include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. The communication connection between the network element of the system and at least one other network element is realized through at least one communication interface 804 (which may be wired or wireless), and the internet, a wide area network, a local network, a metropolitan area network, and the like may be used.

The bus 803 may be an ISA bus, PCI bus, EISA bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one double-headed arrow is shown in FIG. 4, but that does not indicate only one bus or one type of bus.

The memory 801 is used for storing a program, the processor 802 executes the program after receiving an execution instruction, and the method performed by the apparatus defined by the process disclosed in any of the foregoing embodiments of the present invention may be applied to the processor 802, or implemented by the processor 802.

The processor 802 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 802. The Processor 802 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the device can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in the memory 801, and the processor 802 reads the information in the memory 801 and completes the steps of the method in combination with the hardware thereof.

Corresponding to the method, the embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium stores machine executable instructions, and when the computer executable instructions are called and executed by a processor, the computer executable instructions cause the processor to execute the steps of the method.

The apparatus provided by the embodiment of the present invention may be specific hardware on the device, or software or firmware installed on the device, etc. The device provided by the embodiment of the present invention has the same implementation principle and technical effect as the method embodiments, and for the sake of brief description, reference may be made to the corresponding contents in the method embodiments without reference to the device embodiments. It can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working processes of the system, the apparatus and the unit described above may all refer to the corresponding processes in the method embodiments, and are not described herein again.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

For another example, a division of elements into only one logical division may be implemented in a different manner, and multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments provided by the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a portable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other media capable of storing program codes.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus once an item is defined in one figure, it need not be further defined and explained in subsequent figures, and moreover, the terms "first", "second", "third", etc. are used merely to distinguish one description from another and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should also be noted that, unless otherwise explicitly stated or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; and the modifications, changes or substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention. Are intended to be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A CPU startup method, comprising:

compiling the Rome firmware image and the Naples firmware image, and combining the Rome firmware image and the Naples firmware image to form a BIOS image; the sizes of the Rome firmware image and the Naples firmware image are both 16M;

reading an EFS state bit of a CPU register through a BootROM mirror image of the CPU; judging the type of the CPU according to the value of the EFS state bit;

2. The CPU startup method according to claim 1, wherein the BIOS image is stored in SPI Flash.

3. The CPU startup method of claim 1, further comprising:

and updating the BIOS mirror image.

4. A CPU startup device, comprising:

the judging module is used for judging the type of the CPU;

5. An electronic device comprising a memory and a processor, wherein the memory stores a computer program operable on the processor, and wherein the processor implements the steps of the method of any of claims 1 to 3 when executing the computer program.

6. A computer readable storage medium having stored thereon machine executable instructions which, when invoked and executed by a processor, cause the processor to execute the method of any of claims 1 to 3.