CN114968683A

CN114968683A - Bus relation detection device, slave device, system and chip

Info

Publication number: CN114968683A
Application number: CN202210523758.8A
Authority: CN
Inventors: 李�杰; 蒋知广; 朱高林
Original assignee: Shanghai Awinic Technology Co Ltd
Current assignee: Shanghai Awinic Technology Co Ltd
Priority date: 2022-05-13
Filing date: 2022-05-13
Publication date: 2022-08-30

Abstract

A bus relation detection device, slave equipment, a system and a chip comprises a pre-detection circuit, a first frequency conversion circuit and a second frequency conversion circuit, wherein the pre-detection circuit is used for acquiring two input signals through a first input port and a second input port, the two input signals are respectively a bus clock signal and a bus data signal, and only the input signal meeting the requirement of preset frequency is output as an intermediate clock signal; and the detection circuit is connected with the pre-detection circuit and used for carrying out address matching according to the two input signals and the intermediate clock signal so as to determine the bus relationship and outputting the matched bus data signal and the matched bus clock signal. The bus relation detection device, the slave device, the system and the chip prevent the condition of abnormal detection judgment, the judgment result of the connection relation of the bus is accurate and reliable, and the accuracy of host machine distinguishing is improved when equipment distinguishing is carried out.

Description

Bus relation detection device, slave device, system and chip

Technical Field

The application relates to the technical field of electronics, in particular to a bus relation detection device, slave equipment, a system and a chip.

Background

With the development of communication technology, the demand for radio frequency front-end devices (such as power amplifiers, low noise amplifiers, antenna tuners, filters, switches, etc.) is increasing. Device manufacturers in the radio frequency field face challenges in sophisticated control of many devices. In this regard, the MIPI (Mobile Industry Processor Interface) alliance proposes an RFFE (RF Front End) bus Interface for connecting one or more RFICs (RF Integrated circuits) in a Mobile terminal to its associated FEM (Front End module) for control and monitoring thereof.

Each Slave device mounted on the RFFE bus is identified by the host through its own Unique signal, such as Unique Slave ID (Slave ID), PID (Product ID), and MID (MANUFACTURER ID). In one communication, the USID is included in the command frame and is used for identifying whether the slave is a device for the host to correctly communicate, and the slave can continue to receive other command frames, address frames or data frames from the host only after the USID is successfully matched.

However, at present, the application scenarios of multi-chip synchronization are more and more, and the application scenarios of a plurality of chips of the same type mounted on the same radio frequency front end system are more and more, and if two devices with the same USID, PID, and MID are needed in one radio frequency front end system, the accuracy of distinguishing between RFFE hosts is low.

Disclosure of Invention

In view of this, the present application provides a bus relationship detecting apparatus, a slave device, a system and a chip to solve the problem that in the existing rf front-end system, if two devices with the same USID, PID and MID are used, the accuracy of differentiation performed by the host is low.

The application provides a bus relation detection device, includes: the pre-detection circuit is used for acquiring two input signals through the first input port and the second input port, wherein the two input signals are a bus clock signal and a bus data signal respectively, and only the input signal meeting the requirement of preset frequency is output as an intermediate clock signal; and the detection circuit is connected with the pre-detection circuit and used for carrying out address matching according to the two input signals and the intermediate clock signal so as to determine the bus relation and outputting the matched bus data signal and the matched bus clock signal.

Optionally, the pre-detection circuit includes a pre-detection unit and a gate control logic unit; the pre-detection unit is used for acquiring the input signal through a first input port and a second input port, determining whether the preset frequency requirement is met according to at least one of the level change times, the rising edge number or the falling edge number of the input signal, and outputting a corresponding clock control signal when the preset frequency requirement is met; and the gating logic unit is connected with the pre-detection unit and used for selecting a corresponding input signal as the intermediate clock signal to be output according to the clock control signal and simultaneously closing the other input signal as the intermediate clock signal to be output.

The interference caused by signal glitch can be prevented by determining the signal frequency relation through the level change times. The number of rising edges or the number of falling edges is judged through the register so as to determine that the signal frequency circuit is convenient to design.

Optionally, the pre-detection circuit further includes a sequence detection unit; the sequence detection unit is used for acquiring the input signal through a first input port and a second input port and outputting a reset signal after detecting a flag bit in the input signal; the pre-detection unit is connected with the sequence detection unit and used for resetting according to the reset signal and determining whether the preset frequency requirement is met according to at least one of the level change times, the rising edge number or the falling edge number of the input signal after resetting.

Through the sequence detection unit, after the zone bit in the input signal is detected, a reset signal is output to control the pre-detection unit to reset, the reset mode comprises synchronous reset and asynchronous reset, preferably asynchronous reset, whether the two input signals meet the preset frequency requirement can be judged after the two input signals are determined to be valid bus data signals SDA, the influence of invalid signals is further eliminated, and the accuracy of the frequency judgment result is improved.

Optionally, the pre-detection unit includes a first pre-detection subunit and a second pre-detection subunit having the same circuit structure; one of the two input signals is used as a first input signal, and the other input signal is used as a second input signal; the first pre-detection subunit is connected with the sequence detection unit and is used for performing asynchronous reset according to the reset signal, determining whether the preset frequency requirement is met according to at least one of the level change times, the falling edge number or the rising edge number of the first input signal, and outputting a first clock control signal when the preset frequency requirement is met; the second pre-detection subunit is connected with the sequence detection unit and is used for performing asynchronous reset according to the reset signal, determining whether the preset frequency requirement is met according to at least one of the level change times, the falling edge number or the rising edge number of the second input signal, and outputting a second clock control signal when the preset frequency requirement is met; and the gating logic unit is connected with the first pre-detection unit and the second pre-detection unit and is used for selecting a corresponding input signal to be output as the intermediate clock signal according to the first clock control signal and the second clock control signal and simultaneously closing the other input signal to be output as the intermediate clock signal.

The first pre-detection subunit and the second pre-detection subunit which have the same circuit structure can realize the same judgment on the two input signals so as to determine the bus clock signal SCL therein, thereby improving the detection consistency and facilitating the circuit design.

Optionally, the first pre-detection subunit includes at least two registers and a first and gate device, where an input end of the first register is connected to a high level, a clock end is connected to the first input signal, a reset end is connected to the reset signal, an output end is connected to a first input end of the first and gate device, and a second input end of the first and gate device is inverted and then connected to the second clock control signal; the output end of the first AND gate device is connected with the input end of a second register, the clock end of the second register is connected with the first input signal, the reset end is connected with the reset signal, and the output end is used for outputting the first clock control signal; the second pre-detection subunit comprises at least two registers and a second AND gate device, wherein the input end of a third register is connected with a high level, a clock end is connected with the second input signal, a reset end is connected with the reset signal, the output end is connected with the first input end of the second AND gate device, and the second input end of the second AND gate device is connected with the first clock control signal after being inverted; the output end of the second AND gate device is connected with the input end of a fourth register, the clock end of the fourth register is connected with the second input signal, the reset end is connected with the reset signal, and the output end is used for outputting the second clock control signal.

Optionally, the flag bit is a sequence start condition flag bit; the sequence detection unit comprises a first sequence detection subunit, a second sequence detection subunit and a first OR gate device; the first sequence detection subunit is configured to output a first intermediate reset signal to the first input end of the first or gate device after detecting the sequence start condition flag bit in the second input signal; the second sequence detection subunit is configured to output a second intermediate reset signal to the second input end of the first or-gate device after detecting the sequence start condition flag bit in the first input signal; the first or gate device is configured to output the reset signal according to the first intermediate reset signal and the second intermediate reset signal.

Optionally, the gate control logic unit includes a third and gate device and a fourth and gate device; the first input end of the third AND gate device is connected with the output end of the second register after being inverted, and the second input end of the third AND gate device is connected with the second input signal; the third AND gate device is used for controlling the second input signal to be output as a second intermediate clock signal according to the first clock control signal; the first input end of the fourth AND gate device is connected with the output end of the fourth register after being inverted, and the second input end of the fourth AND gate device is connected with the first input signal; and the fourth AND gate device is used for controlling the first input signal to be output as a first intermediate clock signal according to the second clock control signal.

Optionally, the detection circuit includes a first detection unit and a second detection unit; a first input end of the first detection unit is used for acquiring the first input signal, a second input end of the first detection unit is used for acquiring the first intermediate clock signal, a reset end of the first detection unit is used for acquiring the reset signal, and the first detection unit is used for performing address matching according to the first input signal and the first intermediate clock signal and outputting a first address matching signal; the first input end of the second detection unit is used for acquiring the second input signal, the second input end of the second detection unit is used for acquiring the second intermediate clock signal, the reset end of the second detection unit is used for acquiring the reset signal, and the second detection unit is used for performing address matching according to the second input signal and the second intermediate clock signal and outputting a second address matching signal.

The first detection unit and the second detection unit support asynchronous reset of signals, so that the detection result of the detection circuit is not dead-locked, and the bus relation of the input port of the slave machine needs to be detected again when the host machine sends a new instruction, so that real-time detection can be realized, and the detection accuracy is improved.

Optionally, the detection unit further includes a signal selection unit; the signal selection unit is connected with the first detection unit and the second detection unit and is used for selecting and outputting a matched bus clock signal and a matched bus data signal according to the first address matching signal and the second address matching signal.

Optionally, the reset signal includes a first reset signal and a second reset signal, the first reset signal is used to control the first pre-detection subunit to reset, and the second reset signal is used to control the second pre-detection subunit to reset; the sequence detection unit further comprises a second or gate device and a third or gate device; a first input end of the second or gate device is used for acquiring the first address matching signal, a second input end of the second or gate device is connected with an output end of the first or gate device, and an output end of the second or gate device is used for outputting the first reset signal; the first input end of the third or-gate device is used for obtaining the second address matching signal, the second input end of the third or-gate device is connected with the output end of the first or-gate device, and the output end of the third or-gate device is used for outputting the second reset signal.

Optionally, the detection circuit includes a counter; the counter is used for counting according to the two input signals and the intermediate clock signal, performing address matching when the counting value is a preset value to determine the bus relation, and outputting the matched signals as a bus data signal and a bus clock signal.

The present application also provides a slave device, comprising: the bus relation detection device and the data processing unit; the bus relation detection device is used for selecting a matched bus data signal and a matched bus clock signal according to the frequency relation of the input signals and sending the bus data signal and the matched bus clock signal to the data processing unit; and the data processing unit is connected with the bus relation detection device and is used for processing the received bus data signal and the received bus clock signal.

Optionally, the data processing unit includes a data frame processing unit, a state machine, and a register module; the data frame processing unit and the state machine are connected with the bus relation detection device and are used for receiving the command in the bus data signal and processing the command; and the first input end of the register is connected with the data frame processing unit and the output end of the state machine, and the second input end of the register is connected with the detection circuit, and the register is used for receiving a slave device address in the bus data signal and processing the slave device address.

The present application further provides a communication system, comprising: the master device and at least two slave devices; the first slave device and the second slave device are two devices of the same kind manufactured by the same manufacturer; the clock end of the master device is connected to the first input port of the first slave device and the second input port of the second slave device, respectively, and the data end of the master device is connected to the second input port of the first slave device and the first input port of the second slave device, respectively.

The application also provides a radio frequency chip which comprises a circuit interface formed by the bus relation detection device.

The bus relation detection device, the slave device, the system and the chip are characterized in that the pre-detection circuit is used for acquiring two input signals through a first input port and a second input port, wherein the two input signals are a bus clock signal and a bus data signal respectively, and only the input signal meeting the requirement of preset frequency is output as an intermediate clock signal; the detection circuit is connected with the pre-detection circuit and used for carrying out address matching according to the two input signals and the intermediate clock signal so as to determine the bus relationship and outputting the matched bus data signal and the bus clock signal, so that the condition of abnormal detection judgment is prevented, the judgment result of the bus connection relationship is accurate and reliable, and the host distinguishing accuracy is improved when equipment is distinguished.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1a is a schematic diagram of an interface of an MIPI RFFE device defined by the RFFE standard;

FIG. 1b is a schematic diagram of a MIPI RFFE command sequence;

FIG. 2 is a schematic structural diagram of a bus relationship detection apparatus according to an embodiment;

FIG. 3 is a schematic structural diagram of a bus relationship detection apparatus according to an embodiment;

FIG. 4 is a schematic structural diagram of a bus relationship detection apparatus according to an embodiment;

FIG. 5 is a timing diagram of the SCL bus connected to the first input port and the SDA bus connected to the second input port;

FIG. 6 is a timing diagram of when the SDA bus is connected to the first input port and the SCL bus is connected to the second input port;

FIG. 7 is a schematic diagram of a slave device according to an embodiment;

fig. 8 is a communication system of an embodiment.

Detailed Description

In the process of implementing the present invention, the MIPI RFFE standard of the present invention defines an interface between RFFE devices, as shown in fig. 1 a. A maximum of 1 master device and 15 slave devices can be mounted on a single RFFE bus (only slave device 1 and slave device 2 are shown in fig. 1 a). The bus is composed of clock signal lines SCLK and SDATA, wherein SCLK is controlled by the host computer, SDATA is a bidirectional data line, and the host computer and the slave computer can be controlled. The slave devices mounted on the RFFE bus can be identified by the host through signals such as unique USID, product ID and manufacturer ID of the slave devices.

As shown in fig. 1b, the MIPI RFFE command sequence mainly consists of the following three parts, in order:

1. transmission of sequence start conditions

2. Transmission of frames (containing a command frame, 0,1 or more address/data frames, depending on the type of command frame)

3. Bus release (Bus Park Cycle)

Taking a register write (register write) instruction as an example, a typical MIPI communication includes the following flow, as shown in fig. 1 b:

(1) the host sends a Start signal "SSC (Sequence Start Condition), when no clock signal is transmitted on SCLK. Starting a communication after the SSC signal;

(2) the host then sends a Command Frame (Register Write Command Frame). The command frame consists of 4 bits of slave device address USID, SA3, SA2, SA1 and SA0, 3 bits of register write identifier, i.e. 010, 5 bits of register address, i.e. a4, A3, a2, a1 and a0, 1 bit of parity bit P. The command frame compositions of different read-write command sequences are different;

(3) the host then generates a Data Frame (Data Frame). The data frame is composed of 8-bit data D7, D6, D5, D4, D3, D2, D1, D0 and 1-bit parity bit P;

(4) the host sends a Bus release (Bus Park)0 to finish the communication and release the Bus.

In one communication, the USID is included in the command frame and is used for identifying whether the slave is a device for the host to correctly communicate, and the slave can continue to receive other command frames, address frames or data frames from the host only after the USID is successfully matched.

In order to solve the problem that when a plurality of slave devices with the same USID/PID/MID are used in a radio frequency front-end system, the RFFE host has lower distinguishing accuracy in distinguishing, the prior art provides a solution.

Prior art 1: when two MIPI RFFE slave devices (slave device 1 and slave device 2) are completely the same, connecting SCLK of the slave device 1 to SCLK and SDATA of the master device to SDATA of the master device; SCLK of the slave device 2 is connected to SDATA of the master device, and SDATA is connected to SCLK of the master device. Each slave device detects SSC signals in received signals to determine the connection relation of the current bus, and the USIDs corresponding to different bus connection modes are different, so that two completely same MIPI RFFE slave devices are distinguished in the MIPI RFFE system.

Prior art 2: the data characteristics of the first 13bit command frame of the main device sending instruction are detected by two sets of signal detection circuits (signal detection circuit 1 and signal detection circuit 2) which are symmetrical in structure and are connected in a bus cross mode, and then the connection mode of the current bus is judged, so that two completely same MIPI RFFE slave devices are distinguished in an MIPI RFFE system.

The inventor finds that the prior art has the following disadvantages:

disadvantages of prior art 1: the technology judges the connection relationship between the current SCL and the SDA bus through SSC detection, and if a glitch occurs on the bus before one-time communication judgment, the error detection of an SSC signal is possibly caused, so that the abnormal judgment of the current bus relationship is caused. Therefore, this technique does not sufficiently consider the abnormal situation, and the accuracy of detection judgment is poor.

Disadvantages of prior art 2: the technology is to detect the data characteristics (whether a command sequence is a sequence specified by a protocol or not and whether a parity bit is correct or not) of a first 13-bit command frame of a command sent by a main device through two sets of signal detection circuits (a signal detection circuit 1 and a signal detection circuit 2) which are symmetrical in structure and are connected with each other in a bus cross mode. If data transmitted by a host is abnormal or data distortion is caused in the transmission process of the data, the command frame of the command can not meet the data characteristics, the work of the bus relation abnormality detection system can not be shielded in time, and the abnormality judgment of the bus relation can be caused after sufficient pulses are provided. Therefore, this technique does not sufficiently consider the abnormal situation, and the accuracy of detection judgment is poor.

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.

Please refer to fig. 2, a schematic structural diagram of a bus relationship detecting apparatus according to an embodiment of the present application.

The bus relation detection device of the application comprises: a pre-detection circuit 1 and a detection circuit 2.

The pre-detection circuit 1 is configured to obtain two input signals data _ in1 and data _ in2 through a first input port and a second input port, where the two input signals are a bus clock signal and a bus data signal, respectively, and output only the input signal data _ in1 or the input signal data _ in2 meeting a preset frequency requirement as an intermediate clock signal gata _ clk1 or gata _ clk 2.

And the detection circuit 2 is connected with the pre-detection circuit 1 and is used for performing address matching according to the input signal data _ in1, the input signal data _ in2 and the intermediate clock signal gata _ clk1 or gata _ clk2 to determine a bus relationship, and outputting the matched bus data signal data _ in _ ctrl and bus clock signal clk _ ctrl.

The bus relationship detection device of the embodiment comprises a pre-detection circuit 1, a pre-detection circuit and a pre-detection circuit, wherein the pre-detection circuit is used for acquiring two input signals data _ in1 and data _ in2 through a first input port and a second input port, the two input signals are respectively a bus clock signal and a bus data signal, and only the input signal data _ in1 or the input signal data _ in2 meeting the preset frequency requirement is output as an intermediate clock signal gata _ clk1 or gata _ clk 2; the detection circuit 2 is connected with the pre-detection circuit 1 and is used for performing address matching according to the input signal data _ in1, the input signal data _ in2 and the intermediate clock signal gata _ clk1 or gata _ clk2 to determine a bus relationship, and outputting the matched bus data signal data _ in _ ctrl and the matched bus clock signal clk _ ctrl, so that the condition of abnormality detection judgment is prevented, the judgment result of the bus connection relationship is accurate and reliable, and the host distinguishing accuracy is improved when equipment distinguishing is performed.

In an alternative embodiment, one of gata _ clk1 and gata _ clk2 is used as an intermediate clock signal, and is held in line with the bus clock signal in the input signal, while the other is held at a constant level.

A bus relation detecting apparatus of the present embodiment is composed of a pre-detection circuit 1 and a detection circuit 2. The working process of the bus relation detection device is as follows: when an MIPI host sends a complete instruction to a slave machine, (1) a pre-detection circuit 1 of a bus relation detection device pre-judges the bus relation by detecting the signal frequency relation of two input ports (a first input port and a second input port), outputs a signal meeting the preset frequency requirement to a detection circuit in an intermediate clock signal form, and closes the signal not meeting the preset frequency requirement; (2) the detection circuit 2 determines the final bus relationship by judging the address id (identification number) matching condition of the intermediate clock signal output from the output end of the pre-detection circuit 1 and the two input signals, and selects and outputs the data end and the clock end with the correct relationship for the subsequent data processing unit to use.

In the bus relationship detection apparatus of this embodiment, the pre-detection circuit 1 pre-determines the bus relationship according to the frequency relationship between two input signals, and determines which of the two input signals is the bus clock signal SCL and which is the bus data signal SDA, because the frequency of the bus clock signal SCL is several times, such as 2 times, 3 times or other times, of the frequency of the bus data signal SDA, by determining whether the two input signals meet the preset frequency requirement, it can be determined which of the two input signals is the bus clock signal SCL and which is the bus data signal SDA, and only the bus clock signal SCL meeting the preset frequency requirement is output to the detection circuit, and because the level of the bus data signal SDA does not change, the clock transmission pre-determined as the bus data signal SDA is turned off, thereby controlling the pulse number of the corresponding detection unit in the detection circuit 2 that uses the bus data signal SDA as the clock The corresponding detection unit in the detection circuit 2 cannot continue the detection operation. The design has the advantages that even if the instruction sent by the current host cannot meet the detection condition of the detection unit taking the bus clock signal SCL as the clock, the number of clock pulses of the bus data signal SDA is controlled by the pre-detection unit, so that the detection unit taking the bus data signal SDA as the clock cannot perform detection work due to the limitation of the number of the pulses, and the condition of abnormal detection judgment is prevented. The detection circuit 2 determines the final bus relationship by judging the address matching condition of the intermediate clock signal output by the output end of the pre-detection circuit 1 and the two input signals, and selects and outputs the data end and the clock end with correct relationship for subsequent units, so that address expansion through bus switching is realized, the judgment result of the connection relationship of the buses is accurate and reliable, and the realization circuit is simple.

The bus relation detection device judges the bus relation through the frequency relation, and compared with the judgment of the bus relation through the data characteristic relation, the bus relation detection device avoids the problem that command frames of instructions cannot meet data characteristics due to data distortion caused by the fact that data sent by a host is abnormal or the data are interfered in the transmission process, the work of a bus relation abnormality detection system cannot be shielded in time, and the bus relation is judged abnormally after enough pulses are provided. Therefore, the bus relation detection device has sufficient consideration on abnormal conditions and high accuracy of detection and judgment.

Please refer to fig. 3, which is a schematic structural diagram of a bus relationship detection apparatus according to an embodiment of the present application.

In this embodiment, the pre-detection circuit includes a pre-detection unit 11 and a gate control logic unit 12; the pre-detection unit 11 is configured to acquire the input signal through a first input port and a second input port, determine whether the preset frequency requirement is met according to at least one of the level change times, the number of rising edges, or the number of falling edges of the input signal, and output a corresponding clock control signal when the preset frequency requirement is met.

For example, the pre-detection unit 11 determines the signal frequency of the first input signal and the second input signal by determining the number of level changes of the first input signal and the second input signal through a level comparator and a counter, and then compares the signal frequency with a preset frequency requirement to determine whether the signal frequency is the intermediate clock signal, i.e., the bus clock signal SCL, or the data signal, i.e., the bus data signal SDA. The interference caused by signal glitch can be prevented by determining the signal frequency relation through the level change times.

Or, the number of rising edges or the number of falling edges of the two input signals are judged through the register to determine the signal frequency of the two input signals, and then the signal frequency is compared with a preset frequency requirement to determine whether the intermediate clock signal is the bus clock signal SCL or the data signal, namely the bus data signal SDA. The number of rising edges or the number of falling edges is judged through the register so as to determine that the signal frequency circuit is convenient to design.

The gate control logic unit 12 is connected to the pre-detection unit 11, and configured to select a corresponding input signal as the intermediate clock signal according to the clock control signal, and simultaneously close another input signal as the intermediate clock signal. Even if the current instruction cannot generate final judgment on the detection circuit by closing the output of the bus data signal SDA, the error detection operation cannot be generated due to the limitation of the number of clocks of the detection unit with the SDA bus input end as the clock, and the reliability of the bus relation detection device is ensured.

In an alternative embodiment, the pre-detection circuit further comprises a sequence detection unit 13; the sequence detection unit 13 is configured to obtain the input signal through a first input port and a second input port, and output a reset signal after detecting a flag bit in the input signal; the pre-detection unit 11 is connected to the sequence detection unit 13, and configured to reset according to the reset signal, and determine whether the preset frequency requirement is met according to at least one of the number of level changes, the number of rising edges, or the number of falling edges of the input signal after resetting.

Through the sequence detection unit 13, after the flag bit in the input signal is detected, a reset signal is output to control the pre-detection unit 11 to reset, the reset mode includes synchronous reset and asynchronous reset, preferably asynchronous reset, and whether the two input signals meet the preset frequency requirement can be judged after the two input signals are determined to be valid bus data signals SDA, so that the influence of invalid signals is further eliminated, and the accuracy of the frequency judgment result is improved.

In another alternative embodiment, the pre-detection unit 11 includes a first pre-detection subunit 111 and a second pre-detection subunit 112 with the same circuit structure; one of the two input signals is used as a first input signal, and the other input signal is used as a second input signal; the first pre-detection subunit 111 is connected to the sequence detection unit 13, and configured to perform asynchronous reset according to the reset signal, determine whether the preset frequency requirement is met according to at least one of the number of level changes, the number of falling edges, or the number of rising edges of the first input signal, and output a first clock control signal when the preset frequency requirement is met; the second pre-detection subunit 112 is connected to the sequence detection unit 13, and configured to perform asynchronous reset according to the reset signal, determine whether the preset frequency requirement is met according to at least one of the number of level changes, the number of falling edges, or the number of rising edges of the second input signal, and output a second clock control signal when the preset frequency requirement is met; the gate control logic unit 12 is connected to the first pre-detection subunit 111 and the second pre-detection subunit 112, and configured to select a corresponding input signal as the intermediate clock signal to be output according to the first clock control signal and the second clock control signal, and simultaneously turn off another input signal as the intermediate clock signal to be output.

Please refer to fig. 4, which is a schematic structural diagram of a bus relationship detection apparatus according to an embodiment of the present application.

The pre-detection circuit 1 of the present embodiment is composed of two pre-detection units (a first pre-detection subunit 111 and a second pre-detection subunit 112) and a sequence detection unit (a first sequence detection subunit SSC1 and a second sequence detection subunit SSC2), and the first pre-detection subunit 111 and the second pre-detection subunit 112 have the same structure.

The first pre-detection subunit 111 includes at least two registers and a first and gate device, wherein an input end of the first register Q1 is connected to a high level, a clock end is connected to the first input signal, a reset end is connected to the reset signal, an output end is connected to a first input end of the first and gate device a1, and a second input end of the first and gate device a1 is inverted and then connected to the second clock control signal gc 2; the output end of the first and gate device a1 is connected with the input end of a second register Q2, the clock end of the second register Q2 is connected with the first input signal, the reset end is connected with the reset signal, and the output end is used for outputting the first clock control signal gc 1.

The first pre-detection subunit 111 of this embodiment is formed by two stages of registers with a high1 &! The gc2 logic is constructed, and the first level register D is terminated with high level, the gc1 signal generated by the second level register is inverted and ANDed with the second input port, the clock terminal of the two level register is controlled by the falling edge of the first input port signal and supports asynchronous reset of the SSC1 signal, the SSC2 signal, and the flag signal of the second detection subunit 112.

The first pre-detection subunit 111 specifically operates according to the following principle: after the first register Q1 and the second register Q2 receive asynchronous reset of the reset signal, the output end of the first register Q1 outputs a high level high1 under the action of the first falling edge of the first input signal, when the second clock control signal gc2 is 0, the inverted signal is input to the first and gate device a1, the input end of the second register Q2 is high, and under the action of the second falling edge of the first input signal, the first clock control signal gc1 is output, so that the first pre-detection subunit 111 can output the first clock control signal gc1 as 1 after two clock falling edges, which indicates that the current first input signal is the bus clock signal SCL, and if the clock falling edge signal is not detected, the first clock control signal gc1 is 0.

In other alternative embodiments, the number of registers may be 3, 4, or more to enable detection of multiple clock falling edges.

The second pre-detection subunit 112 includes at least two registers and a second and gate device, wherein an input terminal of the third register Q3 is connected to a high level, a clock terminal is connected to the second input signal, a reset terminal is connected to the reset signal, an output terminal is connected to a first input terminal of the second and gate device a2, and a second input terminal of the second and gate device a2 is inverted and then connected to the first clock control signal gc 1; the output end of the second and-gate device a2 is connected to the input end of a fourth register Q4, the clock end of the fourth register Q4 is connected to the second input signal, the reset end is connected to the reset signal, and the output end is used for outputting the second clock control signal gc 2.

The second pre-detection subunit 112 of this embodiment is composed of two stages of registers with high2 &! The gc1 logic is constructed and the first stage register D is terminated high, the gc2 signal generated by the second stage register is negated and anded with the first input port, the clock terminals of the two stages of registers are controlled by the falling edge of the second input port signal and support asynchronous resetting of the SSC1 signal, the SSC2 signal, the flag signal of the first detector subunit 111.

The second pre-detection subunit 112 specifically operates according to the following principle: after the third register Q2 and the fourth register Q4 receive the asynchronous reset of the reset signal, the output end of the third register Q3 outputs a high level high2 under the action of the first falling edge of the first input signal, when the first clock control signal gc1 is 0, the inverted signal is input to the second and gate device a2, the input end of the fourth register Q4 is high, and under the action of the second falling edge of the second input signal, the second clock control signal gc2 is output, so that the second pre-detection subunit 112 may output the second clock control signal gc2 as 1 after two falling edges of the clock, which indicates that the current second input signal is the bus clock signal SCL, and if the clock falling edge signal is not detected, the second clock control signal gc2 is 0.

The flag bit is a sequence start condition flag bit SSC; the sequence detection unit comprises a first sequence detection sub-unit SSC1, a second sequence detection sub-unit SSC2 and a first OR gate device O1; the first sequence detection subunit SSC1 is configured to output a first intermediate reset signal to a first input terminal of the first or gate device O1 upon detection of a sequence start condition flag bit SSC in the second input signal; said second sequence detection subunit SSC2 is adapted to output a second intermediate reset signal to a second input of said first or gate device O1 upon detection of a sequence start condition flag bit SSC in said first input signal; the first or gate device O1 is configured to output the reset signal according to the first intermediate reset signal and the second intermediate reset signal.

The pre-detection circuit 1 uses the characteristic that the frequency of the bus clock signal SCL is at least 2 times of the frequency of the bus data signal SDA, and uses the first sequence detection subunit SSC1 and the second sequence detection subunit SSC2 to output a reset signal to control the first pre-detection subunit 111 and the second pre-detection subunit 112 to perform asynchronous reset after judging the SSC signal in advance, after resetting, the input signals of the first pre-detection subunit 111 and the second pre-detection subunit 112 reaching two falling edges first are the bus clock signal SCL, that is, the input end is the input end of the SCL bus, and the other input end is the input end of the SDA bus; at this time, the unit of the first pre-detection subunit 111 and the second pre-detection subunit 112 using the input terminal of the SCL bus as the clock first generates the clock control signal, the first clock control signal gc1 or the second clock control signal gc2, which can mask the generation of the clock control signal of the pre-detection unit using the input terminal of the SDA bus as the clock, and turn off the clock generation of the detection unit using the input terminal of the SDA bus as the clock through the gate control logic, and keep the clock of the detection unit using the input terminal of the SCL bus as the clock on.

The gate control logic unit comprises a third AND gate device A3 and a fourth AND gate device A4; the first input end of the third and-gate device a3 is connected with the output end of the second register Q2 after being inverted, and the second input end is connected with the second input signal; the third and gate device a3 is configured to control the second input signal to be output as a second intermediate clock signal gata _ clk2 according to the first clock control signal gc 1; a first input end of the fourth and-gate device a4 is connected with an output end of the fourth register Q4 after being inverted, and a second input end is connected with the first input signal; the fourth and gate device Q4 is configured to control the first input signal to be output as a first intermediate clock signal gata _ clk1 according to the second clock control signal.

As can be seen from the above description, after detecting that two clock falling edges exist in the first input signal or the second input signal, the first pre-detection subunit 111 and the second pre-detection subunit 112 output corresponding clock control signals as 1, the unit that does not detect the clock falling edge outputs a clock control signal as 0, and the third and gate device A3 and the fourth and gate device a4 turn off the input signal with the clock control signal as 0, that is, the signal for turning off the SDA bus is output to the detection circuit as an intermediate clock signal.

The detection circuit 2 comprises a first detection unit 21 and a second detection unit 22 which have the same circuit structure;

the first detecting unit 21 has a first input terminal for obtaining the first input signal data _ in1, a second input terminal for obtaining the first intermediate clock signal gata _ clk1, and a reset terminal for obtaining the reset signal, and the first detecting unit 21 is configured to perform address matching according to the first input signal data _ in1 and the first intermediate clock signal gata _ clk1 and output a first address matching signal id _ match 1. The second detecting unit 22 has a first input terminal for obtaining the second input signal data _ in2, a second input terminal for obtaining the second intermediate clock signal gata _ clk2, and a reset terminal for obtaining the reset signal, and is configured to perform address matching according to the second input signal data _ in2 and the second intermediate clock signal gata _ clk1 and output a second address matching signal id _ match 2.

The first detecting unit 21 generates a first address matching signal id _ match1 after the detection is successful, which is used to mask the detection operations of the second pre-detecting sub-unit 112 and the second detecting unit 22 under the current instruction, and select the correct data input (data _ in1) and clock input (gate _ clk1) for the subsequent data frame processing unit to use. The second detecting unit 22 generates a second address matching signal id _ match2 after the detection is successful, which is used to mask the detection operations of the first pre-detecting subunit 111 and the first detecting unit 21 under the current instruction, and select the correct data input (data _ in2) and clock input (gate _ clk2) for the post-signal selecting unit 23 to use.

The reset signal includes a first reset signal and a second reset signal, the first reset signal is used for controlling the first pre-detection subunit 111 to reset, and the second reset signal is used for controlling the second pre-detection subunit 112 to reset.

The sequence detection unit further comprises a second or gate device O2 and a third or gate device O3; a first input terminal of the second or gate device O2 is configured to obtain the first address matching signal id _ match1, a second input terminal thereof is connected to an output terminal of the first or gate device O1, and an output terminal thereof is configured to output the first reset signal; a first input terminal of the third or-gate device O3 is configured to obtain the second address matching signal id _ match2, a second input terminal is connected to an output terminal of the first or-gate device O1, and an output terminal is configured to output the second reset signal.

The detection single channel 2 further comprises a signal selection unit 23; the signal selecting unit 23 is connected to the first detecting unit 21 and the second detecting unit 22, and configured to select and output a matched bus clock signal and a matched bus data signal according to the first address matching signal id _ match1 and the second address matching signal id _ match 2.

The detection circuit of the present embodiment is constituted by two detection units (a first detection unit and a second detection unit) and a signal selection unit. The clock terminal gate _ clk1 of the first detection unit is controlled by the first input port, the data terminal data _ in1 is controlled by the second input port, and the SSC1 signal and the mark signal of the second detection unit are asynchronously reset; the clock terminal gate _ clk2 of the second detecting unit is controlled by the second input port, the data terminal data _ in2 is controlled by the first input port, and the SSC2 signal is supported to be reset asynchronously with the flag signal of the first detecting unit.

The detection circuit is characterized in that the bus relation of the input port is finally judged by verifying whether the slave equipment addresses of the current host sending command frame are matched, wherein the slave equipment addresses comprise BSID (broadcast address), GSID (group address) and USID (user-defined address), and different USIDs are reserved in the two detection circuits; the first detection unit supports asynchronous reset of an SSC1 signal, and the second detection unit supports asynchronous reset of an SSC2 signal, so that the detection result of the detection circuit is not locked, the bus relation of the input port of the slave needs to be detected again when the host sends a new instruction, real-time detection can be realized, and the detection accuracy is improved.

In an alternative further embodiment, the detection circuit 2 comprises a counter; the counter is used for counting according to the two input signals and the intermediate clock signal, performing address matching when the counting value is a preset value to determine the bus relation, and outputting the matched signals as a bus data signal and a bus clock signal. For example, the pre-detection circuit needs two clock edges to generate the clock control signal and mask the clock output of the other detection unit, but the detection circuit needs 4 intermediate clock signals to generate the address matching signal, so that the preset value can be set to 4, and when the counter counts to a value of 4, address matching is performed to determine the data signal and the intermediate clock signal with correct bus relationship, and output is performed. In other alternative embodiments, the preset value may be set to other values according to specific situations.

The detection single circuit further comprises a fourth or gate device O4 and a fifth or gate device O5, wherein a first input end of the fourth or gate device O4 is connected with an output end of the first sequence detection subunit SSC1, a second input end of the fourth or gate device O4 is connected with a first address matching signal id _ match1, and the fourth or gate device O4 is used for controlling the first detection unit 21 to reset according to the first reset signal or the first address matching signal; a first input terminal of the fifth or-gate device O5 is connected to an output terminal of the second sequence detection subunit SSC2, a second input terminal is connected to the second address matching signal id _ match2, and the fifth or-gate device O5 is configured to control the second detection unit 22 to reset according to the second reset signal or the second address matching signal.

In the embodiment, the pre-detection circuit supports asynchronous reset of the SSC1 signal and the SSC2 signal, the first detection unit supports reset of the SSC1 signal, and the second detection unit supports reset of the SSC2 signal, so that the bus detection device can perform detection of the bus relationship again when receiving a new command. The design has the advantages that even if the previous instruction is subjected to bus relation abnormity inspection, the new instruction can be judged again, and the condition that the slave machine cannot work normally due to mistaken locking is prevented.

The following specifically describes the working process of the bus relationship detection apparatus by way of example:

referring to fig. 5, a timing diagram of when the SCL bus is connected to the first input port and the SDA bus is connected to the second input port.

When the SCL bus is connected with the first input port and the SDA bus is connected with the second input port, the host sends a command sequence to the slave, firstly, the first sequence detection unit SSC1 detects a start signal SSC of the command sequence and outputs a reset signal SSC1 as 1, and the first pre-detection subunit and the second pre-detection subunit are reset to be in a state to be detected; then, the clock terminal of the first pre-detection subunit will come from two falling edge pulses first to make the first input terminal high1 of the first and gate be 1, the first clock control signal gc1 is valid first, (when the SSC2 signal is invalid), the valid first clock control signal gc1 will make the D terminal of the second stage register of the second pre-detection subunit keep 0 so as to make the second clock control signal gc2 invalid and be 0, thus realizing the shielding function, and the valid first clock control signal gc1 takes the phase of inverting the phase of the second output port (port connected with the SDA bus) and the phase of the signal causing gate _ SDA 2 (intermediate clock signal with the SDA bus as) to be 0 to turn off; since the second clock control signal gc2 is kept at 0 at this time, the gate _ clk1 intermediate clock signal (the intermediate clock signal of the SCL bus) is always turned on, so that the subsequent first detecting unit can operate normally, and the clock of the second detecting unit is turned off to stop the circuit operation.

Referring to fig. 6, a timing diagram of when the SDA bus is connected to the first input port and the SCL bus is connected to the second input port.

When the SDA bus is connected with the first input port and the SCL bus is connected with the second input port, the host sends a command sequence to the slave, firstly, the second sequence detection unit SSC2 detects a start signal SSC of the command sequence and outputs a reset signal SSC2 to be effective, and the first pre-detection subunit and the second pre-detection subunit are reset to be in a state to be detected; then, the clock terminal of the second pre-detection unit firstly receives two falling edge pulses to enable high2 and the second clock control signal gc2 to be firstly valid (when the SSC1 signal is invalid), the valid second clock control signal gc2 can enable the D terminal of the second-stage register of the first pre-detection subunit to be kept at 0, so that the first clock control signal gc1 is invalid to play a shielding role, and the valid second clock control signal gc2 inverts the phase of the first output port (the port connected with the SDA bus) and enables the phase of the gate _ 1 (the middle clock signal used by the SDA bus) to be converted into 0 to be turned off; since the gc1 signal is kept at 0 at this time, the gate _ clk2 intermediate clock signal (the intermediate clock signal of the SCL bus) is always turned on, so that the subsequent second detecting unit can operate normally, and the clock of the first detecting unit is turned off to stop the circuit operation.

Therefore, the pre-detection circuit is designed according to the frequency characteristics between the SCL bus and the SDA bus, the relationship of the bus input ends can be recognized in advance, the clock generation of the SDA bus input end serving as the detection unit of the clock is closed in a gating mode, even if the current instruction cannot generate final judgment on the detection circuit, the first two clock edges are limited by the number of the clocks of the detection unit with the SDA bus input end serving as the clock, false detection operation cannot be generated, and the reliability of the bus relationship detection device is guaranteed.

The bus relation detection device carries out bus identification by using the combination of the pre-detection circuit and the detection circuit, can realize the function of 2 address extensions, and has the advantages of simple realization principle and accurate and reliable judgment result.

Referring to fig. 7, a schematic structural diagram of a slave device according to an embodiment of the present application is shown.

The slave device comprises the bus relation detection device 7-1 and a data processing unit 7-2; the first input port is connected with a first input end in the bus relation detection device 7-1; the second input port is connected with the second input end; the data processing unit 7-2 is connected with the detection circuit 1 in the bus relation detection device 7-1; the first input port is used for receiving a bus clock signal or a bus data signal; the second input port is used for receiving a bus data signal or a bus clock signal;

the bus relation detection device 7-1 is used for selecting a matched bus data signal and a matched bus clock signal according to the frequency relation of the input signals and sending the bus data signal and the matched bus clock signal to the data processing unit 7-2; the data processing unit 7-2 is configured to process the received bus data signal and the bus clock signal.

Optionally, the slave devices include MIPI RFFR slave devices and other communication slave devices.

Optionally, the first input port is generally an SCLK end in the MIPI RFFE slave device, and the second input port is generally an SDA end in the MIPI RFFE slave device.

According to the slave device of the embodiment, the bus relationship can be judged in advance according to the frequency relationship of the bus signals through the bus relationship detection device, and the final bus relationship is determined by judging the address matching according to the detection circuit, so that the address expansion is realized, the circuit is simple, and the judgment result of the bus connection relationship is accurate and reliable.

In an alternative embodiment, the data processing unit 7-2 includes a data frame processing unit and state machine 31 and a register 42; the data frame processing unit and the state machine 41 are connected to the bus relation detecting device 7-1, and configured to receive a command in the bus data signal and process the command. Optionally, the command is an RFFE command, or a command specified by another communication protocol.

The register 42 has a first input end connected to the output end of the data frame processing unit and the state machine 41, and a second input end connected to the detection circuit, and is configured to receive a slave address in the bus data signal and process the slave address.

The slave device of the embodiment can determine the connection relation of the bus according to the frequency relation of the input signal, and the judgment result of the connection relation of the bus is accurate and reliable.

Referring to fig. 8, the present application further provides a communication system.

An embodiment of the present application further provides a communication system, including: the master device 8-1, at least two slave devices described above, in this embodiment, the slave device includes a first slave device and a second slave device as an example; the first slave device 8-2 and the second slave device 8-3 are two devices of the same kind manufactured by the same manufacturer; the clock terminal SCLK of the master device 8-1 is connected to the first input port of the first slave device 8-2 and the second input port of the second slave device 8-3, respectively, and the data terminal SDA of the master device is connected to the second input port of the first slave device and the first input port of the second slave device, respectively. The first input ports of the first slave device 8-2 and the second slave device 8-3 are both the clock port SCLK and the second input ports are both the data port SDA.

The communication system of the embodiment implements address expansion of the slave device by switching the SCL and the SDA buses, so that the master device can distinguish two slave devices with the same USID, PID, and MfrlID, and the bus collision problem of the two identical slave devices in the system can be accurately and reliably solved.

Optionally, the communication system is a MIPI RFFE system, the master device is a MIPI RFFE master device, and the slave device is a MIPI RFFE slave device. In the MIPI RFFE system, the USID, the PID and the MID of two devices of the same kind, which are manufactured by a first MIPI RFFE slave device and a second MIPI RFFE slave device for the same manufacturer, are the same; the clock end of the MIPI RFFE master device is connected to the first input port of the first MIPI RFFE slave device and the second input port of the second MIPI RFFE slave device, respectively, and the data end of the MIPI RFFE master device is connected to the second input port of the first MIPI RFFE slave device and the first input port of the second MIPI RFFE slave device, respectively.

The clock terminal (SCLK) of the MIPI RFFE master device is respectively connected with the first input port (SCLK) of the first MIPI RFFE slave device and the second input port (SDA) of the second MIPI RFFE slave device, and the data terminal (SDA) of the MIPI RFFE master device is respectively connected with the second input port (SDA) of the first MIPI RFFE slave device and the first input port (SCLK) of the second MIPI RFFE slave device.

The MIPI RFFE system of this embodiment realizes address expansion of the slave device by performing SCL and SDA bus switching, so that the MIPI RFFE master device can distinguish two slave devices that are the same as the USID, PID, and MfrlID, and the bus collision problem of two completely same MIPI RFFE slave devices in the MIPI RFFE system can be accurately and reliably solved, the circuit of implementation is simple, and the connection relation determination result of the bus is accurate and reliable.

The application also provides a radio frequency chip which comprises a circuit interface formed by the bus relation detection device. The radio frequency chip can realize the communication of two devices with the same address through the circuit interface formed by the bus relation detection device, and has high communication accuracy.

The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.

Claims

1. A bus relationship detecting apparatus, comprising:

the system comprises a pre-detection circuit, a first frequency detection circuit, a second frequency detection circuit and a control circuit, wherein the pre-detection circuit is used for acquiring two input signals through a first input port and a second input port, the two input signals are respectively a bus clock signal and a bus data signal, and only the input signal meeting the requirement of preset frequency is output as an intermediate clock signal;

and the detection circuit is connected with the pre-detection circuit and used for carrying out address matching according to the two input signals and the intermediate clock signal so as to determine the bus relation and outputting the matched bus data signal and the matched bus clock signal.

2. The bus relationship detection device of claim 1, wherein the pre-detection circuit includes a pre-detection unit and a gate control logic unit;

the pre-detection unit is used for acquiring the input signal through a first input port and a second input port, determining whether the preset frequency requirement is met according to at least one of the level change times, the rising edge number or the falling edge number of the input signal, and outputting a corresponding clock control signal when the preset frequency requirement is met;

and the gating logic unit is connected with the pre-detection unit and used for selecting a corresponding input signal as the intermediate clock signal to be output according to the clock control signal and simultaneously closing the other input signal as the intermediate clock signal to be output.

3. The bus relationship detecting device according to claim 2, wherein the pre-detection circuit further includes a sequence detecting unit;

the sequence detection unit is used for acquiring the input signal through a first input port and a second input port and outputting a reset signal after detecting a flag bit in the input signal;

the pre-detection unit is connected with the sequence detection unit and used for resetting according to the reset signal and determining whether the preset frequency requirement is met according to at least one of the level change times, the rising edge number or the falling edge number of the input signal after resetting.

4. The bus relationship detection device according to claim 3, wherein the pre-detection unit includes a first pre-detection subunit and a second pre-detection subunit having the same circuit structure;

one of the two input signals is used as a first input signal, and the other input signal is used as a second input signal;

the first pre-detection subunit is connected with the sequence detection unit and is used for performing asynchronous reset according to the reset signal, determining whether the preset frequency requirement is met according to at least one of the level change times, the falling edge number or the rising edge number of the first input signal, and outputting a first clock control signal when the preset frequency requirement is met;

the second pre-detection subunit is connected with the sequence detection unit and is used for performing asynchronous reset according to the reset signal, determining whether the preset frequency requirement is met according to at least one of the level change times, the falling edge number or the rising edge number of the second input signal, and outputting a second clock control signal when the preset frequency requirement is met;

and the gating logic unit is connected with the first pre-detection unit and the second pre-detection unit and is used for selecting a corresponding input signal as the intermediate clock signal to be output according to the first clock control signal and the second clock control signal and simultaneously closing the other input signal as the intermediate clock signal to be output.

5. The bus relationship detection device according to claim 4, wherein the first pre-detection subunit includes at least two registers and a first AND gate device, wherein an input terminal of the first register is connected to a high level, a clock terminal is connected to the first input signal, a reset terminal is connected to the reset signal, an output terminal is connected to a first input terminal of the first AND gate device, and a second input terminal of the first AND gate device is inverted and then connected to the second clock control signal;

the output end of the first AND gate device is connected with the input end of a second register, the clock end of the second register is connected with the first input signal, the reset end is connected with the reset signal, and the output end is used for outputting the first clock control signal;

the second pre-detection subunit comprises at least two registers and a second AND gate device, wherein the input end of a third register is connected with a high level, a clock end is connected with the second input signal, a reset end is connected with the reset signal, the output end is connected with the first input end of the second AND gate device, and the second input end of the second AND gate device is connected with the first clock control signal after being inverted;

the output end of the second AND gate device is connected with the input end of a fourth register, the clock end of the fourth register is connected with the second input signal, the reset end is connected with the reset signal, and the output end is used for outputting the second clock control signal.

6. The bus relationship detection device of claim 5, wherein the flag bit is a sequence start condition flag bit;

the sequence detection unit comprises a first sequence detection subunit, a second sequence detection subunit and a first OR gate device;

the first sequence detection subunit is configured to output a first intermediate reset signal to the first input terminal of the first or gate device after detecting the sequence start condition flag bit in the second input signal;

the second sequence detection subunit is configured to output a second intermediate reset signal to the second input terminal of the first or gate device after detecting the sequence start condition flag bit in the first input signal;

the first or gate device is configured to output the reset signal according to the first intermediate reset signal and the second intermediate reset signal.

7. The bus relationship detection device of claim 6, wherein the gate control logic unit comprises a third AND gate device and a fourth AND gate device;

the first input end of the third AND gate device is connected with the output end of the second register after being inverted, and the second input end of the third AND gate device is connected with the second input signal;

the third AND gate device is used for controlling the second input signal to be output as a second intermediate clock signal according to the first clock control signal;

the first input end of the fourth AND gate device is connected with the output end of the fourth register after being inverted, and the second input end of the fourth AND gate device is connected with the first input signal;

and the fourth AND gate device is used for controlling the first input signal to be output as a first intermediate clock signal according to the second clock control signal.

8. The bus relationship detection device of claim 7, wherein the detection circuit includes a first detection unit and a second detection unit;

a first input end of the first detection unit is used for acquiring the first input signal, a second input end of the first detection unit is used for acquiring the first intermediate clock signal, a reset end of the first detection unit is used for acquiring the reset signal, and the first detection unit is used for performing address matching according to the first input signal and the first intermediate clock signal and outputting a first address matching signal;

the first input end of the second detection unit is used for acquiring the second input signal, the second input end of the second detection unit is used for acquiring the second intermediate clock signal, the reset end of the second detection unit is used for acquiring the reset signal, and the second detection unit is used for performing address matching according to the second input signal and the second intermediate clock signal and outputting a second address matching signal.

9. The bus relationship detecting device according to claim 8, wherein the detecting unit further includes a signal selecting unit;

the signal selection unit is connected with the first detection unit and the second detection unit and is used for selecting and outputting a matched bus clock signal and a matched bus data signal according to the first address matching signal and the second address matching signal.

10. The bus relationship detecting device as claimed in claim 8, wherein the reset signal comprises a first reset signal and a second reset signal, the first reset signal is used for controlling the first pre-detecting subunit to reset, the second reset signal is used for controlling the second pre-detecting subunit to reset;

the sequence detection unit further comprises a second or gate device and a third or gate device;

a first input end of the second or gate device is used for acquiring the first address matching signal, a second input end of the second or gate device is connected with an output end of the first or gate device, and an output end of the second or gate device is used for outputting the first reset signal;

the first input end of the third or gate device is used for obtaining the second address matching signal, the second input end of the third or gate device is connected with the output end of the first or gate device, and the output end of the third or gate device is used for outputting the second reset signal.

11. The bus relationship detection device of claim 1, wherein the detection circuit includes a counter;

the counter is used for counting according to the two input signals and the intermediate clock signal, performing address matching when the counting value is a preset value to determine the bus relation, and outputting the matched signals as a bus data signal and a bus clock signal.

12. A slave device, comprising: a bus relationship detection device and a data processing unit according to any of claims 1-11;

the bus relation detection device is used for selecting a matched bus data signal and a matched bus clock signal according to the frequency relation of the input signals and sending the bus data signal and the matched bus clock signal to the data processing unit;

and the data processing unit is connected with the bus relation detection device and is used for processing the received bus data signal and the received bus clock signal.

13. The slave device of claim 12, wherein the data processing unit comprises a data frame processing unit and a state machine and register module;

the data frame processing unit and the state machine are connected with the bus relation detection device and are used for receiving the command in the bus data signal and processing the command;

and the first input end of the register is connected with the data frame processing unit and the output end of the state machine, and the second input end of the register is connected with the detection circuit, and is used for receiving a slave device address in the bus data signal and processing the slave device address.

14. A communication system, comprising: a master device, at least two slave devices according to claim 12 or 13; the first slave device and the second slave device are two devices of the same kind manufactured by the same manufacturer;

the clock end of the master device is connected to the first input port of the first slave device and the second input port of the second slave device, respectively, and the data end of the master device is connected to the second input port of the first slave device and the first input port of the second slave device, respectively.

15. A radio frequency chip comprising a circuit interface formed by the bus relation detection apparatus according to any one of claims 1 to 11.