CN110647486B

CN110647486B - PCIe link training method, end equipment and communication system

Info

Publication number: CN110647486B
Application number: CN201910936651.4A
Authority: CN
Inventors: 刘海亮
Original assignee: Jiangsu Xinsheng Intelligent Technology Co ltd
Current assignee: Jiangsu Xinsheng Intelligent Technology Co ltd
Priority date: 2019-09-29
Filing date: 2019-09-29
Publication date: 2021-05-11
Anticipated expiration: 2039-09-29
Also published as: CN110647486A

Abstract

The application provides a PCIe link training method, end equipment and a communication system, and relates to the technical field of solid state disks. The link training method is applied to end equipment, the end equipment comprises a shift register and a CPU, after a first reset release signal is received, the shift register carries out bitwise AND operation on the received reset signal to obtain a processed reset signal, and then the CPU starts PCIe link training according to the processed reset signal. The PCIe link training method, the end device and the communication system have the advantage of improving the robustness of the end device in the link training process.

Description

PCIe link training method, end equipment and communication system

Technical Field

The application relates to the technical field of solid state disks, in particular to a PCIe link training method, end equipment and a communication system.

Background

Pcie (peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard, proposed by intel in 2001, as a third generation high-speed serial bus, intended to replace the old PCI, PCI-X, AGP bus standards. Since PCIe has been proposed, it has been widely applied in the fields of personal computers, servers, solid state disks, data centers, and the like, with the characteristics of fast transmission rate, reliable end-to-end transmission, hot plug support, power management, and quality of service.

PCIe link training is the premise that two PCIe devices perform normal communication, and in the actual application process, because the specific methods of host sides of different manufacturers are different, various problems can exist in the PCIe link training process, which causes link training failure.

However, the prior art does not start from the end device to improve the robustness of the end device in the link training process.

Disclosure of Invention

The invention aims to provide a PCIe link training method to solve the problem that the robustness in the link training process is not improved from the starting of end equipment in the prior art.

Another object of the present invention is to provide an end device, so as to solve the problem in the prior art that the robustness in the link training process is not improved from the end device.

Another objective of the present invention is to provide a communication system to solve the problem in the prior art that robustness in the link training process is not improved from the end device.

In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:

in a first aspect, an embodiment of the present invention provides a PCIe link training method, where the link training method is applied to an end device, the end device includes a shift register and a CPU, and the method includes:

after receiving a first reset release signal, the shift register performs bitwise AND operation on the received reset signal to obtain a processed reset signal;

and the CPU starts PCIe link training according to the processed reset signal.

Further, the end device further includes a power-on reset register, a configuration register, a PCIe kernel reset register, and a channel register, the CPU is electrically connected to the power-on reset register, the configuration register, the PCIe kernel reset register, and the channel register, the power-on reset register is electrically connected to the configuration register, and the step of the CPU starting PCIe link training according to the training signal includes:

when the CPU reads a second reset release signal, releasing the power-on reset register through the configuration register after preset time;

when the power-on reset register is released and the CPU simultaneously reads that the value of the PCIe kernel reset register is in a high level, releasing a channel register to open all the paths in the PCIe link; wherein the lane register is electrically connected to each lane in the PCIe link;

and when the CPU determines that at least one path in the PCIe link is in a data interaction state, starting PCIe link training.

Further, the end device further includes a training control enable register and a link training state machine, the link training state machine is used for performing link training in a PCIe link, the training control enable register is electrically connected to the link training state machine, the training control enable register is further electrically connected to the CPU, and before the step of starting PCIe link training when the CPU determines that at least one path in the PCIe link is in a data interaction state, the method further includes:

the CPU controls the training control enabling register to be in a non-enabling state so as to enable the link training state machine to be in a non-working state;

when the CPU determines that at least one path in the PCIe link is in a data interaction state, the step of starting the PCIe link training comprises the following steps:

and when the CPU determines that at least one path in the PCIe link is in a data interaction state, the CPU controls a training control enabling register to be in an enabling state so as to enable the link training state machine to be in a working state.

Further, the end device further includes an electrical idle register, the CPU is electrically connected to the electrical idle register, and before the step of initiating PCIe link training when the CPU determines that at least one lane in the PCIe link is active, the method further includes:

the CPU reads data of an electrical idle register in real time and determines whether the data of the electrical idle register has a low level signal or not so as to determine whether at least one path exists in the PCIe link and is in a data interaction state or not; wherein the electrical idle register is used for recording the state of all paths in the PCIe link.

Further, before the step of determining whether a low level signal is present in the data of the electrical idle register, the method further comprises:

and the electric idle register shifts the data corresponding to each channel, and performs bitwise AND operation on the shifted data of each channel, wherein the data corresponding to the channel in the data interaction state is at a low level.

Further, the end device further includes a common register, and before the step of releasing the lane register to open all lanes in the PCIe link, the method further includes:

the CPU configures the common register to a low level.

Further, the end device further includes an interrupt circuit, and when the PCIe is in a warm reset period, the step of obtaining the computed training signal includes:

the interrupt circuit carries out rising edge and falling edge generation processing and interrupt signal extraction processing on the reset signal after the shift register operation so as to obtain an interrupt signal;

the step that the CPU starts PCIe link training according to the processed reset signal comprises the following steps:

and the CPU starts PCIe link training according to the interrupt signal.

Further, the end device further includes a sampling circuit, and before the step of performing a bitwise and operation on the received reset signal by the shift register, the method further includes:

the sampling circuit samples the reset signal;

the step of the shift register carrying out bitwise AND operation on the received reset signal comprises the following steps:

and the shift register performs bit AND operation on the sampled reset signal according to bytes.

In a second aspect, an embodiment of the present invention provides a PCIe link training method, where the link training method is applied to an end device, the end device further includes a power-on reset register, a configuration register, a PCIe kernel reset register, and a channel register, the CPU is electrically connected to the power-on reset register, the configuration register, the PCIe kernel reset register, and the channel register, and the power-on reset register is electrically connected to the configuration register, and the method includes:

when the CPU reads a reset release signal, releasing a power-on reset register through a configuration register after a preset time;

In a third aspect, an embodiment of the present invention further provides an end device, where the end device is configured to implement the PCIe link training method described above.

In a fourth aspect, an embodiment of the present invention further provides a communication system, where the communication system includes a main device, a communication line, and an end device, the main device and the end device are communicatively connected through the communication line, and the end device is configured to implement the PCIe link training method.

Compared with the prior art, the method has the following beneficial effects:

the embodiment of the invention provides a PCIe link training method, end equipment and a communication system, wherein the link training method is applied to the end equipment, the end equipment comprises a shift register and a CPU, after a first reset release signal is received, the shift register carries out bit-wise AND operation on the received reset signal to obtain a processed reset signal, and then the CPU starts PCIe link training according to the processed reset signal. Since the reset signal of the master device to the end device is the low active sideband reset signal, that is, when the signal is at low level, it indicates that the current power supply is stable. And the reset signal may have glitches and instability due to possible jitter in the circuit. After the end equipment receives the reset signal, the reset signal is operated according to the bit, and then burrs and unstable operations of the reset signal are eliminated in a hardware mode, so that the robustness of the reset signal is enhanced, and the robustness of the end equipment in a link training process is improved.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic flowchart of a PCIe link training method according to an embodiment of the present application.

Fig. 2 is a schematic block diagram of an end device provided in an embodiment of the present application.

Fig. 3 is a schematic flowchart of the S101 sub-step in fig. 1 provided in an embodiment of the present application.

Fig. 4 is another schematic flowchart of the S101 sub-step in fig. 1 provided in an embodiment of the present application.

Fig. 5 is a schematic flowchart of the S103 sub-step in fig. 1 provided in an embodiment of the present application.

Fig. 6 is another schematic flowchart of the S103 sub-step in fig. 1 provided in an embodiment of the present application.

Fig. 7 is an exemplary timing diagram for PCIe link training initialization according to an embodiment of the present application.

Fig. 8 is a schematic flowchart of another PCIe link training method provided in the embodiment of the present application.

Icon: 200-end equipment; 210-CPU, 220-configuration register; 230-PCIe core reset register; 240-power on reset register; 250-train control enable register; 260-link training state machine; 270-appliance idle register; 280-common registers; 290-channel register.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.

In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

First embodiment

As described in the background, PCIe (peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard.

PCIe link training is the premise that PCIe main equipment and PCIe end equipment normally communicate, and in the actual application process, because the specific methods of host sides of different manufacturers are different, various problems can exist in the PCIe link training process, so that link training fails.

In order to improve the robustness of PCIe link training, improvement is generally performed at the main device end at present, so as to improve the robustness of link training. However, the prior art does not improve the robustness of the end device in the link training process by starting from the end device.

In view of this, the present application provides a PCIe link training method to achieve that starting from an end device, robustness of the end device in a link training process is improved.

The PCIe link training method provided in the present application is exemplarily described below with an end device as an execution subject.

As an implementation manner of the present application, please refer to fig. 1 and fig. 2, in which the PCIe link training method includes:

s101, after receiving the first reset release signal, the shift register carries out bitwise AND operation on the received reset signal and obtains a processed reset signal.

S103, the CPU starts PCIe link training according to the processed reset signal.

Before the master device and the peer device 200 need to communicate, PCIe link training needs to be performed first. When the link training needs to be started, the end device 200 needs to be reset first.

At this time, the master device sends a reset signal to the peer device 200, where the reset signal is PERST #, and PERST # is an active-low sideband reset signal sent by the PCIe master device to the peer device 200, and when the signal is low, it indicates that the current power supply is stable, and starts the reset operation of the peer device 200. The present invention enhances the robustness of PERST # by technical means, since jitter may be present in the circuit.

After receiving the first reset release signal, the shift register performs bit-wise and operation on the received reset signal to obtain a processed reset signal. For example, when the CPU210 receives the first reset release signal, the processed reset signal is output to a shift register of 32-bit width to perform a bit-wise and operation using the 32-bit shift register to acquire the processed reset signal. And provides the processed reset signal for software use, and CPU210 initiates PCIe link training according to the processed reset signal.

Through the processing mode, the burrs and unstable operation of the PERST # signal can be effectively filtered, and the robustness of the PERST # signal is enhanced.

It should be noted that, as a possible implementation manner of the present application, the first chip reset release signal described in the present application is a signal generated when the master device terminates sending the reset signal to the end device 200, that is, when the master device finishes sending the reset signal to the end device 200, the end device 200 may detect the corresponding first reset release signal, and at this time, the end device 200 starts processing the reset signal. Moreover, the principle of improving the robustness of the PERST # signal after bitwise AND operation in the application is as follows:

when the PERST # signal generates a glitch, a transition may occur in a part of the signal because the PERST # signal is an active-low sideband reset signal. For example, the PERST # signal is 0000, and when a glitch occurs, the PERST # signal changes to 0001. In addition, the bitwise and operation described in the present application is two bitwise and operations, for example, an and logic is performed between the signal of the previous cycle and the signal of the next cycle, and it can be understood that the processed PERST # signal is 0000, and thus the effect of filtering out the glitch and the unstable operation of the PERST # signal can be achieved.

As a possible implementation manner of the present application, the end device 200 further includes a sampling circuit, please refer to fig. 3, and S101 includes:

s101-1, after receiving the first reset release signal, the sampling circuit samples the reset signal.

S101-2, the shift register carries out bit AND operation on the sampled reset signal according to bytes.

That is, in the implementation process of the present application, after the CPU210 receives the first reset release signal, the sampling circuit is used to sample the reset signal, for example, the sampling circuit is aux _ clk auxiliary clock, the aux _ clk auxiliary clock is used to sample the PERST # signal, and the sampled signal reset signal is input to the shift register with a bit width of 32 bits, and then the result of the shift register with 32 bits is bitwise and operated, and the bitwise and the following reset signal are stored in the register and then stored as the PERST # signal in the PCIe core.

The processed PERST # signal is directly used by software and is suitable for a cold reset period, and when the signal is in a warm reset period, the signal can be used by the software by utilizing an interrupt signal. When the end device 200 starts to operate during the cold reset period, the circuits in the end device 200 do not start to operate completely, and thus the signal is not interrupted at this time. When the terminal device 200 is in the warm reset period, since the circuits in the terminal device 200 have all started to operate, the interrupt signal can be generated at this time, and when the software is processed according to the interrupt signal, the processing speed of the software is faster, so that the interrupt signal is used by the software at this time.

That is, when PCIe is in the warm reset period, please refer to fig. 4, S101 includes:

s101-a, after receiving the first reset release signal, the shift register carries out bitwise AND operation on the received reset signal.

And S101-b, the interrupt circuit carries out rising edge and falling edge generation processing and interrupt signal extraction processing on the reset signal after the shift register operation so as to obtain an interrupt signal.

The end device 200 includes an interrupt circuit, and the interrupt signal is generated based on the computed PERST # signal, so that the glitch and unstable operation of the PERST # signal can be filtered. The interrupt circuit can detect a rising edge and a falling edge of the computed PERST # signal, and generate an interrupt signal according to the detected rising edge and falling edge, for example, when the interrupt circuit detects the rising edge.

Moreover, when the PCIe is in the warm reset period, the CPU210 also starts PCIe link training according to the interrupt signal.

Meanwhile, it should be noted that, the CPU210 starts PCIe link training according to the processed reset signal, and generally includes formal link training and a preparation process before link training.

Referring to fig. 5 as an implementation manner of the present application, S103 includes:

s103-1, when the CPU210 reads the second reset release signal, the power-on reset register is released through the configuration register 220 after a preset time.

S103-3, when the power-on reset register is released and the CPU210 simultaneously reads that the value of the PCIe kernel reset register is in a high level, the channel register is released to open all the paths in the PCIe link.

S103-5, when the CPU210 determines that at least one path in the PCIe link is in a data interaction state, starting PCIe link training.

The end device 200 further includes a power-on reset register 240, a configuration register 220, a PCIe core reset register 230, and a channel register 290, the CPU210 is electrically connected to the power-on reset register 240, the configuration register 220, the PCIe core reset register 230, and the channel register 290, and the power-on reset register 240 is electrically connected to the configuration register 220.

It should be noted that the end device 200 generally includes a PHY function module, a Controller function module, and a control top-level function module, and the PHY function module, the Controller function module, and the control top-level function module all include a plurality of registers. For example, the PHY function block includes a lane register therein.

Before the link training needs to be started, the PHY function module and the Controller function module need to be enabled first. In other words, in order to achieve robustness in the PCIe link training process, the corresponding registers need to be started in sequence, so that robustness in PCIe link training is ensured.

Therefore, when the CPU210 reads the second reset release signal, the power-on reset register 240 is released through the configuration register 220 after a preset time. As an implementation manner of the present application, the second reset release signal is associated with the first reset release signal. For example, the end device 200 further includes a register generating a second reset release signal, and when the CPU210 detects the second reset release signal of the register through software, it indicates that the preparation for link training can be started at this time.

In addition, after the power-on reset register 240 provided in this application is released, it indicates that the PHY function module and the Controller function module of the peer device 200 are already in a state where they can start to operate. Since it is necessary to wait for at least a period of time to release the reset signal in the PHY function module after the PHY function module of the end device 200 is stable after receiving the second reset release signal, which indicates that the end device 200 has started to be powered on, it is necessary to wait for a preset time to release the power-on reset register 240 through the configuration register 220. As one implementation, the preset time is set to 25 us. I.e., after 25us, the software releases the PCIe power up reset (power on reset register 240).

Moreover, after the power-on reset register 240 is released, hardware reset implementation and circuit state detection are performed in the PCIe core reset register 230, after the condition is satisfied, the core _ rst _ n (PCIe core reset register 230) is released, the core _ rst _ n is released, the register configuration buses of the PCIe PHY function module and the Controller function module are activated, and then register configuration of the PHY function module and the Controller function module can be performed.

In other words, when the CPU210 reads the second reset release signal, it is necessary to configure the registers of the PHY function module and the Controller function module after the power-on reset register 240 is released and the CPU210 simultaneously reads that the value of the PCIe core reset register 230 is at a high level. Wherein, when the value of the PCIe core reset register 230 is high, it indicates that it is already in the release state.

Since the channel register 290 is a kind of register in the PHY functional module, when the PHY functional module and the Controller functional module can be configured, the channel register 290 can be released, so as to open all the paths in the PCIe link. In the present application, the number of the lane registers is pipe _ lane _ reset _ n, for example, if the number of the PCIe lanes is 4, the number of the lane registers may also be four, which are pipe _ lane0_ reset _ n, pipe _ lane2_ reset _ n, pipe _ lane x _ reset _ n, and pipe _ lane3_ reset _ n.

And when the CPU210 determines that at least one path in the PCIe link is in the data interaction state, it indicates that at least one PCIe lane is active, and at this time, the CPU210 starts PCIe link training.

Moreover, on the basis of the above implementation, the end device 200 further includes a training control enabling register 250 and a link training state machine 260, where the link training state machine 260 is configured to perform link training in a PCIe link, the training control enabling register 250 is electrically connected to the link training state machine 260, and the training control enabling register 250 is further electrically connected to the CPU 210. In order to achieve robustness during link training, different registers need to be enabled according to strict time sequence and time requirement, so that when a PCIe lane is started and at least one PCIe lane is active, the training control enabling register 250 is always in a non-enabled state, so that the link training state machine 260 does not work.

That is, as an implementation manner, after S103-1, referring to fig. 6, S103 further includes:

s103-2a, the CPU controls the training control enabling register to be in a non-enabling state, so that the link training state machine is in a non-working state.

The step of S103-5 includes:

s103-5a, when the CPU determines that at least one path in the PCIe link is in a data interaction state, the CPU controls the training control enabling register to be in an enabling state, so that the link training state machine is in a working state.

The training control enable register 250 provided in the present application is app _ ltssm _ enable, when app _ ltssm _ enable is 0, it indicates that the training control enable register 250 is in a disabled state at this time, the link training state machine 260 does not operate at this time, and when app _ ltssm _ enable is 1, it indicates that the training control enable register 250 is in an enabled state at this time, the link training state machine 260 operates to start link training.

Meanwhile, the end device 200 further includes a common register 280, the common register 280 is connected to the CPU210, and before the step of S103-3, the step of S103 further includes:

s103-2b, the CPU configures the common register to be at a low level.

The PHY function module includes a common register 280 and a channel register 290, and when the PHY function module is released, the CPU210 first configures other registers in the PHY function module, and after the configuration is completed, first configures the common register 280 to be a low level. After configuration is complete, the channel registers 290 are then reconfigured high, even though this indicates that all channels in the PCIe link have been opened.

As an implementation manner of the present application, the end device 200 further includes an electrical idle register, the CPU210 is electrically connected to the electrical idle register, and before the step S103-5, the PCIe link training method further includes:

and S103-4, the electrical idle register shifts the data corresponding to each channel, and performs bitwise AND operation on the shifted data of each channel, wherein the data corresponding to the channel in the data interaction state is at a low level.

After CPU210 releases the pull-channel register 290, the channel register 290 is configured high, and each channel is turned on in euro. Thereafter, the electrical idle register always detects whether the bus of the side device 200 is in an idle state, and when there is data transmission in a certain channel on the bus, the signal of the channel for transmitting data is at a low level.

In addition, in the hardware circuit, the method of enhancing the robustness of the PERST # signal is used, the shift operation is performed by using 4 registers with 32-bit width, and the bitwise and operation is performed on each 32-bit data after the shift, taking the number of PCIe lanes as an example, the processed data finally constitutes a 4-bit electrical idle register signal, and certainly, when the number of lanes is 8, an 8-bit signal is constituted, which is not limited in this application. When any bit of the electrical idle register is 0, it indicates that there is a channel in the 4 channels to start receiving data, and the master device is already starting training the PCIe link.

For the processing of each channel signal, for example, taking any channel as an example, when the channel register 290 is enabled, the channel is turned on, and the channel signal detected by the electrical idle register is 1 at this time, that is, the channel is at a high level at this time. And, the electrical idle register will periodically acquire the channel signal, for example, or 4 cycles of signals, which are 1, and 0, respectively. And then, carrying out bitwise AND operation on the signals in 4 periods, and finally obtaining that the channel signal is 0, which indicates that the channel has data transmission.

And for all channels, in the detection process of the electrical idle register, when a channel is idle, a detected signal is 1111, which indicates that 4 channels are all high level, and at this time, four channels are all in idle state. And when the detected signal is not 1111, the detected signals all indicate that at least one channel in the 4 channels is active. For example, if the detected signal is 1001, it indicates that two channels are active, or if the detected signal is 0000, it indicates that 4 channels are active.

It is understood that S103-5 is:

the CPU210 reads the data of the electrical idle register in real time, and determines whether there is a low level signal in the data of the electrical idle register to determine whether there is at least one path in the PCIe link in a data interaction state; the electrical idle register is used for recording the states of all paths in the PCIe link.

That is, the CPU210 reads the data of the electrical idle register in real time to determine that at least one path in the PCIe link is in the data exchange state when the electrical idle register has a low level signal.

At this point, CPU210 will enable training control enable register 250, causing training control enable register 250 to write a 1, thereby enabling link training state machine 260 to perform link training.

In summary, referring to fig. 7, the initialization of the pci ephy function module and the Controller function module provided in the present application has strict requirements on the sequence and time of events. Upon receiving the first reset release signal, the CPU210 waits for 25us to reconfigure power up reset (power on reset register 240), because the PHY function module needs to wait at least 25us after the power on is stabilized, and then can release the reset (reset signal) of the PHY function module. Write app _ ltssm _ enable to 0, which means that PCIe link training state machine 260 is not enabled (when the condition is satisfied after initialization of the PCIe register is completed, app _ ltssm _ enable is enabled). The reason why the CPU210 needs to read the register configuration of the PHY function module and the Controller function module after releasing the core _ rst _ n (PCIe core reset register 230) is that after the powerreset is released, the internal of the PCIe core performs hardware reset implementation and circuit state detection, and after the condition is satisfied, the core _ rst _ n and the core _ rst _ n are released, the register configuration buses of the PCIe PHY function module and the Controller function module are activated, and then, the register configuration of the PHY function module and the Controller function module may be performed.

Then, the CPU210 starts to configure the PHY function module and the Controller function module, after all the registers are configured, the software configures app _ hold _ PHY _ rst (the common register 280) to be low level to indicate that the register configuration is completed, releases the PHY _ rst reset signal, and finally configures pipe _ laneX _ reset _ n (the channel register 290) to be high level to indicate that the reset of each channel is released, so that the PHY function module starts to operate, and then the CPU210 directly reads the electrical idle register at the receiving end of the PHY function module, and after detecting that the signal is not f (indicating that at least one PCIe channel in the link is active), the software enables app _ ltssm _ enable to enable the link training state machine 260 to start the link training.

The PCIe link training method provided by the application can enhance the robustness of the reset signal in a hardware mode, and enable different registers in a software mode according to a strict time sequence, so that the problem of link training failure in a formal link training process under various conditions is solved, and the robustness of PCIe link training is integrally enhanced.

Second embodiment

Compared with the first embodiment, the PCIe link training method provided by the embodiment of the invention enables different registers according to a strict time sequence only in a software mode, thereby avoiding the problem of link training failure in the formal link training process under various conditions and achieving the purpose of enhancing the robustness of PCIe link training.

Referring to fig. 8, the method includes:

s201, when the CPU reads the reset release signal, the power-on reset register is released through the configuration register after the preset time.

S203, when the power-on reset register is released and the CPU simultaneously reads that the value of the PCIe kernel reset register is in a high level, releasing the channel register to open all the paths in the PCIe link; wherein the lane register is electrically connected to each lane in the PCIe link.

S205, when the CPU determines that at least one path in the PCIe link is in a data interaction state, starting PCIe link training.

Meanwhile, similar to the software processing flow in the first embodiment, the end device further includes a training control enabling register and a link training state machine, the link training state machine is used for performing link training in the PCIe link, the training control enabling register is electrically connected to the link training state machine, the training control enabling register is further electrically connected to the CPU, and when the CPU determines that at least one path in the PCIe link is in the data interaction state, before the step of starting PCIe link training, the method further includes:

when the CPU determines that at least one path in the PCIe link is in a data interaction state, the CPU controls the training control enabling register to be in an enabling state so as to enable the link training state machine to be in a working state.

Further, the end device further includes an electrical idle register, the CPU is electrically connected to the electrical idle register, and before the step of initiating the PCIe link training when the CPU determines that at least one lane in the PCIe link is active, the method further includes:

the CPU reads the data of the electric idle register in real time and determines whether the data of the electric idle register has a low level signal or not so as to determine whether at least one path exists in a PCIe link and is in a data interaction state or not; the electrical idle register is used for recording the states of all paths in the PCIe link.

Further, before the step of determining whether a low signal is present in the data of the electrical idle register, the method further comprises:

and the electric idle register shifts the data corresponding to each channel and performs bitwise AND operation on the shifted data of each channel, wherein the data corresponding to the channel in the data interaction state is at a low level.

the CPU configures the common register to a low level.

Furthermore, the end device further comprises an interrupt circuit, when the PCIe is in a warm reset period, the interrupt circuit performs rising edge and falling edge generation processing and interrupt signal extraction processing on a reset signal sent by the main device to acquire the interrupt signal, and the CPU starts PCIe link training according to the interrupt signal.

Third embodiment

Referring to fig. 1, an embodiment of the present invention further provides an end device 200, where the end device 200 is configured to execute the PCIe link training method according to the first embodiment or the second embodiment.

The short shot respectively comprises a CPU210, a configuration register 220, a PCIe core reset register 230, a power-on reset register 240, a training control enabling register 250, a link training state machine 260, an appliance idle register 270, a common register 280 and a channel register 290, wherein the CPU210 is electrically connected with the configuration register 220, the PCIe core reset register 230, the power-on reset register 240, the training control enabling register 250, the appliance idle register 270, the common register 280 and the channel register 290, the configuration register 220 is electrically connected with the PCIe core reset register 230, and the training control enabling register 250 is electrically connected with the link training state machine 260.

Since the PCIe link training method has already been described in detail in the first embodiment, this embodiment is not described again.

Fourth embodiment

The embodiment of the present invention further provides a communication system, where the communication system includes a main device, a communication line, and an end device 200, the main device is in communication connection with the end device 200 through the communication line, and the end device 200 is configured to implement the PCIe link training method described in the first embodiment or the second embodiment. As can be appreciated, the communication line is a PCIe bus.

To sum up, the embodiment of the present invention provides a PCIe link training method, an end device, and a communication system, where the link training method is applied to the end device, and the end device includes a shift register and a CPU, and after receiving a first reset release signal, the shift register performs bit-wise and operation on the received reset signal to obtain a processed reset signal, and then the CPU starts PCIe link training according to the processed reset signal. Since the reset signal of the master device to the end device is the low active sideband reset signal, that is, when the signal is at low level, it indicates that the current power supply is stable. And the reset signal may have glitches and instability due to possible jitter in the circuit. After the end equipment receives the reset signal, the reset signal is operated according to the bit, and then burrs and unstable operations of the reset signal are eliminated in a hardware mode, so that the robustness of the reset signal is enhanced, and the robustness of the end equipment in a link training process is improved.

Claims

1. A PCIe link training method is applied to end equipment, the end equipment comprises a shift register, a CPU and a sampling circuit, and the method comprises the following steps: after receiving a first reset release signal, the sampling circuit samples a reset signal; the shift register performs bit AND operation on the sampled reset signal according to bytes and obtains a processed reset signal; the bit AND operation on the sampled reset signal according to bytes means that AND logic is executed between a previous period and a next period of the sampled reset signal;

and the CPU starts PCIe link training according to the processed reset signal.

2. The PCIe link training method of claim 1, wherein the end device further comprises a power-on reset register, a configuration register, a PCIe core reset register, and a channel register, the CPU is electrically connected to the power-on reset register, the configuration register, the PCIe core reset register, and the channel register, the power-on reset register is electrically connected to the configuration register, and the step of the CPU starting PCIe link training according to the processed reset signal comprises:

3. The PCIe link training method of claim 2, the end device further comprising training control enable registers and a link training state machine, the link training state machine for link training in PCIe links, the training control enable registers being electrically connected to the link training state machine, the training control enable registers being further electrically connected to the CPU, the method further comprising, prior to the step of initiating PCIe link training when the CPU determines that there is at least one lane in the PCIe link in a data interaction state:

4. The PCIe link training method of claim 2, wherein the end device further comprises an electrical idle register, the CPU is electrically connected to the electrical idle register, the method further comprises, prior to the step of initiating PCIe link training when the CPU determines that there is at least one lane in the PCIe link active, the method further comprises:

5. The PCIe link training method of claim 4, wherein prior to the step of determining whether the data of the electrical idle register has a low signal, the method further comprises:

6. The PCIe link training method of claim 2, wherein the end device further comprises a common register, prior to the step of releasing lane registers to open all lanes in the PCIe link, the method further comprising:

the CPU configures the common register to a low level.

7. The PCIe link training method of claim 1, wherein the end device further comprises an interrupt circuit, and when PCIe is in a warm reset period, the step of deriving the processed reset signal comprises:

and the CPU starts PCIe link training according to the interrupt signal.

8. A PCIe link training method is characterized in that the link training method is applied to end equipment, the end equipment further comprises a CPU, a power-on reset register, a configuration register, a PCIe kernel reset register and a channel register, the CPU is electrically connected with the power-on reset register, the configuration register, the PCIe kernel reset register and the channel register, the power-on reset register is electrically connected with the configuration register, and the method comprises the following steps:

9. An end device, characterized in that the end device is configured to implement the PCIe link training method according to any one of claims 1 to 8.

10. A communication system, comprising a main device, a communication line and an end device, wherein the main device and the end device are communicatively connected via the communication line, and the end device is configured to implement the PCIe link training method according to any one of claims 1 to 8.