CN114780143A

CN114780143A - CAN controller excitation sequence generation method and device based on UVM and verification platform

Info

Publication number: CN114780143A
Application number: CN202210443652.7A
Authority: CN
Inventors: 马盼; 倪园慧; 林子明; 靳旭; 巩京爽; 刘肖婷
Original assignee: CRSC Research and Design Institute Group Co Ltd
Current assignee: CRSC Research and Design Institute Group Co Ltd
Priority date: 2022-04-26
Filing date: 2022-04-26
Publication date: 2022-07-22

Abstract

The invention provides a method, a device and a verification platform for generating a CAN controller excitation sequence based on UVM, wherein the method comprises the following steps: creating a TLM interface data class and a frame parameter data class, instantiating the TLM interface data class and the frame parameter data class as objects, then packaging the objects as functions and tasks for CAN controller verification, combining the function to be verified of a CAN controller, randomizing the frame parameter data object, conveniently calling the functions and tasks, carrying out constraint and time sequence control on the TLM interface data object, generating an expected excitation sequence, and further generating an expected excitation sequence community to realize CAN controller application scene simulation verification. When the CAN controller verification is carried out by the excitation sequence generation device, the excitation sequence generation device does not need to be changed aiming at different CAN controller interfaces, the multiplexing of the excitation sequence generation device is realized, and the CAN controller verification efficiency CAN be improved.

Description

CAN controller excitation sequence generation method and device based on UVM and verification platform

Technical Field

The invention belongs to the field of chip verification platform structures, and particularly relates to a method and a device for generating a CAN controller excitation sequence based on UVM and a verification platform.

Background

In the development cycle of the present dedicated chip, the functional verification is a crucial flow. With the increasing complexity of chips and the ever-existing project progress pressure, research and exploration of leading-edge technologies of functional verification are always hot topics concerned in the research and development field of special chips.

The traditional functional verification technology is based on directional test written in Verilog language, a test excitation sequence is constructed one by one according to different characteristics of a design to be tested and is applied to the design to be tested, and whether the target design realizes an expected function or not is judged by adopting a mode of observing a waveform and a trace file. The Verilog language of the traditional verification technology is limited by static instantiation, dynamic transformation cannot be carried out along with simulation conditions, the constructed test excitation sequence is low in abstraction level, excessive test excitation sequences are not beneficial to project multiplexing and maintenance, the verification difficulty and workload can be multiplied along with the increase of the scale and complexity of design, and the verification process is lack of high efficiency.

In order to meet the requirement of efficient verification, a Universal Verification Methodology (UVM) based on the systemvelilog language is used as a new generation verification methodology, a formal version of the universal verification methodology is introduced by Accellera in 2011 and 2 months, the universal verification methodology absorbs the advantages of different methodologies such as ERM, AVM, VMM, OVM and the like, the universal verification methodology is popular among the public, and the current UVM standard is formulated to UVM1.2 and is declared as a formal standard by IEEE in 2017. The UVM methodology has been widely applied in the chip development industry, and provides a basic class library and a basic development framework which mainly use verification language, and the UVM self-defined framework construction class and the testing class can help a verifier to reduce the burden of environment construction, and concentrate more efforts on making a verification plan and creating an excitation sequence.

The CAN bus is one field bus, and has the advantages of high efficiency, flexibility, reliability, economy and the like, and is widely applied to the fields of industrial fields, vehicles, ships and the like. The CAN controller realizes the sending and receiving of message data conforming to the CAN bus protocol. The CAN controller is compatible with two working modes of BasicCAN and PeliCAN, a physical interface is mainly divided into a configuration interface (cfg _ interface) and a bus interface (bus _ interface), the configuration interface supports reading and writing of two modes of Intel and Motola, and the bus interface supports a CAN bus 2.0 protocol.

With the expansion of the application range of the CAN bus and the rapid development of the process technology and the chip design capability in China, the CAN controller is not only developed into a special chip, but also widely integrated in super-large-scale chips such as SOC (system on chip). The interfaces of the CAN controllers applied to different chips are different, the control modes have differences, and the CAN controllers have the characteristics that the number of internal registers is large, flexible configuration is needed in an application layer, the number of constraint conditions is large, and the requirements on universality and reusability of a constructed test scene are high in the verification process of different CAN controllers.

Disclosure of Invention

Aiming at the problems, the invention provides a UVM-based CAN controller excitation sequence generation method, a UVM-based CAN controller excitation sequence generation device and a UVM-based CAN controller excitation sequence verification platform, which CAN be suitable for simultaneously verifying a plurality of CAN controllers and CAN improve the CAN controller verification efficiency.

The invention discloses a CAN controller excitation sequence generation method based on UVM, which comprises the following steps:

creating a TLM interface data class and a frame parameter data class;

instantiating the TLM interface data class into a TLM interface data object, encapsulating the TLM interface data object into a register operation task, instantiating the frame parameter data class into a frame parameter data object, and encapsulating a parameter format conversion function;

randomizing the frame parameter data object according to a function to be verified of a CAN controller, and performing constraint and time sequence control on the TLM interface data object to generate an expected excitation sequence corresponding to the function to be verified;

organizing and coordinating a plurality of the expected excitation sequences to generate an expected excitation sequence community.

Further, the frame parameter data class is a new class defined according to the message description of the CAN bus 2.0 protocol.

Further, the frame parameter data class includes:

a data portion comprising a dynamic array, a frame format, a frame type, a frame data length, and dynamic array frame data;

a base constraint component that includes a characterization of the data component.

Further, the TLM interface data class inherits the uvm sequence item class, which includes random type read/write data, address, and read/write command parameters.

Further, the register operation tasks include:

a write operation task, a read operation task, and a bit operation task for a single register.

Further, the air conditioner is characterized in that,

and the parameter format conversion function is used for converting the internal variables of the frame parameter data objects into constraint parameters conforming to the format of a sending buffer register in the CAN controller.

Further, when the register operation task is packaged, an interface variable for transmitting the constraint parameter to the TLM interface data object is reserved.

Further, after the step of encapsulating the TLM interface data object into a register operation task, the method further includes the following steps:

according to the function to be verified of the CAN controller, logically packaging the register operation task into a verification task, wherein the verification task comprises the following steps:

the CAN controller initialization task, the CAN transmitting/receiving task and the CAN clearance task.

Further, the method for generating the expected excitation sequence corresponding to the function to be verified comprises the following steps:

randomizing the frame parameter data object according to the verification function of the CAN controller;

transmitting the randomized result to the parameter format conversion function to obtain an output constraint parameter;

transferring the constraint parameters to interface variables reserved by the register operation task;

and the register operation task restricts the TLM interface data objects, and organizes and controls the time sequence among the TLM interface data objects to obtain an expected excitation sequence corresponding to the function to be verified.

The invention also provides a device for generating the excitation sequence of the CAN controller based on the UVM, which comprises:

the creating unit is used for creating a TLM interface data class and a frame parameter data class;

the packaging unit is used for instantiating the TLM interface data class into a TLM interface data object, packaging the TLM interface data object into a register operation task, instantiating the frame parameter data class into a frame parameter data object, and packaging a parameter format conversion function;

the first generation unit is used for randomizing the frame parameter data object according to the function to be verified of the CAN controller, carrying out constraint and time sequence control on the TLM interface data object and generating an expected excitation sequence;

and the second generation unit is used for organizing and coordinating a plurality of expected excitation sequences to generate the CAN controller expected excitation sequence community.

Further, the air conditioner is characterized in that,

a base constraint portion comprising a characterization of the data portion.

Further, the first generating unit performs the following operational steps in generating the desired excitation sequence:

transmitting the constraint parameters to interface variables reserved by the register operation task;

The invention also provides a CAN controller verification platform based on UVM, which comprises the excitation sequence generation device.

According to the method for generating the excitation sequence of the CAN controller based on the UVM, the TLM interface data class and the frame parameter data class are created and instantiated into objects, and then the objects are packaged into functions and tasks for CAN controller verification, so that the frame parameter data objects CAN be randomized by combining functions to be verified of the CAN controller, the functions and the tasks packaged in advance CAN be conveniently called, the TLM interface data objects are subjected to constraint and time sequence control, an expected excitation sequence is generated, and an expected excitation sequence community is further generated to realize CAN controller application scene simulation verification. The method comprises the steps of creating a TLM interface data class and a frame parameter data class, instantiating the TLM interface data class and the frame parameter data class as objects, and then packaging the objects into functions and tasks for CAN controller verification, so that the generation efficiency of an excitation sequence during CAN controller verification CAN be effectively improved, and the error risk is reduced.

According to the excitation sequence generation device and the verification platform, the method for generating the excitation sequence of the CAN controller is realized, when the CAN controller is verified, only the bottom driver component is modified according to the corresponding physical interface protocol aiming at different CAN controller interfaces, and the structure of the excitation sequence generation device is not required to be changed. The second generation unit of the excitation sequence generation device CAN organize and coordinate a plurality of expected excitation sequences and generate an expected excitation sequence community to realize the verification of a plurality of CAN controllers at the same time.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

FIG. 1 shows a flow chart of a UVM based CAN controller excitation sequence generation method of the present invention;

FIG. 2 shows a schematic diagram of a UVM-based CAN controller excitation sequence generation apparatus according to the present invention;

FIG. 3 illustrates a UVM based CAN controller verification platform data invocation/transmission diagram according to the present invention;

FIG. 4 illustrates an inheritance relationship between classes in a UVM-based CAN controller excitation sequence generation apparatus according to the present invention;

FIG. 5 shows a schematic block diagram of a UVM based CAN controller authentication platform according to the present invention;

FIG. 6 illustrates one of the flow diagrams of the authentication process for a UVM based CAN controller authentication platform in accordance with the present invention;

fig. 7 is a schematic diagram illustrating a message structure received and transmitted by a CAN controller in an embodiment of the present invention;

fig. 8 shows a second flowchart of the authentication process of the UVM-based CAN controller authentication platform according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

The Systemverilog verification language has language characteristics of constraint, multi-thread communication, object-oriented programming and the like, and can build a higher hierarchical structure and generate constrained random excitation. And the UVM verification methodology based on Systemverilog provides a basic class library and a basic development framework which take verification language as a main body, and the UVM self-defined framework construction class and the test class can help a verifier to reduce the burden of environment construction, so that more efforts are focused on making a verification plan and creating an incentive sequence.

The invention adopts the excitation sequence structure built by the technology, and CAN drive different CAN controller physical interfaces under the condition of not modifying an excitation sequence generating device. The hierarchical structure of the excitation sequence generation device is high, each hierarchical structure has reasonable granularity, and horizontal multiplexing and vertical multiplexing of a test scene are met. The constrained random excitation sequence generated in the verification process CAN meet the requirement of realizing full coverage of the function points while the CAN controller to be tested is driven correctly, and the verification efficiency is improved. The defects that the directional excitation sequence written by the Verilog language in the traditional verification technology is limited by static instantiation, cannot be dynamically changed along with the simulation condition and is poor in maintainability and reusability are overcome. The verification platform CAN instantiate a plurality of CAN controllers at the same time, so that the verification efficiency is greatly improved.

Description of related terms: the uvm sequence class and uvm sequence item class are basic classes in uvm methodology.

Referring to fig. 1, a specific implementation process of the method for generating the excitation sequence of the UVM-based CAN controller of the present invention is as follows:

creating a TLM interface data class and a frame parameter data class;

instantiating a TLM interface data class and a frame parameter data class as objects; packaging the TLM interface data object into a register operation task, and packaging a parameter format conversion function for the frame parameter data object;

randomizing a frame parameter data object according to a function to be verified of the CAN controller, and calling a register operation task and a parameter format conversion function to perform constraint and time sequence control on the TLM interface data object to generate an expected excitation sequence corresponding to the function to be verified;

and finally, organizing and coordinating a plurality of expected excitation sequences to generate an expected excitation sequence community according to specific verification contents.

Referring to fig. 2, the present invention also provides a UVM-based CAN controller excitation sequence generation apparatus, including:

the packaging unit is used for instantiating the TLM interface data into TLM interface data objects, packaging the TLM interface data into register operation tasks, instantiating the frame parameter data into frame parameter data objects, and packaging parameter format conversion functions;

the first generation unit is used for randomizing the frame parameter data object according to the function to be verified of the CAN controller, calling a register operation task and a parameter format conversion function to carry out constraint and time sequence control on the TLM interface data object and generating an expected excitation sequence corresponding to the function to be verified;

and the second generation unit is used for organizing and coordinating a plurality of expected excitation sequences to generate an expected excitation sequence community.

Fig. 3 shows a connection transmission structure of the excitation sequence generating apparatus of the CAN controller based on UVM, the verification platform assembly and the design to be tested.

Referring to fig. 3, in an embodiment of the present invention, the excitation sequence generation apparatus is divided into four levels: basic data, unit sequences, constraint sequences, and virtualization sequences. The hierarchical inheritance relationships are shown in fig. 4. Data call relations exist among all levels in the excitation sequence generation device, data transmission relations exist among verification components, the verification components are generic names of modules used for achieving simulation verification of the design to be tested in the verification platform, and arrows in different forms are adopted for distinguishing and representing in the figure 3.

As shown in FIG. 3, the TLM interface data class and the frame parameter data class constitute the base data hierarchy as shown in FIG. 3; the register operation tasks and the parameter format conversion functions constitute a hierarchy of cell sequences as shown in fig. 3.

For the simulation verification of the CAN controller, three common operations to be executed in the process of verifying the CAN controller, namely initialization configuration, data transmission and data reception, are given, three expected excitation sequences, namely an initialization configuration sequence, a data transmission sequence and a data reception sequence, are correspondingly generated, and a constraint sequence hierarchy as shown in fig. 3 is formed. Each desired excitation sequence in the hierarchy of constraint sequences may be referred to as a constraint sequence.

It should be understood that the three expected excitation sequences given in this embodiment are commonly used in the CAN controller verification process, and may be specifically supplemented in the constraint sequence hierarchy according to the actual verification process.

For specific verification content of the CAN controller, organizing and coordinating a plurality of expected excitation sequences to generate an expected excitation sequence community, for example, when verifying a normal transceiving message of the CAN controller, invoking an initialization configuration sequence, a data transmission sequence and a data reception sequence in a constraint sequence hierarchy to organize, and generating a normal transceiving sequence (community), as shown in fig. 3, further enumerating an error sequence (community) and an arbitration sequence (community) as examples, the expected excitation sequence communities form a virtualization sequence hierarchy as shown in fig. 3, and each sequence (expected excitation sequence community) in the virtualization sequence hierarchy may be referred to as a virtualization sequence.

In one embodiment of the invention, the register operation task and the parameter format conversion function are tasks and functions with higher frequency in the process of verifying the CAN controller, and the operation step of pre-packaging the target function and the tasks CAN greatly improve the efficiency of verifying the CAN controller in the process of verifying a large number of CAN controllers.

Referring to fig. 4, for explaining an inheritance relationship between each hierarchy in an embodiment of the excitation sequence generation apparatus of the present invention, a unit sequence inherits a uvm sequence class, a constraint sequence inherits a unit sequence, and a virtualization sequence inherits a uvm sequence class.

In the invention, TLM interface data class and frame parameter data class are established to form the basic data hierarchy, which takes the transmission characteristics of the verification component and the CAN bus protocol characteristics into consideration, and the proper bottom layer minimum granularity CAN improve the generation efficiency of the excitation sequence in the process of generating the excitation sequence of the CAN controller.

The CAN controller is mainly driven through a configuration register, so that the TLM interface data class inherits the uvm sequence item class, comprises random type read/write data, addresses and read/write command parameters, and CAN be used for communication among all verification components in the verification platform through the TLM interface.

The frame parameter data class is a new class defined according to the message description of the CAN bus 2.0 protocol, is not a legacy UVM base library class, and is a targeted design made according to the scene actually applied to CAN controller verification according to the present invention, a specific frame structure is shown in fig. 7, and the frame parameter data class includes:

the data part comprises a dynamic array ID, a frame format FF, a frame type RTR, a frame data length DLC and dynamic array frame data;

a base constraint part including a feature description of the data part; for example: the DLC has a numerical range of 0-8 bytes, which is the clear characteristic description of DLC.

The frame parameter data class is mainly used for constructing a (desired) excitation sequence after configuring or randomizing data portions in a frame parameter data object, and is explained below by taking the generation of a data transmission sequence as an example:

randomizing a frame parameter data object according to a function to be verified (data transmission function) of the CAN controller;

and after the randomized result is transferred to a parameter format conversion function for processing, a constraint parameter is output, and then a CAN sending task is called to construct a data sending sequence according to the constraint parameter.

Referring to fig. 3, a sequence (e.g., a normal transceiving sequence, an arbitration sequence, etc.) in a virtualization sequence level organizes a data transmission sequence to be driven to a CAN controller by a cfg _ agent (configured agent container) in a verification component, and when the data transmission function of the CAN controller is normal, a bus end of the CAN controller sends a corresponding message conforming to a 2.0 protocol of a CAN bus after receiving the data transmission sequence, so as to verify the data transmission function of the CAN controller.

Referring to fig. 3, interface variables for external randomization are reserved when register operation tasks and parameter format conversion functions are declared, the interface variables of the register operation tasks control randomization of TLM interface data objects through constraint parameters transmitted from a previous layer, and excitation sequence single functions are realized by organizing and performing timing control on the register operation tasks.

Specifically, the process steps for generating a desired excitation sequence are:

randomizing a frame parameter data object according to a function to be verified of the CAN controller;

transmitting the randomized result to a parameter format conversion function and then acquiring an output constraint parameter;

and the register operation task restricts TLM interface data objects, and organizes and controls the time sequence among a plurality of TLM interface data objects to realize generation of an excitation sequence.

Specifically, the register operation tasks include: and performing a writing operation task, a reading operation task and a bit operation task on a single register. By encapsulating the single register write operation task and the read operation task again, the single register bit operation task can be realized, namely, the current value of the register is read firstly, then the appointed bit of the read value is modified according to the configuration requirement, and finally the modified value is written back to the register.

Further, the external interface variables reserved by the register operation task are address variables and data variables, the address of the TLM interface data object and the read/write command parameters are specifically assigned by using a' UVM _ do _ with macro in the UVM sequence mechanism, and in the register read operation task, a get _ response task is also required to be called to obtain valid read data transmitted by a driver in the verification component.

In order to facilitate repeated calling, the operation of the registers CAN be further used as basic tasks to carry out multiple packaging, and more tasks are constructed according to the actual configuration of the CAN controller. For example, according to the to-be-verified function of the CAN controller, the register operation task is logically encapsulated again, and is encapsulated into a verification task that CAN implement a relatively complex task, as shown in fig. 3, the verification task in this embodiment includes: the CAN controller initialization task, the CAN transmitting/receiving task and the CAN clearance task. Multiplexing (functions and tasks) in the vertical direction as shown in fig. 3 can be realized.

Specifically, in this embodiment, the CAN controller initialization task includes: and respectively carrying out corresponding register bit operation and register write operation on the mode register, the clock frequency division register, the acceptance filter, the bus timing register and the output filter.

The CAN controller sends/receives tasks by continuously reading states, monitoring the register and circularly calling the write operation or the read operation of the register to the corresponding register address when the states are met so as to send or receive frame data.

The interface variable preserved by the parameter format conversion function is input as a frame parameter data object of a basic data level and output as a format array conforming to an internal sending buffer of the CAN controller, so that the frame parameter is converted into specified format data through the parameter format conversion function.

As shown in fig. 3, in this embodiment, the initial configuration sequence in the constraint sequence hierarchy is specifically configured by presetting parameters such as a single/dual filter, a baud rate, an acceptance code register, and an acceptance mask register, then calling a CAN controller initialization task in the parent unit sequence hierarchy, and finally calling a register bit operation task to start an interrupt register and switch modes according to requirements of a test scenario of the CAN controller.

As shown in fig. 3, the data sending sequence in the constraint sequence hierarchy is to specifically utilize randomize () with a statement to constrain and randomize the frame parameter data object, then call a parent function (a parameter format conversion function in the unit sequence hierarchy) to perform parameter format conversion, and transfer the output constraint parameter to the CAN sending task, and the CAN sending task writes the specific content of the message into a sending buffer inside the CAN controller according to the constraint parameter. By using the same structure, the data transmission sequences of different message types and message formats CAN be obtained only by changing the constraint configuration of the data part in the frame parameter data object, so that the bus end of the CAN controller CAN transmit different types of messages. The constraint configuration is to specifically configure the data part on the basis of the feature description conforming to the basic constraint part, and the range of the basic constraint part is not exceeded.

And the data receiving sequence in the constraint sequence level relatively simply calls a CAN receiving task to wait for receiving a frame of message data and then calls a reading register task to receive and clear the interrupt.

The virtualized sequence inherits the uvm sequence class;

the virtualization sequence bears and coordinates a plurality of constraint sequences, generates an expected excitation sequence community to realize synchronous verification of a plurality of CAN controllers, and specifically comprises the following steps:

creating a p _ sequence variable using the macro uvm _ detail _ p _ sequence;

indexing into each sequence handle declared in can _ virtual _ sequence by p _ sequence;

and (4) respectively mounting each constraint sequence to a corresponding sequence of the corresponding CAN controller through the macro uvm _ do _ on.

"UVM _ detail _ p _ sequence and" UVM _ do _ on are macros in the UVM verification methodology.

As shown in fig. 3, the virtualization sequence is carried as a top-level excitation sequence and coordinates a constraint sequence of each CAN controller (corresponding to the function to be verified of each CAN controller), thereby implementing a complete test scenario.

The excitation sequence generation device provided by the invention enables four hierarchical structures of the excitation sequence to have reasonable granularity, nesting is realized layer by layer, the excitation sequence generation efficiency is improved through reasonable division, and horizontal multiplexing is realized.

For different test scenes, namely, when different functions of the CAN controller are verified, different test purposes CAN be achieved only by changing the limiting conditions of the constraint sequences and the coordination sequence of the virtualization sequences, and vertical multiplexing is achieved.

In the invention, horizontal multiplexing refers to how to utilize the existing resources to complete efficient excitation sequence creation; vertical multiplexing includes the possibility of performing both structural multiplexing and excitation sequence multiplexing.

According to fig. 3, the cfg _ agent (configuration agent container) in the verification component communicates with the dut (device Under test) to be designed through the cfg _ interface (configuration interface);

each CAN controller corresponds to one authentication component cfg _ agent. The can _ virtual _ sequence bridges the UVM stimulus sequence community and multiple cfg _ agents, and can _ virtual _ sequence internally contains sequence (sequencer) handles that interface with cfg _ agent underlying sequence component objects. The virtualization sequences carry constraint sequence communities of different target sequences, and the constraint sequences can be distributed to corresponding sequence assemblies through can _ virtual _ sequence routing.

The cfg _ agent comprises a sequence and a driver, wherein the sequence and the driver in the cfg _ agent realize mutual communication by adopting a bidirectional interface, the sequence starts register operation tasks in the unit sequence one by one according to the setting sequence and the constraint conditions of the distributed constraint sequence, the register operation tasks can generate a target number of randomized TLM interface data objects, and the randomized TLM interface data objects flow to the driver through the TLM interface.

And the driver analyzes the randomized TLM interface data object and drives the data object to the interface according to a physical interface protocol of the CAN controller, so as to effectively excite the design to be tested. That is, the excitation sequence generated by the excitation sequence generating means is transmitted to the driver through the sequence r, and the driver drives the DUT.

Further, in order to read the value of a certain register in the CAN controller in the unit sequence, the driver CAN write the state and data information in the design to be tested back to the unit sequence object through the sequence, so that the unit sequence CAN obtain the state of interaction between the driver and the DUT.

According to the CAN controller verification platform, the excitation sequence generation device is adopted, aiming at different CAN controller interfaces, only the bottom driver component needs to be modified according to the corresponding physical interface protocol, and the excitation sequence generation device does not need to be changed, so that the excitation sequence generation efficiency is improved, and the verification efficiency of the CAN controller is improved.

Referring to fig. 5, according to an embodiment of the present invention, a UVM-based CAN controller verification platform tests a top layer (testbench) instantiates a plurality of DUTs (corresponding to CAN _ n in fig. 5), a configuration interface cfg _ interface, a bus interface bus _ interface, and a CAN transceiver model (CAN transceiver model), and enters a test layer configuration verification component and calls an excitation sequence by calling run _ test (excitation sequence name) in a process statement.

The device is designed as a CAN controller, the cfg _ interface comprises addresses, data and control signals related to DUT configuration, and the bus _ interface comprises DUT bus input signals and output signals.

In the present invention, the CAN transceiver model has the main functions of: simulating a CAN Bus physical layer, and converting Bus logic signals of a plurality of controllers into a differential transmission mode;

in the verification process, the bus _ interface can be used for forcibly assigning values at specific bits of the bus, so that the purpose of inserting bus errors is achieved.

In one embodiment of the invention, as shown in FIG. 5, uvm _ test is used to configure the verification environment and connection relationships and to decide which test stimulus sequence to invoke, as shown in FIG. 5, uvm _ test includes uvm sequence, can _ virtual _ sequence and env.

The uvm sequence is an excitation sequence generating device of the present invention, and is used for generating an excitation sequence, the generated excitation sequence is processed by a virtual sequence management module (can _ virtual _ sequence) and then transmitted to env (verification environment), and the env mainly includes an agent (agent), a coverage collection module (coverage) and a score board (scoreboard) as a container package. The components communicate with each other based on a TLM (Transaction Level Modeling) communication mechanism.

The agent (agent) comprises a cfg _ agent and a bus _ agent which both inherit uvm _ agent classes, wherein the cfg _ agent comprises a sequence and a driver, and is mainly used for driving and monitoring the cfg _ interface and transmitting signals with a DUT (device under test) through the cfg _ interface; the bus _ agent is a bus agent encapsulated with a bus _ monitor, and mainly monitors a bus interface.

A Monitor in the cfg _ agent is responsible for monitoring configuration signals and interrupt signals of a DUT (device under test), when the DUT initiates an interrupt, the Monitor restarts an excitation sequence, the excitation sequence is transmitted to a driver again through a sequence, the driver drives the DUT, and the Monitor converts the configuration signals sampled by monitoring into TLM interface data objects which are transmitted to a coverage component and a scoreboard component respectively. The bus _ agent is not used for driving the DUT but for monitoring the bus signal, so only a bus _ monitor component is instantiated inside the bus _ agent, the bus _ agent collects the output signal of the CAN transceiver model through the bus interface (corresponding to RX in fig. 5, TX in fig. 5 is sending a signal to the CAN transceiver model), analyzes the bus signal according to the frame format in the CAN bus protocol, converts the bus signal into a TLM interface data object, and transmits the TLM interface data object to the scoreboard.

The Scoreboard (score board) is used for comparing and analyzing the acquired actual data and the reference data to obtain a verification result, and the Scoreboard data sources are mainly divided into three types, namely, a sending end DUTTLM interface data object transmitted by the cfg _ agent, a receiving end DUT TLM interface data object transmitted by the cfg _ agent and a bus TLM interface data object transmitted by the bus _ agent. Comparing the multi-party data to obtain a comparison result and reporting, and when the comparison result is used for performing function verification on the CAN controller, obtaining a report of whether the verification is successful according to the comparison result, which is shown in a flowchart in fig. 6.

The Coverage collection module Coverage is used for collecting the Coverage condition of TLM interface data objects of a DUT sending end and a DUT receiving end.

As shown in fig. 6, a specific flowchart of the simulation verification of the CAN controller based on the verification platform of the present invention is given.

The simulation verification principle is as follows: firstly, each module of the verification platform is instantiated, and a UVM excitation sequence generation device is started to be configured to a virtual sequence. And then distributing the unit sequence TLM interface data object generated by randomization to the sequence of each cfg _ agent according to the setting of the excitation sequence, transmitting the data object to the driver by the sequence, transmitting the signal to an internal register of each DUT by the driver through the cfg _ interface, simultaneously acquiring effective data by a monitor in the cfg _ agent through the cfg _ interface, converting the signal into the TLM interface data object, and respectively transmitting the TLM interface data object to the scoreboard and the coverage.

Referring to fig. 6, at the beginning of verification, each DUT and verification component is instantiated first, and then each hierarchical sequence in the excitation sequence generation apparatus of the present invention is instantiated to generate an excitation sequence; the generated excitation sequence is transmitted to the driver through the sequence r, and then the driver sends signals to the internal registers of the DUTs through the cfg _ interface. As shown in fig. 6, two CAN controllers (CAN _1 and CAN _ 2) to be tested are taken as an example to perform the verification of the received and transmitted message: under a normal working mode, CAN _1 sends a message to a Bus, when CAN _2 detects that the Bus has the message, the message is identified and screened, the message is received after data screening, data reading is carried out through cfg _ interface, finally, the sending end data (corresponding to monitor sampling CAN _1 configuration interface in figure 6), the receiving end data (corresponding to monitor sampling CAN _2 configuration interface in figure 6) of cfg _ interface and the Bus data (corresponding to Bus _ monitor sampling message data in figure 6) of Bus _ interface are compared in scoreboard, coverage rate statistics is carried out after comparison is successful, the reason is checked and modified if comparison is unsuccessful, and re-verification is carried out after modification is finished. And when the data comparison result is that the data are consistent, the comparison is judged to be successful, otherwise, the comparison is judged to be failed. In this embodiment, the message sending function of the CAN _1 controller is verified, and the message receiving function of the CAN _2 controller is verified, that is, the two CAN controllers are verified.

The design to be tested is a CAN controller, and is compatible with two working modes of BasicCAN and PeliCAN, the physical interface is mainly divided into a configuration interface and a bus interface, the configuration interface supports reading and writing of two modes of Intel and Motola, and the bus interface supports CAN bus 2.0 protocol.

According to the CAN bus 2.0 protocol standard, the CAN controller CAN receive and transmit 4 types of messages including data frames, remote frames, error frames and overload frames, wherein the data frames and the remote frames respectively have two formats, namely a standard frame format and an extended frame format, and the structures of the message types and the message formats are shown in fig. 7.

Referring to fig. 7, the remote frame does not contain a data field, and the rest is the same as the data frame structure.

On the CAN bus, frame intervals of continuous recessive bits are inserted between two frames, and the beginning of the frame is formed by a dominant bit;

the arbitration field is composed of an ID code and a plurality of flag bits, wherein a remote frame flag bit (RTR) is used for marking the frame type as a data frame or a remote frame; the main difference between the standard frame format, which has no IDE bits in the arbitration field and has 11 bits, and the extended frame format, which has a value of 1 IDE bits and has a 29-bit ID code, is the IDE flag bit and ID code length of the arbitration field.

The control fields of the standard frame format and the extended frame format each include 4-bit data long multi-code (DLC), wherein the control field of the standard frame format has IDE (value 0) bits and reserved bits r0, and the control field of the extended frame format has two reserved bits r0 and r 1.

The standard frame format and the extended frame format can only transmit 0-8 bytes of data in a data field. The CRC field includes a 15-bit CRC sequence and a 1-bit implicit CRC delimiter. The acknowledgement field (ACK field) contains the acknowledgement slot and the acknowledgement delimiter, followed by the end of frame consisting of 7 recessive bits, indicating the end of a frame message.

The frame parameter data class in the base data hierarchy is a new class defined by the message description according to the protocol described above.

The data part of the type is parameter data designed aiming at code bits and flag bits of each field in the message format, and comprises dynamic array ID, frame format FF, frame type RTR, frame data length DLC and dynamic array frame data.

The basic constraint part of the class describes the defined parameter data according to the message type, wherein one frame of a data field can only transmit 0-8 characters, so the numerical range of DLC is 0-8 bytes, and DLC determines the width of a frame data dynamic array. Similarly, the width of the dynamic array ID depends on the frame format FF, and the ID array width is 4 when FF is the extended frame format and 2 when FF is the standard frame format. This allows generation of parametric data conforming to the protocol description when randomizing the frame parametric data object in a constrained sequence.

The frame parameter data class is defined as a new class directly according to the message description of the CAN bus 2.0 protocol, so that the generation efficiency of the excitation sequence in the verification process of the CAN controller is greatly improved, and the reuse rate of the verification component is improved.

Referring to fig. 3, unlike the existing CAN verification method, the verification method of the present invention simulates a real communication scenario, and connects at least two CAN controllers (corresponding to CAN _ n in fig. 3) of the design under test to the same CAN BUS (CAN BUS) through a CAN transceiver model (not shown in fig. 3).

Taking the example that two nodes of the CAN controller are connected with the same bus, the specific verification process of the CAN controller is as follows: one CAN controller is used as a sending end, and the other CAN controllers are used as receiving ends to simultaneously carry out sending verification and receiving verification. The advantage of this design is that multiple CAN controllers CAN be transceive verified without writing a complex CAN verification model.

Further, referring to fig. 8, as an excitation sequence generation procedure of a normal transceiving sequence in the virtualization sequence in fig. 3, starting from each level sequence of the instantiated excitation sequence generation device, entering a reset mode, invoking a constraint sequence to initialize and configure CAN _1 and CAN _2, respectively, and configuring respective acceptance filter IDs for subsequent transceiving data for CAN _1 and CAN _ 2.

After entering a working mode (carrying out transceiving verification on a CAN controller), configuring CAN _1 to send data, when data are transmitted on a bus, analyzing the bus data through CAN _2 to extract ID, comparing the ID with the ID in an acceptance filter which is initially configured, if the data are valid frames, carrying out data receiving on CAN _2, reading a message from a receiving buffer, and otherwise, discarding the message.

The process of sending and receiving a frame of message is completed, and the process CAN configure effective cycle times in a virtualization sequence to carry out multiple receiving and sending among CAN controllers.

For different test scenarios, such as the arbitration sequences listed in the virtualization sequence in fig. 3, the purpose of testing the bus arbitration of the CAN controller CAN be achieved by only changing the coordination sequence and configuring both the CAN1 and the CAN2 as transmitting ends so that the two DUTs CAN transmit data at the same time. And the error sequences listed in the virtualization sequence are inserted into bus errors by using the CAN transceiver model on the basis of the normal transceiving sequence, so that the error types such as bit errors, format errors and the like of the CAN controller CAN be tested.

Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A UVM-based CAN controller excitation sequence generation method is characterized by comprising the following steps:

creating a TLM interface data class and a frame parameter data class;

randomizing the frame parameter data object according to a function to be verified of the CAN controller, and performing constraint and time sequence control on the TLM interface data object to generate an expected excitation sequence corresponding to the function to be verified;

and organizing and coordinating a plurality of expected excitation sequences to generate an expected excitation sequence community.

2. The UVM-based CAN controller stimulus sequence generation method of claim 1, wherein the frame parameter data class is a new class defined according to a message description of CAN bus 2.0 protocol.

3. The UVM-based CAN controller excitation sequence generation method of claim 2, wherein the frame parameter data class includes:

a base constraint portion comprising a characterization of the data portion.

4. The UVM-based CAN controller stimulus sequence generation method of claim 1, wherein the TLM interface data class inherits a uvmsequenceitemem class, including random type read/write data, addresses, and read/write command parameters.

5. The UVM-based CAN controller excitation sequence generation method of claim 1, wherein the register operation task includes:

6. The UVM-based CAN controller excitation sequence generation method of any one of claims 1 to 5,

7. The UVM-based CAN controller excitation sequence generation method of claim 6, wherein interface variables that pass the constraint parameters to the TLM interface data object are reserved when encapsulating the register operation task.

8. The UVM-based CAN controller stimulus sequence generation method of claim 7, further comprising, after the step of encapsulating the TLM interface data object into register manipulation tasks, the steps of:

the CAN controller initializes tasks, CAN transmitting/receiving tasks and CAN clearing and interrupting tasks.

9. The UVM-based CAN controller excitation sequence generation method according to claim 7 or 8, wherein the method of generating a desired excitation sequence corresponding to the function to be verified includes the steps of:

10. A UVM-based CAN controller excitation sequence generation apparatus, comprising:

the first generation unit is used for randomizing the frame parameter data object according to the function to be verified of the CAN controller, and carrying out constraint and time sequence control on the TLM interface data object to generate an expected excitation sequence;

11. The UVM-based CAN controller excitation sequence generating apparatus of claim 10, wherein the frame parameter data class is a new class defined according to a message description of CAN bus 2.0 protocol.

12. The UVM-based CAN controller excitation sequence generation apparatus of claim 11,

13. The UVM-based CAN controller excitation sequence generation apparatus of claim 10, wherein the first generation unit performs the following operational steps in generating a desired excitation sequence:

14. A UVM-based CAN controller verification platform comprising the excitation sequence generation apparatus of any one of claims 10 to 13.