CN114765528B - Frame synchronization method, device, equipment and readable storage medium - Google Patents
Frame synchronization method, device, equipment and readable storage medium Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0062—Network aspects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0062—Network aspects
- H04Q11/0067—Provisions for optical access or distribution networks, e.g. Gigabit Ethernet Passive Optical Network (GE-PON), ATM-based Passive Optical Network (A-PON), PON-Ring
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Abstract
The invention provides a frame synchronization method, a device, equipment and a readable storage medium. The method comprises the following steps: when the frame synchronization state machine is in a search state, determining a target sequence from a received bit stream, and controlling the frame synchronization state machine to enter a presynchronization state, wherein the unmatched part of the target sequence is smaller than or equal to N bits compared with a standard physical synchronization sequence, and N is a positive integer; extracting a physical frame corresponding to the target sequence from the bit stream; performing Forward Error Correction (FEC) processing on the physical frame, and obtaining a physical frame payload of the physical frame when the FEC processing is successful; detecting whether the data of the physical frame payload is correct; if the result is correct, the control frame synchronization state machine enters a synchronization state, otherwise, the control frame synchronization state machine returns to a search state. Compared with the prior art, the invention can enable the frame synchronization state machine to enter the synchronization state more quickly.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a frame synchronization method, apparatus, device, and readable storage medium.
Background
In the passive optical network PON (Passive Optical Network) system, the optical line terminal OLT (Optical Line Termination), the optical distribution network ODN (Optical Distribution Network), and the optical network unit ONU (Optical Network Unit) are commonly configured to carry traffic. Frame synchronization is needed between OLT and ONU to correctly assemble the carried traffic from the physical stream. The physical bit stream of the PON system divides physical frames according to 125 microseconds, and the frame structure of the physical frames is composed of physical synchronization blocks PSBd and physical frame payloads as shown in fig. 1. The realization of synchronization of physical frames from physical streams is a key technology for realizing service bearing.
The physical frame synchronization of the existing PON system is performed by a frame synchronization state machine, and the states of the frame synchronization state machine are four: search state (Hunt), presynchronization state (Pre-Sync), synchronization state (Sync), and resynchronization state (Re-Sync). As shown in fig. 2, fig. 2 is a state transition diagram of a frame synchronization state machine. The PON system enables the frame synchronization state machine to operate and maintain in a synchronization state according to the physical flow condition, and in this state, the physical frame can be unpacked into a service data unit, and the service bearer of the user is extracted. Specifically, when the frame synchronization state machine of the receiving end in the PON system is in the search state, if the receiving end searches a part of bit stream consistent with the standard physical synchronization sequence 0xC5E51840FD59BB49 from the received physical bit stream, the frame synchronization state machine is controlled to enter a pre-synchronization state, and the part of bit stream is used as a frame header of a physical frame, and in combination with a rule of dividing the physical frame by 125 microseconds, each physical frame is separated from the physical bit stream, and then it is verified whether data in a downlink physical synchronization block PSBd (Physical Synchronization Block, downlink stream) in a frame structure of a plurality of physical frames are correct, if data in PSBd in a frame structure of a plurality of physical frames are correct, the frame synchronization state machine is controlled to enter a synchronization state, thereby decapsulating the physical frame into a service data unit, and extracting service bearers of users.
However, when the network environment is bad or in a high-speed PON system, there is a high error rate of the optical fiber line. In this case, it is difficult for the receiving end to search for a partial bitstream consistent with the standard physical synchronization sequence 0xC5E51840FD59BB49 from the received physical bitstream, resulting in difficulty in the frame synchronization state machine entering the pre-synchronization state, and thus, it is impossible to extract a physical frame from the physical stream. And even if the frame synchronization state machine enters a pre-synchronization state, due to the fact that a high error rate exists in the optical fiber line, it is difficult to ensure that data in PSBd in a frame structure of a plurality of physical frames are correct, so that the frame synchronization state machine is difficult to enter the synchronization state, and finally the physical frames cannot be unpacked into service data units, and service bearing transmission cannot be carried out.
Disclosure of Invention
In order to solve the technical problems, the invention provides a frame synchronization method, a device, equipment and a readable storage medium.
In a first aspect, the present invention provides a frame synchronization method, including:
when the frame synchronization state machine is in a search state, determining a target sequence from a received bit stream, and controlling the frame synchronization state machine to enter a presynchronization state, wherein the unmatched part of the target sequence is smaller than or equal to N bits compared with a standard physical synchronization sequence, and N is a positive integer;
Extracting a physical frame corresponding to the target sequence from the bit stream;
performing Forward Error Correction (FEC) processing on the physical frame, and obtaining a physical frame payload of the physical frame when the FEC processing is successful;
detecting whether the data of the physical frame payload is correct;
if the result is correct, the control frame synchronization state machine enters a synchronization state, otherwise, the control frame synchronization state machine returns to a search state.
Optionally, when the target sequence is completely matched with the standard physical synchronization sequence, after the step of extracting the physical frame corresponding to the target sequence from the bitstream, the method further includes:
performing HEC verification on synchronous information protected by hybrid error correction HEC codes in a physical synchronous block PSBd of the physical frame;
and if the verification is passed, controlling the frame synchronization state machine to enter a synchronization state.
Optionally, the step of detecting whether the data of the physical frame payload is correct includes:
performing hybrid error correction HEC verification on data in a frame header of the physical frame payload;
if the verification is passed, determining that the data of the physical frame payload is correct;
if the test is not passed, determining that the data of the physical frame payload is incorrect.
Optionally, the step of detecting whether the data of the physical frame payload is correct includes:
Performing bit interleaved parity check on data in the frame tail of the physical frame payload;
if the verification is passed, determining that the data of the physical frame payload is correct;
if the test is not passed, determining that the data of the physical frame payload is incorrect.
Optionally, the step of detecting whether the data of the physical frame payload is correct includes:
detecting whether a value in a specific field of the physical frame payload is a preset value;
if yes, determining that the data of the physical frame payload is correct;
if not, determining that the data of the physical frame payload is incorrect.
Optionally, the specific field is a bandwidth map BWmap field, and the preset value is an Allocation structure.
Optionally, the specific field is a physical layer operation maintenance management PLOAM field, and the preset value is a PLOAM message undefined in a PON system protocol of the passive optical network.
Optionally, after the step of controlling the frame synchronization state machine to enter the synchronization state, the method further includes:
when a physical frame with errors is extracted from the bit stream, controlling a frame synchronization state machine to enter a resynchronization state, wherein:
if the data corresponding to the physical synchronization domain Psync of the physical frame is greater than N bits compared with the standard physical synchronization sequence, the physical frame is a faulty physical frame;
Or if the Forward Error Correction (FEC) processing is carried out on the physical frame and the FEC processing fails, the physical frame is a physical frame with errors;
or if HEC verification is carried out on the synchronous information protected by the hybrid error correction HEC code in the physical synchronous block PSBd of the physical frame and the verification is not passed, the physical frame is a physical frame with errors;
or if the data of the physical frame payload of the physical frame is incorrect, the physical frame is a physical frame with errors.
Optionally, after the step of controlling the frame synchronization state machine to enter the resynchronization state, the method further includes:
and when the frame synchronization state machine is in a resynchronization state, performing decapsulation processing on the extracted physical frame.
Optionally, after the step of controlling the frame synchronization state machine to enter the resynchronization state, the method further includes:
when a new physical frame with errors is extracted from the bit stream, the frame synchronization state machine is controlled to enter a search state.
Optionally, after the step of controlling the frame synchronization state machine to enter the resynchronization state, the method further includes:
when an error-free physical frame is extracted from the bit stream, controlling a frame synchronization state machine to enter a synchronization state, wherein:
if the data corresponding to the physical synchronization domain Psync of the physical frame is smaller than or equal to N bits compared with the standard physical synchronization sequence, and/or the forward error correction FEC processing is performed on the physical frame, and the FEC processing is successful, and/or the HEC check is performed on the synchronization information protected by the hybrid error correction HEC code in the physical synchronization block PSBd of the physical frame, and the check passes, and/or the data of the physical frame payload of the physical frame is correct, the physical frame is an error-free physical frame.
In a second aspect, the present invention also provides a frame synchronization device, including:
the state switching module is used for determining a target sequence from a received bit stream when the frame synchronization state machine is in a search state, and controlling the frame synchronization state machine to enter a presynchronization state, wherein the unmatched part of the target sequence is smaller than or equal to N bits compared with a standard physical synchronization sequence, and N is a positive integer;
an extracting module, configured to extract a physical frame corresponding to the target sequence from the bitstream;
the FEC processing module is used for performing Forward Error Correction (FEC) processing on the physical frame, and obtaining the physical frame payload of the physical frame when the FEC processing is successful;
a detection module, configured to detect whether data of the physical frame payload is correct;
and the state switching module is also used for controlling the frame synchronization state machine to enter a synchronization state if the frame synchronization state machine is correct, otherwise, controlling the frame synchronization state machine to return to a search state.
In a third aspect, the present invention also provides a frame synchronization device comprising a processor, a memory, and a frame synchronization program stored on the memory and executable by the processor, wherein the frame synchronization program, when executed by the processor, implements the steps of the frame synchronization method as described above.
In a fourth aspect, the present invention also provides a readable storage medium having stored thereon a frame synchronization program, wherein the frame synchronization program, when executed by a processor, implements the steps of the frame synchronization method as described above.
In the invention, when a target sequence which is slightly different from a standard physical synchronization sequence is determined from a received bit stream, the frame synchronization state machine is controlled to enter a presynchronization state from a search state, so that the situation that the frame synchronization state machine cannot enter the presynchronization state due to too severe presynchronization conditions is avoided; after the frame synchronization state machine enters the presynchronization state, only the correctness of the data of the physical frame payload part of the physical frame corresponding to the currently determined target sequence is required to be verified, if the verification result is correct, the frame synchronization state machine is controlled to enter the synchronization state, namely, the data of one frame of physical frame is verified, and after the verification is passed, the frame synchronization state machine can be changed from the search state to the synchronization state, and compared with the prior art, the frame synchronization state machine can enter the synchronization state more quickly.
Drawings
Fig. 1 is a schematic diagram of a frame structure of a physical frame in a physical bit stream;
FIG. 2 is a state transition diagram of a frame synchronization state machine;
fig. 3 is a schematic hardware structure of a frame synchronization device according to an embodiment of the present invention;
FIG. 4 is a flow chart of an embodiment of a frame synchronization method according to the present invention;
FIG. 5 is a diagram of a frame structure of a physical frame payload in one embodiment;
FIG. 6 is a schematic diagram of a physical synchronization block PSBd according to an embodiment;
fig. 7 is a schematic functional block diagram of an embodiment of a frame synchronization device according to the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In a first aspect, an embodiment of the present invention provides a frame synchronization device.
Referring to fig. 3, fig. 3 is a schematic hardware structure of a frame synchronization device according to an embodiment of the present invention. In an embodiment of the present invention, the frame synchronization device may include a processor 1001 (e.g., central processing unit Central Processing Unit, CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Wherein the communication bus 1002 is used to enable connected communications between these components; the user interface 1003 may include a Display screen (Display), an input unit such as a Keyboard (Keyboard); the network interface 1004 may optionally include a standard wired interface, a WIreless interface (e.g., WIreless-FIdelity, WI-FI interface); the memory 1005 may be a high-speed random access memory (random access memory, RAM) or a stable memory (non-volatile memory), such as a disk memory, and the memory 1005 may alternatively be a storage device independent of the processor 1001. Those skilled in the art will appreciate that the hardware configuration shown in fig. 3 is not limiting of the invention and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
With continued reference to fig. 3, an operating system, a network communication module, a user interface module, and a frame synchronization program may be included in the memory 1005, which is one type of computer storage medium in fig. 3. The processor 1001 may call a frame synchronization program stored in the memory 1005 and execute the frame synchronization method provided by the embodiment of the present invention.
In a second aspect, an embodiment of the present invention provides a frame synchronization method.
Referring to fig. 4, fig. 4 is a flowchart illustrating an embodiment of a frame synchronization method according to the present invention. As shown in fig. 4, in one embodiment, the frame synchronization method includes:
step S10, when the frame synchronization state machine is in a search state, determining a target sequence from a received bit stream, and controlling the frame synchronization state machine to enter a presynchronization state, wherein the unmatched part of the target sequence is smaller than or equal to N bits compared with a standard physical synchronization sequence, and N is a positive integer;
in this embodiment, when the frame synchronization state machine is in the search state, if the target sequence is searched from the received bit stream, where the unmatched portion of the target sequence is smaller than or equal to N bits compared with the standard physical synchronization sequence, N is a positive integer, and at this time, the frame synchronization state machine can be controlled to enter the presynchronization state.
Specifically, N is set according to actual needs, for example, set to 2. The standard physical synchronisation sequence is defined in the PON standard, specifically 0xC5E51840FD59BB49. Because the length of the standard physical synchronization sequence is 8 bytes, the continuous 8 bytes in the received physical bit stream can be continuously acquired by a sliding window with the size of 8 bytes, and when the 8 bytes acquired at a time are smaller than or equal to N bits compared with the standard physical synchronization sequence, the control frame synchronization state machine can be brought into a presynchronization state.
Step S20, extracting the physical frame corresponding to the target sequence from the bit stream;
in this embodiment, when the 8 bytes acquired at a time are smaller than or equal to N bits compared with the standard physical synchronization sequence, the control frame synchronization state machine may be brought into the pre-synchronization state. Then, taking the 8 bytes as the frame head of the physical frame 1, dividing the physical frame according to the rule of 125 microseconds in the physical bit stream, taking the physical bit stream received from the time t0 to the time t1 when the first byte of the 8 bytes is received as the physical frame 1, taking the physical bit stream received from the time t1 to the time t2 as the physical frame 2, and so on, wherein t is n And t n+1 The time interval therebetween was 125 microseconds, n=0, 1,2,3. Thus, the physical frame corresponding to the target sequence can be extracted from the physical bit stream1 and physical frames following physical frame 1.
Step S30, forward Error Correction (FEC) processing is carried out on the physical frame, and when the FEC processing is successful, the physical frame payload of the physical frame is obtained;
in this embodiment, the physical frame payload in the physical frame is sent after being encoded by the sending end through forward error correction FEC (Forward Error Correction), after the receiving end obtains the physical frame, forward error correction FEC processing is performed on the physical frame, and when FEC processing is successful, that is, FEC decoding is successful and error correction is successful, the physical frame payload of the physical frame can be obtained.
It should be noted that, the forward error correction FEC processing may be performed on a portion of the FEC code block of the physical frame, and when the FEC processing is successful, the portion of the data of the payload of the physical frame is obtained. For example, forward error correction FEC processing is performed on FEC code blocks used for protecting the header portion of the payload of the physical frame in the physical frame, and when FEC processing is successful, data of the header portion of the payload of the physical frame can be obtained. Of course, it is possible to perform forward error correction FEC processing on all code blocks of the physical frame, and when FEC processing is successful, all data of the physical frame payload is obtained.
It is easy to understand that if the FEC decoding of the physical frame fails or the FEC decoding is successful but the error correction fails, the FEC processing is considered to fail, and at this time, the control frame synchronization state machine returns to the search state from the pre-synchronization state, and the step S10 is re-executed.
Step S40, detecting whether the data of the physical frame payload is correct;
in this embodiment, referring to fig. 5, fig. 5 is a schematic frame structure of a physical frame payload in an embodiment. As shown in fig. 5, the physical frame payload (FS frame) includes an FS frame header, an FS frame payload, and an FS tail. Wherein FS is the Framing sub-layer. The FS frame header includes an Hlend field, a BWmap (Bandwidth Map) field, and a PLOAM (Physical Layer OAM (Operation, administrations and Maintenance) field; the Hlend field includes a field describing the length of the BWmap field, a field describing the number of PLOAM fields, and a hybrid error correction HEC code; the FS frame end includes a Bit interleaved parity BIP (Bit-Interleaved Parity) code. According to the frame structure of the physical frame payload, the data of the FS frame header part is found to be protected by the HEC code, so that HEC verification can be carried out on the data of the FS frame header part, and if the verification is passed, the data of the physical frame payload is considered to be correct; similarly, the data at the tail of the FS is protected by the received bit interleaved parity check BIP code, so that BIP check can be performed on the data at the tail of the FS, and if the data passes the BIP check, the data of the payload of the physical frame is considered to be correct. It may be specified that, when the transmitting end transmits the physical frame payload, a specific value is inserted into a specific field of the physical frame payload, and the receiving end detects whether the value in the specific field of the received physical frame payload is a specific value, if so, the data of the physical frame payload is considered to be correct.
Specifically, in one embodiment, step S40 includes:
performing hybrid error correction HEC verification on data in a frame header of the physical frame payload; if the verification is passed, determining that the data of the physical frame payload is correct; if the test is not passed, determining that the data of the physical frame payload is incorrect.
In this embodiment, as shown in fig. 5, the data in the FS frame header part of the physical frame payload (FS frame) is protected by the hybrid error correction HEC code, so HEC verification can be performed on the data in the FS frame header part of the physical frame payload (FS frame), if the verification is passed, the data in the physical frame payload is considered to be correct, otherwise, it is determined that the data in the physical frame payload is incorrect.
Specifically, in one embodiment, step S40 includes:
performing bit interleaved parity check on data in the frame tail of the physical frame payload; if the verification is passed, determining that the data of the physical frame payload is correct; if the test is not passed, determining that the data of the physical frame payload is incorrect.
In this embodiment, as shown in fig. 5, the data at the FS tail of the physical frame payload (FS frame) is protected by the bit interleaved parity check BIP code, so that BIP check can be performed on the data at the FS tail of the physical frame payload, if the data passes the BIP check, the data of the physical frame payload is considered to be correct, otherwise, it is determined that the data of the physical frame payload is incorrect.
Specifically, in one embodiment, step S40 includes:
detecting whether a value in a specific field of the physical frame payload is a preset value; if yes, determining that the data of the physical frame payload is correct; if not, determining that the data of the physical frame payload is incorrect.
In this embodiment, as shown in fig. 4, the FS frame header of the physical frame payload (FS frame) includes a BWmap field and a PLOAM field, where the sender writes a preset value in the BWmap field or PLOAM field of the FS frame header of the physical frame payload (FS frame), and the receiver detects whether the value in the BWmap field or PLOAM field of the FS frame header of the physical frame payload (FS frame) is the preset value, if so, it indicates that the data in the frame header portion of the physical frame payload has no error in the transmission process, so that the data in the physical frame payload has no error in the transmission process is considered, that is, it is determined that the data in the physical frame payload is correct; otherwise, determining that the data of the physical frame payload is incorrect.
In an optional embodiment, the specific field is a bandwidth map BWmap field, and the preset value is an Allocation structure.
In this embodiment, a specific Allocation structure (8 bytes) is defined in the BWmap field, where the Allocation structure meets PON protocol standard, but a value in the Allocation structure is fixed, where the Allocation value is a value reserved by the PON system, for example, 0x3FFF, so that the bandwidth grant is 0, i.e., the grant size is 0, and the startTime value is a fixed value, for example, 0xaaaaaaa, 0x55555555, so that an Allocation structure (8 bytes) is constructed, and if the value in the Allocation structure is a preset fixed value, the receiving end determines that the data of the physical frame payload is correct, otherwise, determines that the data of the physical frame payload is incorrect. The normal operation of the PON system is not affected, and the verification of the correctness of the data of the physical frame payload is also realized. Specifically, the office device OLT constructs the Allocation structure special and synchronous positioning of the remote device ONU.
In another alternative embodiment, the specific field is a physical layer operation maintenance management PLOAM field, and the preset value is a PLOAM message undefined in a PON system protocol of the passive optical network.
In this embodiment, a specific PLOAM (48 bytes) is defined in the PLOAM field, the PLOAM conforms to the PON protocol standard, but the value in the PLOAM is fixed, the PLOAM message type defined by the PON protocol is one byte, and the valid PLOAM message type value is within 0x 20. If a PLOAM message type undefined in the PON system protocol is adopted, for example, PLOAM with a PLOAM message type of 0x33, 0x55 or 0xff can be constructed to any value in other 47 bytes in the PLOAM message field, so long as the PLOAM message constructed in this way can enable the PLOAM message not to influence the operation of the PON system, and meanwhile, the fixed PLOAM message field content can be used for carrying out matching verification of FS frame payload data. The local side device needs to construct the synchronous positioning between the special PLOAM message and the remote side device.
Further, in an embodiment, if the following conditions are satisfied, the data of the physical frame payload is considered to be correct, and when at least one piece of data is not established, it is determined that the data of the physical frame payload is incorrect, as follows:
a. Performing hybrid error correction HEC verification on data in a frame header of a physical frame payload, wherein the verification is passed;
b. performing bit interleaved parity check on data in the frame tail of the physical frame payload, and passing verification;
c. the value in a specific field of the physical frame payload is a preset value.
Step S50, if the result is correct, the control frame synchronization state machine enters a synchronization state, otherwise, the control frame synchronization state machine returns to a search state.
In this embodiment, if the data of the physical frame payload is correct, the control frame synchronization state machine enters the synchronization state from the pre-synchronization state, otherwise, the control frame synchronization state machine returns to the search state from the pre-synchronization state.
In this embodiment, when the frame synchronization state machine is in a search state, determining a target sequence from a received bit stream, and controlling the frame synchronization state machine to enter a presynchronization state, where the unmatched portion of the target sequence is smaller than or equal to N bits, and N is a positive integer, compared with a standard physical synchronization sequence; extracting a physical frame corresponding to the target sequence from the bit stream; performing Forward Error Correction (FEC) processing on the physical frame, and obtaining a physical frame payload of the physical frame when the FEC processing is successful; detecting whether the data of the physical frame payload is correct; if the result is correct, the control frame synchronization state machine enters a synchronization state, otherwise, the control frame synchronization state machine returns to a search state. In this embodiment, considering that in a high error environment, the probability of the optical fiber line having an error is high, which causes that the physical synchronization sequence of the physical frame in the bit stream is slightly different from the standard physical synchronization sequence, according to the existing method, the frame synchronization state machine cannot enter the presynchronization state from the search state, so in this embodiment, when the target sequence slightly different from the standard physical synchronization sequence is determined from the received bit stream, the frame synchronization state machine is controlled to enter the presynchronization state from the search state, thereby avoiding that the frame synchronization state machine cannot enter the presynchronization state because the presynchronization condition is too severe; after the frame synchronization state machine enters the presynchronization state, only the correctness of the data of the physical frame payload part of the physical frame corresponding to the currently determined target sequence is required to be verified, if the verification result is correct, the frame synchronization state machine is controlled to enter the synchronization state, namely, the data of one frame of physical frame is verified, and after the verification is passed, the frame synchronization state machine can be changed from the search state to the synchronization state, and compared with the prior art, the frame synchronization state machine can enter the synchronization state more quickly.
Further, in an embodiment, when the target sequence completely matches the standard physical synchronization sequence, after step S20, the method further includes:
performing HEC verification on synchronous information protected by hybrid error correction HEC codes in a physical synchronous block PSBd of the physical frame; and if the verification is passed, controlling the frame synchronization state machine to enter a synchronization state.
In this embodiment, if the target sequence is completely matched with the standard physical synchronization sequence, the correctness of the data in the physical frame payload portion of the physical frame is not required to be verified, but rather HEC verification is performed on the synchronization information protected by the hybrid error correction HEC code in the physical synchronization block PSBd of the physical frame, and if the verification is passed, the frame synchronization state machine is controlled to enter the synchronization state from the pre-synchronization state. Referring to fig. 6, fig. 6 is a schematic structural diagram of a physical synchronization block PSBd in an embodiment. As shown in fig. 6, the physical synchronization block PSBd includes a physical synchronization sequence Psync field, an SFC structure, and an OC structure, wherein the SFC structure is composed of a multiframe count and HEC code. It can be seen that the SFC structure in the physical synchronization block PSBd of the physical frame is synchronization information protected by the hybrid error correction HEC code, and therefore, HEC check is performed thereon; and if the verification is passed, controlling the frame synchronization state machine to enter a synchronization state. Not shown in the figure, the HEC code is also included in the OC structure, that is, the OC structure is also synchronization information protected by the hybrid error correction HEC code, so that HEC verification can be performed on the OC structure; and if the verification is passed, controlling the frame synchronization state machine to enter a synchronization state.
Further, in an embodiment, after the step of controlling the frame synchronization state machine to enter the synchronization state, the method further includes:
when a physical frame with errors is extracted from the bit stream, controlling a frame synchronization state machine to enter a resynchronization state, wherein:
if the data corresponding to the physical synchronization domain Psync of the physical frame is greater than N bits compared with the standard physical synchronization sequence, the physical frame is a faulty physical frame;
or if the Forward Error Correction (FEC) processing is carried out on the physical frame and the FEC processing fails, the physical frame is a physical frame with errors;
or if HEC verification is carried out on the synchronous information protected by the hybrid error correction HEC code in the physical synchronous block PSBd of the physical frame and the verification is not passed, the physical frame is a physical frame with errors;
or if the data of the physical frame payload of the physical frame is incorrect, the physical frame is a physical frame with errors.
In this embodiment, when the frame synchronization state machine is in the search state, a target sequence is determined from the received bit stream, and the target sequence is entered into the presynchronization state, and at this time, according to the determined target sequence and a rule of dividing physical frames in the physical bit stream according to 125 microseconds, a physical frame 1 corresponding to the target sequence, and a physical frame 2 and a physical frame 3 after the physical frame 1 can be extracted from the physical bit stream.
When the frame synchronization state machine has entered the synchronization state, if a physical frame, such as physical frame 7, is subsequently extracted, when any one of the following conditions occurs, determining that physical frame 7 is a faulty physical frame, and controlling the frame synchronization state machine to enter the re-synchronization state from the synchronization state:
case 1: the data corresponding to the physical synchronization field Psync of the physical frame (referring to fig. 1 and 6, for each physical frame, the data corresponding to each physical frame Psync may be obtained according to the structure of the physical frame and the structure of the PSBd) is greater than N bits compared with the standard physical synchronization sequence;
case 2: performing Forward Error Correction (FEC) processing on the physical frame, wherein the FEC processing fails;
case 3: performing HEC verification on synchronous information protected by hybrid error correction HEC codes in a physical synchronous block PSBd of a physical frame, wherein the verification is not passed;
case 4: the data of the physical frame payload of the physical frame is incorrect.
It is easy to understand that after the frame synchronization state machine enters the synchronization state, when a physical frames are continuously extracted to meet the condition 1, the frame synchronization state machine is controlled to enter a re-synchronization state from the synchronization state; or continuously extracting b physical frames to meet the condition 2, and controlling the frame synchronization state machine to enter a resynchronization state from the synchronization state; or continuously extracting c physical frames to meet the condition 3, and controlling the frame synchronization state machine to enter a resynchronization state from the synchronization state; or continuously extracting d physical frames to meet the condition 4, and controlling the frame synchronization state machine to enter a resynchronization state from the synchronization state. The specific value of a, b, c, d is set according to actual needs.
Further, in an embodiment, when the frame synchronization state machine is in a resynchronization state, the decapsulation process is performed on the extracted physical frame.
In this embodiment, it should be noted that, in the Re-synchronization (Re-Sync) state, the frame synchronization state machine still considers that the frame synchronization is valid, and submits the extracted physical frame as the correct physical frame data information to the framing sublayer to enter the next decapsulation process.
Further, in an embodiment, after the step of controlling the frame synchronization state machine to enter the resynchronization state, the method further includes:
when a new physical frame with errors is extracted from the bit stream, the frame synchronization state machine is controlled to enter a search state.
In this embodiment, for example, when it is determined that the physical frame 7 is a physical frame with errors, the frame synchronization state machine is controlled to enter the resynchronization state from the synchronization state, in which case, if one or more physical frames with errors are extracted again, the frame synchronization is considered to be in error, and the frame synchronization state machine is controlled to enter the search state.
Further, in an embodiment, after the step of controlling the frame synchronization state machine to enter the resynchronization state, the method further includes:
when an error-free physical frame is extracted from the bit stream, controlling a frame synchronization state machine to enter a synchronization state, wherein:
If the data corresponding to the physical synchronization domain Psync of the physical frame is less than or equal to N bits compared with the standard physical synchronization sequence, and/or the synchronization information protected by the hybrid error correction HEC code in the physical synchronization block PSBd of the physical frame is HEC checked, and the verification is passed, and/or the forward error correction FEC processing is performed on the physical frame, and the FEC processing is successful, and/or the data of the physical frame payload of the physical frame is correct, the physical frame is an error-free physical frame.
In this embodiment, if the extracted physical frame is not a physical frame with error in the resynchronization state, the control frame synchronization state machine returns to the synchronization state from the resynchronization state.
The error-free physical frame is defined according to practical situations, for example, when one or more of the following situations are defined, the physical frame is the error-free physical frame:
case 5: compared with the standard physical synchronization sequence, the data corresponding to the physical synchronization domain Psync of the physical frame has a mismatch part smaller than or equal to N bits;
case 6: performing Forward Error Correction (FEC) processing on the physical frame, wherein the FEC processing is successful;
case 7: performing HEC verification on synchronous information protected by hybrid error correction HEC codes in a physical synchronous block PSBd of a physical frame, wherein the verification is passed;
Case 8: the data of the physical frame payload of the physical frame is correct.
If M cases from the case 5 to the case 8 are defined, the physical frame is an error-free physical frame, it is easy to understand that the larger the M setting is, the more severe the condition that the frame synchronization state machine returns to the synchronization state from the resynchronization state is, and in order to make the frame synchronization state machine return to the synchronization state from the resynchronization state more quickly, the larger the M setting is not suitable.
It is easy to understand that, after the frame synchronization state machine enters the resynchronization state, when e physical frames are continuously extracted to meet condition 5, the frame synchronization state machine is controlled to return to the synchronization state from the resynchronization state; and/or continuously extracting f physical frames to meet the condition 6, and controlling the frame synchronization state machine to return to the synchronization state from the resynchronization state; and/or continuously extracting g physical frames to meet the condition 7, and controlling the frame synchronization state machine to return to the synchronization state from the resynchronization state; and/or continuously extracting h physical frames to meet the condition 8, and returning the control frame synchronization state machine from the resynchronization state to the synchronization state. The specific value of e, f, g, h is set according to actual needs.
In a third aspect, an embodiment of the present invention further provides a frame synchronization device.
Referring to fig. 7, fig. 7 is a schematic functional block diagram of a frame synchronization device according to an embodiment of the invention. As shown in fig. 7, in one embodiment, the frame synchronization device includes:
the state switching module 10 is configured to determine a target sequence from a received bit stream when the frame synchronization state machine is in a search state, and control the frame synchronization state machine to enter a presynchronization state, where the unmatched portion of the target sequence is less than or equal to N bits, and N is a positive integer, compared with a standard physical synchronization sequence;
an extracting module 20, configured to extract a physical frame corresponding to the target sequence from the bitstream;
the FEC processing module 30 is configured to perform forward error correction FEC processing on the physical frame, and obtain a physical frame payload of the physical frame when the FEC processing is successful;
a detection module 40, configured to detect whether the data of the physical frame payload is correct;
the state switching module 10 is further configured to control the frame synchronization state machine to enter a synchronization state if the frame synchronization state machine is correct, and otherwise, control the frame synchronization state machine to return to a search state.
Further, in an embodiment, when the target sequence completely matches the standard physical synchronization sequence, the detection module 40 is further configured to:
performing HEC verification on synchronous information protected by hybrid error correction HEC codes in a physical synchronous block PSBd of the physical frame;
The state switching module 10 is further configured to control the frame synchronization state machine to enter the synchronization state if the check passes.
Further, in an embodiment, the detection module 40 is further configured to:
performing hybrid error correction HEC verification on data in a frame header of the physical frame payload;
if the verification is passed, determining that the data of the physical frame payload is correct;
if the test is not passed, determining that the data of the physical frame payload is incorrect.
Further, in an embodiment, the detection module 40 is further configured to:
performing bit interleaved parity check on data in the frame tail of the physical frame payload;
if the verification is passed, determining that the data of the physical frame payload is correct;
if the test is not passed, determining that the data of the physical frame payload is incorrect.
Further, in an embodiment, the detection module 40 is further configured to:
detecting whether a value in a specific field of the physical frame payload is a preset value;
if yes, determining that the data of the physical frame payload is correct;
if not, determining that the data of the physical frame payload is incorrect.
Further, in an embodiment, the specific field is a bandwidth map BWmap field, and the preset value is an Allocation structure.
Further, in an embodiment, the specific field is a physical layer operation maintenance management PLOAM field, and the preset value is a PLOAM message undefined in a PON system protocol of the passive optical network.
Further, in an embodiment, the state switching module 10 is further configured to:
when a physical frame with errors is extracted from the bit stream, controlling a frame synchronization state machine to enter a resynchronization state, wherein:
if the data corresponding to the physical synchronization domain Psync of the physical frame is greater than N bits compared with the standard physical synchronization sequence, the physical frame is a faulty physical frame;
or if the Forward Error Correction (FEC) processing is carried out on the physical frame and the FEC processing fails, the physical frame is a physical frame with errors;
or if HEC verification is carried out on the synchronous information protected by the hybrid error correction HEC code in the physical synchronous block PSBd of the physical frame and the verification is not passed, the physical frame is a physical frame with errors;
or if the data of the physical frame payload of the physical frame is incorrect, the physical frame is a physical frame with errors.
Further, in an embodiment, the frame synchronization device further includes a decapsulation module, configured to:
and when the frame synchronization state machine is in a resynchronization state, performing decapsulation processing on the extracted physical frame.
Further, in an embodiment, the state switching module 10 is further configured to:
when a new physical frame with errors is extracted from the bit stream, the frame synchronization state machine is controlled to enter a search state.
Further, in an embodiment, the state switching module 10 is further configured to:
when an error-free physical frame is extracted from the bit stream, controlling a frame synchronization state machine to enter a synchronization state, wherein:
if the data corresponding to the physical synchronization domain Psync of the physical frame is smaller than or equal to N bits compared with the standard physical synchronization sequence, and/or the forward error correction FEC processing is performed on the physical frame, and the FEC processing is successful, and/or the HEC check is performed on the synchronization information protected by the hybrid error correction HEC code in the physical synchronization block PSBd of the physical frame, and the check passes, and/or the data of the physical frame payload of the physical frame is correct, the physical frame is an error-free physical frame.
The function implementation of each module in the frame synchronization device corresponds to each step in the frame synchronization method embodiment, and the function and implementation process thereof are not described in detail herein.
In a fourth aspect, embodiments of the present invention also provide a readable storage medium.
The readable storage medium of the present invention stores a frame synchronization program, wherein the frame synchronization program, when executed by a processor, implements the steps of the frame synchronization method as described above.
The method implemented when the frame synchronization procedure is executed may refer to various embodiments of the frame synchronization method of the present invention, and will not be described herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) as described above, comprising several instructions for causing a terminal device to perform the method according to the embodiments of the present invention.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
Claims (14)
1. A frame synchronization method, the frame synchronization method comprising:
when the frame synchronization state machine is in a search state, determining a target sequence from a received bit stream, and controlling the frame synchronization state machine to enter a presynchronization state, wherein the unmatched part of the target sequence is smaller than or equal to N bits compared with a standard physical synchronization sequence, and N is a positive integer;
extracting a physical frame corresponding to the target sequence from the bit stream;
performing Forward Error Correction (FEC) processing on the physical frame, and obtaining a physical frame payload of the physical frame when the FEC processing is successful;
detecting whether the data of the physical frame payload is correct;
if the frame synchronization state machine is correct, the frame synchronization state machine is controlled to enter a synchronization state, otherwise, the frame synchronization state machine is controlled to return to a search state;
if the FEC processing fails, the control frame synchronization state machine returns to the searching state.
2. The frame synchronization method of claim 1, further comprising, when the target sequence is completely matched with a standard physical synchronization sequence, after the step of extracting a physical frame corresponding to the target sequence from the bitstream:
performing HEC verification on synchronous information protected by hybrid error correction HEC codes in a physical synchronous block PSBd of the physical frame;
and if the verification is passed, controlling the frame synchronization state machine to enter a synchronization state.
3. The frame synchronization method of claim 1, wherein the step of detecting whether the data of the physical frame payload is correct comprises:
performing hybrid error correction HEC verification on data in a frame header of the physical frame payload;
if the verification is passed, determining that the data of the physical frame payload is correct;
if the test is not passed, determining that the data of the physical frame payload is incorrect.
4. The frame synchronization method of claim 1, wherein the step of detecting whether the data of the physical frame payload is correct comprises:
performing bit interleaved parity check on data in the frame tail of the physical frame payload;
if the verification is passed, determining that the data of the physical frame payload is correct;
If the test is not passed, determining that the data of the physical frame payload is incorrect.
5. The frame synchronization method of claim 1, wherein the step of detecting whether the data of the physical frame payload is correct comprises:
detecting whether a value in a specific field of the physical frame payload is a preset value;
if yes, determining that the data of the physical frame payload is correct;
if not, determining that the data of the physical frame payload is incorrect.
6. The frame synchronization method of claim 5, wherein the specific field is a bandwidth map BWmap field, and the preset value is an Allocation structure.
7. The frame synchronization method of claim 5, wherein the specific field is a physical layer operation maintenance administration PLOAM field, and the preset value is a PLOAM message undefined in a PON system protocol of the passive optical network.
8. The frame synchronization method according to any one of claims 1 to 7, further comprising, after the step of controlling the frame synchronization state machine to enter a synchronization state:
when a physical frame with errors is extracted from the bit stream, controlling a frame synchronization state machine to enter a resynchronization state, wherein:
if the data corresponding to the physical synchronization domain Psync of the physical frame is greater than N bits compared with the standard physical synchronization sequence, the physical frame is a faulty physical frame;
Or if the Forward Error Correction (FEC) processing is carried out on the physical frame and the FEC processing fails, the physical frame is a physical frame with errors;
or if HEC verification is carried out on the synchronous information protected by the hybrid error correction HEC code in the physical synchronous block PSBd of the physical frame and the verification is not passed, the physical frame is a physical frame with errors;
or if the data of the physical frame payload of the physical frame is incorrect, the physical frame is a physical frame with errors.
9. The frame synchronization method of claim 8, further comprising, after the step of controlling the frame synchronization state machine to enter a resynchronization state:
and when the frame synchronization state machine is in a resynchronization state, performing decapsulation processing on the extracted physical frame.
10. The frame synchronization method of claim 8, further comprising, after the step of controlling the frame synchronization state machine to enter a resynchronization state:
when a new physical frame with errors is extracted from the bit stream, the frame synchronization state machine is controlled to enter a search state.
11. The frame synchronization method of claim 8, further comprising, after the step of controlling the frame synchronization state machine to enter a resynchronization state:
When an error-free physical frame is extracted from the bit stream, controlling a frame synchronization state machine to enter a synchronization state, wherein:
if the data corresponding to the physical synchronization domain Psync of the physical frame is smaller than or equal to N bits compared with the standard physical synchronization sequence, and/or the forward error correction FEC processing is performed on the physical frame, and the FEC processing is successful, and/or the HEC check is performed on the synchronization information protected by the hybrid error correction HEC code in the physical synchronization block PSBd of the physical frame, and the check passes, and/or the data of the physical frame payload of the physical frame is correct, the physical frame is an error-free physical frame.
12. A frame synchronization device, the frame synchronization device comprising:
the state switching module is used for determining a target sequence from a received bit stream when the frame synchronization state machine is in a search state, and controlling the frame synchronization state machine to enter a presynchronization state, wherein the unmatched part of the target sequence is smaller than or equal to N bits compared with a standard physical synchronization sequence, and N is a positive integer;
an extracting module, configured to extract a physical frame corresponding to the target sequence from the bitstream;
the FEC processing module is used for performing Forward Error Correction (FEC) processing on the physical frame, and obtaining the physical frame payload of the physical frame when the FEC processing is successful;
A detection module, configured to detect whether data of the physical frame payload is correct;
the state switching module is also used for controlling the frame synchronization state machine to enter a synchronization state if the frame synchronization state machine is correct, otherwise, controlling the frame synchronization state machine to return to a search state;
and the state switching module is also used for controlling the frame synchronization state machine to return to the search state if the FEC processing fails.
13. A frame synchronization device comprising a processor, a memory, and a frame synchronization program stored on the memory and executable by the processor, wherein the frame synchronization program, when executed by the processor, implements the steps of the frame synchronization method according to any one of claims 1 to 11.
14. A readable storage medium, wherein a frame synchronization program is stored on the readable storage medium, wherein the frame synchronization program, when executed by a processor, implements the steps of the frame synchronization method according to any one of claims 1 to 11.
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