CN114625234A

CN114625234A - Server voltage monitoring method, device and system

Info

Publication number: CN114625234A
Application number: CN202210329160.5A
Authority: CN
Inventors: 张世强; 李岩
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2022-03-30
Filing date: 2022-03-30
Publication date: 2022-06-14

Abstract

The invention discloses a server voltage monitoring method, a device and a system, wherein the method is applied to a complex programmable logic device, the complex programmable logic device is connected with a power supply of a server, and the method comprises the following steps: when the server is monitored to be powered on, sending a control signal to a voltage acquisition module so that the voltage acquisition module acquires the voltage of a mainboard of the server; receiving and storing voltage data returned by the voltage acquisition module; and sending the voltage data to a target object and informing the BMC to read the voltage data. The technical scheme provided by the invention avoids the problem that the voltage data of the server cannot be acquired due to untimely starting of the BMC or failure of the BMC, and improves the reliability of monitoring the voltage of the server.

Description

Server voltage monitoring method, device and system

Technical Field

The invention relates to the field of data monitoring, in particular to a server voltage monitoring method, device and system.

Background

Generally, the problem of abnormal situations such as shutdown or no startup of a server is firstly considered whether the power supply of the server is normal, the abnormal situations are very difficult to check the power supply situation in a server room, firstly, a special voltage measuring tool is needed on site, and secondly, a site support person is required to be familiar with a fault reporting server circuit, so that the server voltage monitoring is very important. In the prior art, monitoring of a voltage of a motherboard of a server is usually achieved through a Board Management Controller (BMC), but when the BMC is hung up or the BMC is not started immediately after the server is powered on, the situation that the voltage cannot be monitored is encountered, so that robustness and reliability of monitoring work of the server voltage are poor. Therefore, how to improve the reliability of server voltage monitoring is an urgent problem to be solved.

Disclosure of Invention

In view of this, embodiments of the present invention provide a server voltage monitoring method, apparatus, and system, so as to improve reliability of server voltage monitoring.

According to a first aspect, the present invention provides a server voltage monitoring method, applied to a complex programmable logic device, where the complex programmable logic device is connected to a power supply of a server, the method including: when the server is monitored to be powered on, sending a control signal to a voltage acquisition module so that the voltage acquisition module acquires the voltage of a mainboard of the server; receiving and storing voltage data returned by the voltage acquisition module; and sending the voltage data to a target object, and informing the BMC to read the voltage data.

Optionally, the method further comprises: when the server is electrified, sending a second control signal to the state monitoring module so that the state monitoring module collects state signals of each power supply module on a server mainboard; receiving state data returned by the state monitoring module; adding the state data to the voltage data.

Optionally, the method further comprises: and informing a processor in a server to read the voltage data so that the processor reads the voltage data from the complex programmable logic device and displays the read voltage data on a BIOS configuration interface.

Optionally, before sending the voltage data to a target object and informing the BMC to read the voltage data, the method further includes: storing a plurality of voltage data received for a preset number of continuous times, and removing the maximum data and the minimum data in the plurality of voltage data; and calculating the average value of the residual voltage data to obtain preprocessed data, and taking the preprocessed data as the voltage data.

Optionally, the method further comprises: and judging whether the voltage data is abnormal or not based on a preset condition, if so, controlling an LED state indicating module to display a preset character, and sending an abnormal message to the BMC.

Optionally, the voltage data is stored in a first register in the complex programmable logic device, and the notifying the BMC to read the voltage data includes: and continuously sending a plurality of paths of general input and output signals to the BMC so that the BMC can acquire a first register state of the first register according to the plurality of paths of general input and output signals and read voltage data from the first register when the first register state represents updated voltage data.

Optionally, the voltage data is stored in a second register in the complex programmable logic device, and the notifying a processor in a server to read the voltage data includes: and continuously sending a plurality of paths of general input and output signals to a processor in the server, so that the processor in the server acquires a second register state of the second register according to the plurality of paths of general input and output signals, and reads the voltage data from the second register when the second register state represents the updated voltage data.

According to a second aspect, an embodiment of the present invention provides a server voltage monitoring apparatus, which is applied to a complex programmable logic device, where the complex programmable logic device is connected to a power supply of a server, and the apparatus includes: the control unit is used for sending a control signal to the voltage acquisition module when the server is monitored to be powered on so as to enable the voltage acquisition module to acquire the mainboard voltage of the server; the data receiving unit is used for receiving and storing the voltage data returned by the voltage acquisition module; and the data forwarding unit is used for sending the voltage data to a target object and informing the BMC to read the voltage data.

According to a third aspect, an embodiment of the present invention provides a server voltage monitoring system, including: the system comprises a complex programmable logic device, a voltage acquisition module and a BMC, wherein the complex programmable logic device is connected with a power supply of a server and is respectively in communication connection with the voltage acquisition module and the BMC; the complex programmable logic device stores computer instructions for causing the complex programmable logic device to perform the method provided in any of the alternative embodiments of the first aspect.

Optionally, the system further comprises: the state monitoring module is in communication connection with the complex programmable logic device and is used for collecting state signals of each power supply module on the server mainboard; the complex programmable logic device is in communication connection with a processor of the server.

The technical scheme provided by the application has the following advantages:

according to the technical scheme, interface resources are enriched by using a Complex Programmable Logic Device (CPLD), and the CPLD directly controls the voltage acquisition module to optimally design voltage monitoring of the server. When the CPLD is powered on with the server and the BMC simultaneously, the response speed of the CPLD is far faster than the starting speed of the server and the starting speed of the BMC. Therefore, the CPLD intelligently controls the multi-path voltage acquisition chip, voltage acquisition is carried out in a polling mode, voltage data at the initial power-on stage of the server are acquired in time, and besides the voltage data are output to the BMC by the CPLD, the voltage data are output to an external printer, a display and other target objects capable of displaying the data through a debugging serial port or other common interfaces. The problem that server voltage data cannot be acquired due to untimely BMC starting or BMC faults is avoided, and the reliability of server voltage monitoring is improved.

In addition, in another embodiment, the CPLD also performs intelligent optimization processing on the cached voltage data, and the BMC does not directly perform voltage acquisition chip operation, but reads the intelligently optimized data of the CPLD and provides the BMC with more reliable voltage data. In addition, in an embodiment, the CPLD is also in communication connection with a processor of the server, so that after the server is powered on, the processor can read the voltage data cached in the CPLD and display the voltage data on the BIOS configuration interface. The server voltage monitoring scheme provided by the embodiment of the invention can realize multi-variety voltage monitoring through the debugging serial port, the BIOS configuration interface and the BMC monitoring interface, thereby further improving the reliability of voltage monitoring.

Drawings

The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and not to be construed as limiting the invention in any way, and in which:

FIG. 1 is a schematic diagram illustrating steps of a server voltage monitoring method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating a server voltage monitoring apparatus according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a server voltage monitoring system according to an embodiment of the present invention;

FIG. 4 illustrates a topology diagram of a voltage acquisition module in one embodiment of the invention;

FIG. 5 is a diagram illustrating a topology of a condition monitoring module in accordance with an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of the present invention.

Referring to fig. 1, in an embodiment, a server voltage monitoring method is applied to a complex programmable logic device, where the complex programmable logic device is connected to a power supply of a server, and the method specifically includes the following steps:

step S101: when the server is monitored to be powered on, a control signal is sent to the voltage acquisition module, so that the voltage acquisition module acquires the voltage of the mainboard of the server.

Step S102: and receiving and storing the voltage data returned by the voltage acquisition module.

Step S103: and sending the voltage data to a target object and informing the BMC to read the voltage data.

Specifically, the server voltage monitoring scheme provided by the embodiment of the invention monitors the voltage of the mainboard of the Ampere platform server in an actual scene, and utilizes rich interface resources of the CPLD to synchronously connect the CPLD with the power supply of the server, so that the CPLD, the server and the BMC can be synchronously electrified. Based on the advantage of second-level response after the CPLD is powered on, the CPLD directly controls the voltage acquisition module, intelligently controls a plurality of voltage acquisition chips in the voltage acquisition module, acquires voltage in a polling mode, and timely acquires voltage data at the power-on initial stage of the server, and the CPLD outputs the voltage data to an external printer, a display and other target objects capable of displaying the data through a debugging serial port or other common interfaces besides outputting the voltage data to the BMC. The problem that server voltage data cannot be acquired due to untimely BMC starting or BMC faults is solved. Even if the worst condition that the BMC and the debugging serial port fail to communicate, or the BMC fails, or the server fails to start directly, the voltage data of the server is collected and stored through the independent work of the CPLD from the power-on start, so that the subsequent data can be analyzed conveniently, and the reliability of the voltage monitoring of the server is greatly improved.

Specifically, in an embodiment, the server voltage monitoring method provided in the embodiment of the present invention further includes the following steps:

the method comprises the following steps: when the server is powered on in an alternating current mode, a second control signal is sent to the state monitoring module, so that the state monitoring module collects state signals of all power modules on the server mainboard.

Step two: and receiving the status data returned by the status monitoring module.

Step three: the status data is added to the voltage data.

Specifically, in this embodiment, the CPLD further establishes a communication connection with the state monitoring module, and the state monitoring module may be composed of a plurality of I/O expansion chips, so that the CPLD collects state signals such as enable, Power Good, and the like of each Power module on the server motherboard. So as to confirm whether the control signal and state of each power module generating voltage are abnormal. If the enable signal is normal, the Power supply chip is damaged, and if the enable signal is abnormal, the control end is abnormal. And the state data returned by the state monitoring module is added into the voltage data and then data output is carried out, so that the accuracy of fault positioning is further improved.

step four: and informing a processor in the server to read the voltage data so that the processor reads the voltage data from the complex programmable logic device and displays the read voltage data on a BIOS configuration interface.

Specifically, in this embodiment, the CPLD is additionally in communication connection with a processor in the server, the configuration processor reads the voltage data cached in the CPLD, and displays the read voltage data on the BIOS configuration interface of the server, so that when the server is powered on, the server can jump to the BIOS configuration interface to check at any time, and even if the BMC fails, the monitoring data of the server voltage can be displayed on the BIOS configuration interface, thereby further improving the robustness and reliability of the server voltage monitoring scheme.

Specifically, in an embodiment, before the step S103, the method further includes the following steps:

step five: the method includes storing a plurality of voltage data received for a preset number of consecutive times, and removing a maximum data and a minimum data among the plurality of voltage data.

Step six: and calculating the average value of the residual voltage data to obtain preprocessed data, and taking the preprocessed data as voltage data.

Specifically, in the embodiment, the bit width of the voltage data buffered in the CPLD is 12 bits, and the voltage data received for a preset number of consecutive times (for example, 5 times) is reserved each time, for example, the address spaces are 0x27 to 0x00, 0x57 to 0x30, 0x87 to 0x60, 0xB7 to 0x90, and 0xE7 to 0xC0, respectively. The CPLD sorts the voltage acquisition data according to 5 times, removes the maximum value and the minimum value, accumulates and averages the remaining 3 groups of data, and then stores the data in a register. Compared with a method for directly acquiring voltage data of a server mainboard by a processor and a BMC in the server, the method has the advantages that the processor and the BMC in the server read the data after the CPLD optimization processing, and the accuracy of the voltage data is further improved.

step seven: and judging whether the voltage data is abnormal or not based on a preset condition, if so, controlling the LED state indicating module to display a preset character, and sending an abnormal message to the BMC. Specifically, in this embodiment, the CPLD is further in communication connection with an LED status indication module preset on the server motherboard, and performs anomaly analysis on the acquired voltage data, and when the voltage data meets an anomaly preset condition (including but not limited to that the voltage data exceeds a preset threshold, and a change trend of the voltage data does not match a preset trend), sends a control instruction to the LED status indication module, so that the LED status indication module displays a specified preset character, for example, "EE", thereby further improving the reliability of monitoring the server voltage.

Specifically, in an embodiment, the step S103 of storing the voltage data in a first register of the complex programmable logic device specifically includes the following steps:

step eight: and continuously sending the multi-path general input and output signal to the BMC so that the BMC can acquire the first register state of the first register according to the multi-path general input and output signal and read the voltage data from the first register when the first register state represents the updated voltage data.

Specifically, in this embodiment, an individual first register is set in the CPLD for the BMC to read data, and the data read by the BMC does not interfere with the reading of the processor and the output of the debug serial port, thereby ensuring stable and reliable data output. And continuously sending the multi-path General input and output signal to the BMC, enabling the BMC to continuously acquire the first register state of the first register according to the multi-path General input and output signal (General Purpose input and output (GPI/O)), and then executing a corresponding data reading action according to the state of the first register, so that the flexibility, the accuracy and the timeliness of the data reading of the BMC are improved. For example: the CPLD distributes 5 GPI/O signals for the BMC, is respectively connected with 5 pins PWR _ ADC _ HARF, PWR _ ADC _ EMPTY, PWR _ ADC _ FULL, PWR _ ADC _ BUSYn and PWR _ ADC _ INTn of the CPLD in a butt joint mode, reads 40 paths of mainboard voltages acquired by the CPLD through an I2C bus, displays the mainboard voltages on a BMC display page, and monitors the voltage state of the mainboard. The signals of the 5 pins are respectively characterized by the following meanings: the PWR _ ADC _ HARF signal is 1 to represent that the CPLD has accumulatively acquired data for more than 3 times, and the cache is half full; the PWR _ ADC _ EMPTY signal is 1 and represents that the buffer is EMPTY; the PWR _ ADC _ FULL signal represents that the CPLD has accumulatively acquired 5 times of data for 1, and the cache is FULL; the PWR _ ADC _ BUSYn signal is 1, which indicates that the register is busy, the CPLD updates the data in the first register and the data cannot be read currently; the PWR _ ADC _ INTn signal is 0 to indicate that new data is present in the register and can be read. The BMC continuously monitors the state of PWR _ ADC _ BUSYn and PWR _ ADC _ INTn, and performs voltage readings without being busy and with new data.

Specifically, in an embodiment, the step four includes the following steps:

step nine: and continuously sending the multi-path general input and output signals to a processor in the server, so that the processor in the server acquires a second register state of the second register according to the multi-path general input and output signals, and reads the voltage data from the second register when the second register state represents the updated voltage data. Specifically, the mechanism and principle related to the processor in the server implemented in this embodiment are the same as the mechanism and principle related to the BMC in the step eight described above, and reference is made to the description related to the step eight in detail, which is not described herein again.

Through the steps, according to the technical scheme provided by the application, the interface resources are enriched by using a Complex Programmable Logic Device (CPLD), and the CPLD directly controls the voltage acquisition module to optimally design the voltage monitoring of the server. When the CPLD is powered on with the server and the BMC simultaneously, the response speed of the CPLD is far faster than the starting speed of the server and the starting speed of the BMC. Therefore, the CPLD intelligently controls the multi-path voltage acquisition chip, voltage acquisition is carried out in a polling mode, voltage data at the initial power-on stage of the server are acquired in time, and besides the voltage data are output to the BMC by the CPLD, the voltage data are output to an external printer, a display and other target objects capable of displaying the data through a debugging serial port or other common interfaces. The problem that server voltage data cannot be acquired due to untimely BMC starting or BMC faults is avoided, and the reliability of server voltage monitoring is improved.

As shown in fig. 2, this embodiment further provides a server voltage monitoring apparatus, which is applied to a complex programmable logic device, where the complex programmable logic device is connected to a power supply of a server, and the apparatus includes:

and the control unit 101 is configured to send a control signal to the voltage acquisition module when it is monitored that the server is powered on, so that the voltage acquisition module acquires the voltage of the motherboard of the server. For details, refer to the related description of step S101 in the above method embodiment, and no further description is provided here.

And the data receiving unit 102 is used for receiving and storing the voltage data returned by the voltage acquisition module. For details, refer to the related description of step S102 in the above method embodiment, and no further description is provided here.

And a data forwarding unit 103 for transmitting the voltage data to the target object and informing the BMC of reading the voltage data. For details, refer to the related description of step S103 in the above method embodiment, and no further description is provided here.

The server voltage monitoring device provided in the embodiment of the present invention is configured to execute the server voltage monitoring method provided in the above embodiment, and the implementation manner and the principle thereof are the same, and details are referred to the related description of the above method embodiment and are not repeated.

Through the cooperation of the above components, the technical scheme provided by the application enriches interface resources by using a Complex Programmable Logic Device (CPLD), and the CPLD directly controls the voltage acquisition module to optimally design the voltage monitoring of the server. When the CPLD is powered on with the server and the BMC at the same time, the response speed of the CPLD is far faster than the starting speed of the server and the starting speed of the BMC. Therefore, the CPLD intelligently controls the multi-path voltage acquisition chip, voltage acquisition is carried out in a polling mode, voltage data at the initial power-on stage of the server are acquired in time, and besides the voltage data are output to the BMC by the CPLD, the voltage data are output to an external printer, a display and other target objects capable of displaying the data through a debugging serial port or other common interfaces. The problem that server voltage data cannot be acquired due to untimely BMC starting or BMC faults is avoided, and the reliability of server voltage monitoring is improved.

In addition, in another embodiment, the CPLD also performs intelligent optimization processing on the cached voltage data, and the BMC does not directly perform voltage acquisition operation by the overvoltage acquisition module, but reads the intelligently optimized data of the CPLD and provides the more reliable voltage data for the BMC. In addition, in an embodiment, the CPLD is also in communication connection with a processor of the server, so that after the server is powered on, the processor can read the voltage data cached in the CPLD and display the voltage data on the BIOS configuration interface. The server voltage monitoring scheme provided by the embodiment of the invention can realize multi-variety voltage monitoring through the debugging serial port, the BIOS configuration interface and the BMC monitoring interface, thereby further improving the reliability of voltage monitoring.

Fig. 3 shows a server voltage monitoring system according to an embodiment of the present invention, including: the system comprises a complex programmable logic device 901 (hereinafter referred to as a CPLD901), a voltage acquisition module 902 and a BMC903, wherein the CPLD901 is connected with a power supply of a server, the CPLD901 is respectively connected with the voltage acquisition module 902 and the BMC903 in a communication manner, and may be connected through a bus or other manners, and fig. 3 is exemplified by I2C bus connection.

In an embodiment, the server voltage monitoring system provided in the embodiment of the present invention further includes a state monitoring module 904, where the state monitoring module 904 is in communication connection with the complex programmable logic device, and the state monitoring module 904 is configured to collect state signals of each power module on a server motherboard;

the complex programmable logic device is also communicatively coupled to a processor 905 of the server (i.e., Ampere processor 905 in the Ampere platform server in this embodiment).

In this embodiment, the CPLD901 selects a CPLD901 chip LCMXO2-7000HC-4FG484C from LATTIC, which is mainly responsible for the intelligent acquisition of the voltage of the Ampere platform server 40, i.e., the CPLD901 is used as a main body to perform voltage data acquisition control, instead of the Ampere processor 905 and the BMC903 to control the operation of the voltage acquisition module 902, the CPLD901 reserves a first register and a second register of a voltage buffer for the BMC903 and the Ampere processor 905 to read the buffered voltage data. The data bit width of the voltage cache in the first register is 12 bits, 40 paths of data are acquired at one time, 5 acquisition spaces are reserved for voltage data cache, the address spaces are 0x 27-0 x00, 0x 57-0 x30, 0x 87-0 x60, 0xB 7-0 x90 and 0xE 7-0 xC0 respectively, and the second register and the first register are similar. In this embodiment, the CPLD901 sorts the voltage acquisition data according to 5 times, removes the maximum and minimum values, accumulates and averages the remaining 3 sets of data, and stores the averaged data in the first register and the second register, so as to provide more stable motherboard voltage data for the BMC903 and the amp re processor 905.

In this embodiment, the voltage acquisition module 902 adopts an analog-to-digital signal acquisition chip of 5 TI company ADC128D818CIMTX for acquiring 40 kinds of motherboard supply voltages. Voltage acquisition module 902 has 40 voltage acquisition paths AD _ IN [39:0], the acquisition topology is shown IN FIG. 4. The CPLD901 reads the corresponding ADC chips according to I2C addresses 0x3A, Ox3C, Ox3E, Ox6A and Ox6C of the ADC0-4 through an I2C _ C bus, and indirectly reads the voltage of the 40 voltage acquisition channels AD _ IN [39:0 ]. Each acquisition channel is allocated as: AD _ IN [7:0] is on ADC0 chip, AD _ IN [15:8] is on ADC1 chip, AD _ IN [23:16] is on ADC2 chip, AD _ IN [31:24] is on ADC3 chip, and AD _ IN [39:32] is on ADC4 chip. In order to meet the voltage input requirement of the ADC channel, the voltage of each channel is adjusted and adapted in a resistance voltage division mode, voltage division coefficient adjustment is carried out after the voltage is read, and the various characteristics of Ampere power supply voltage are matched, wherein the specific details are shown in Table 1.

TABLE 1 resistance voltage divider

In this embodiment, the status monitoring module 904 is mainly responsible for monitoring the enabling signals and Power Good signals of the Power modules generating voltages corresponding to the 40 voltage collecting channels, so as to determine whether the control signals and statuses of the Power modules generating voltages on the motherboard are abnormal. The enabling signals of the Power supply modules are directly connected to the CPLD901, the Power Good signals of the Power supply modules are connected into the 3 PCA9555, the topological structure diagram is shown in FIG. 5, the CPLD901 can read the signal states of the Power Good signals of various voltages through an I2C _ D bus, the normal condition is high level, and the abnormal condition is reading low level.

In the embodiment of the present invention, the Ampere processor 905 adopts an Ampere platform Altra processor, five general input/output signals are distributed to the Ampere processor 905 from the CPLD901, and are respectively connected to five pins, namely, PWR _ ADC _ HARF, PWR _ ADC _ EMPTY, PWR _ ADC _ FULL, PWR _ ADC _ BUSYn and PWR _ ADC _ INTn, of the CPLD901, and the respective functions of the five pins refer to the description of the above method embodiment, and are not described herein again. The Ampere processor 905 is started and enters a BIOS configuration interface, and 40 paths of mainboard voltages acquired by the CPLD901 are read through an I2C _ A bus and displayed on a mainboard voltage display interface in the BIOS configuration interface. The Ampere processor 905 monitors the level states of PWR _ ADC _ BUSYn and PWR _ ADC _ INTn, and performs voltage reading in the case that the registers characterizing the CPLD901 are not busy and there is new data.

In this embodiment, the BMC903 is mainly responsible for server board card management, and the present invention adopts a design chip ASPEED AST2500 commonly used in the industry, and like the Ampere processor 905, this embodiment allocates five general input/output signals to the BMC903 from the CPLD901, and respectively interfaces with the PWR _ ADC _ HARF, PWR _ ADC _ EMPTY, PWR _ ADC _ FULL, PWR _ ADC _ busy, and PWR _ ADC _ INTn pins of the CPLD901, and the functions of each pin refer to the relevant description of the above method embodiment, and are not described herein again. And reading 40 paths of mainboard voltages acquired by the CPLD901 through the I2C _ B bus and displaying the mainboard voltages on the BMC 903. BMC903 monitors the level status of PWR _ ADC _ BUSYn, PWR _ ADC _ INTn, and performs voltage reads without busy and new data.

In an embodiment, the server voltage monitoring system provided in the embodiment of the present invention further includes an LED status indication module 906, which is designed in the form of a 7-segment digital tube on a motherboard by an LED indicator lamp, and indicates the voltage collection times and the voltage status of the current CPLD 901. The LED status indication module 906 is communicatively connected to the CPLD 901. For example: when the CPLD901 monitors that there is an abnormality in any Power Good signal of the state monitoring module 904, the CPLD901 will control the LED state indicating module 906 to display an EE character to identify that there is a voltage fault in the motherboard voltage. When the CPLD901 monitors that the state monitoring module 904 is not abnormal, the current voltage acquisition times are displayed, for example, the data range is displayed from 1 to 5.

Because the debugging serial port 907 is mainly responsible for printing power-on and power-on information of the Ampere platform server, including information such as CPU information printing, memory information printing, BIOS and BMC903 version, and in addition, the serial port can print abnormal states under the condition that the Ampere platform server cannot be started, based on the basic functions, in one embodiment, the debugging serial port 907 of the Ampere platform server is improved by the embodiment of the present invention: additional voltage monitoring information is added to the functional mechanism of debug serial port 907. When the CPLD901 is powered on, voltage data is output to an external target object through the debugging serial port 907, so that operation and maintenance personnel can conveniently check the server. The present invention is not limited thereto, and in other embodiments, the interface or the serial port having the same or similar function as the debug serial port 7 may be configured to additionally add the voltage monitoring information to implement the above function.

The CPLD901 is a programmable logic device that uses CMOS EPROM, EEPROM, flash memory, SRAM, and other programming technologies to achieve high density, high speed, and low power consumption. Those skilled in the art will understand that all or part of the processes in the methods of the embodiments described above can be implemented by instructing relevant hardware through a computer program, and the implemented program can be stored in a readable storage medium in the CPLD901, and when executed, the program can include the processes of the embodiments of the methods described above.

Based on the above hardware connection relationship and computer program, when the server voltage monitoring system provided by the embodiment of the invention normally works, after the Ampere server normally supplies Power, the CPLD901 controls the enabling signals of each Power module to complete Power-on, the CPLD901 reads 40 paths of AD acquisition voltage values through the I2C _ C bus automatic polling voltage acquisition module 902, and simultaneously operates the enabling signals and the Power Good signal states of the I2C _ D reading state monitoring module 904 to confirm whether the enabling signals and the Power Good signals are normal when the voltage abnormality is monitored, if the enabling signals are normal, the Power supply chip is damaged, if the enabling signals are abnormal, the control end is abnormal, and further, the fault is accurately positioned. The CPLD901 performs maximum value and minimum value elimination averaging operation every time 40 voltage data acquisition paths are performed for preset times (for example, 5 times), then processed data are respectively stored in a first register and a second register, after the data are stored in the first register and the second register, the CPLD901 releases the control right of the first register and the second register and sets a signal of a PWR _ ADC _ INTn pin to be 0, and the fact that the latest conversion voltage data exist in the registers of the BMC903 and the Ampere processor 905 can be read is prompted. After the server is powered on, the CPLD901 is synchronously powered on, and the CPLD901 immediately controls the voltage acquisition module 902 to monitor the voltage and then starts to store data. When an operator presses a power-on key of the server, the Ampere processor 905 can read data buffered by the CPLD901 through the I2C _ A bus and print the data through the debugging serial port 907, so that operation and maintenance personnel can know the voltage condition of the mainboard in time conveniently. In addition, when the machine is started, the Ampere server can be manually controlled to enter a voltage monitoring interface in the BIOS configuration interface, and the Ampere processor 905 reads the data of the second register of the CPLD901 through I2C _ A and displays 40 paths of power supply voltage to the voltage monitoring interface in the BIOS configuration interface. The Ampere processor 905 checks the state of the PWR _ ADC _ INTn in an inquiry mode, and when the state of the PWR _ ADC _ INTn is checked to be 0, the voltage refresh data is known to exist, and the data is read again and the voltage monitoring interface in the BIOS configuration interface is updated. The Ampere processor 905 can view the registered state in the current CPLD901 through the general purpose input and output signals. The principle of the BMC903 reading data is the same as the amp re processor 905, and is not described herein. When the CPLD901 monitors that the voltage is abnormal and any status signal is abnormal, the CPLD901 controls the LED status indication module 906 to display an EE character, identifies that the voltage of the mainboard has a voltage fault, simultaneously informs the BMC903 of the fault alarm of the mainboard voltage through I2C _ E, and transmits the statuses of specific enable signals and Power Good signals to the BMC903 so as to record logs.

Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A server voltage monitoring method is applied to a complex programmable logic device, the complex programmable logic device is connected with a power supply of a server, and the method comprises the following steps:

when the server is monitored to be powered on, sending a control signal to a voltage acquisition module so that the voltage acquisition module acquires the voltage of a mainboard of the server;

receiving and storing voltage data returned by the voltage acquisition module;

and sending the voltage data to a target object, and informing the BMC to read the voltage data.

2. The method of claim 1, further comprising:

when the server is powered on in an alternating current mode, a second control signal is sent to the state monitoring module, so that the state monitoring module collects state signals of each power supply module on a server mainboard;

receiving state data returned by the state monitoring module;

adding the state data to the voltage data.

3. The method according to claim 1 or 2, characterized in that the method further comprises:

and informing a processor in a server to read the voltage data so that the processor reads the voltage data from the complex programmable logic device and displays the read voltage data on a BIOS configuration interface.

4. The method of claim 1, wherein prior to sending the voltage data to a target object and notifying a BMC to read the voltage data, the method further comprises:

storing a plurality of voltage data received for a preset number of continuous times, and removing the maximum data and the minimum data in the plurality of voltage data;

and calculating the average value of the residual voltage data to obtain preprocessed data, and taking the preprocessed data as the voltage data.

5. The method of claim 1, further comprising:

and judging whether the voltage data is abnormal or not based on a preset condition, if so, controlling an LED state indicating module to display a preset character, and sending an abnormal message to the BMC.

6. The method of claim 1, wherein the voltage data is stored in a first register in the complex programmable logic device, and wherein notifying the BMC to read the voltage data comprises:

and continuously sending a plurality of paths of general input and output signals to the BMC so that the BMC can acquire a first register state of the first register according to the plurality of paths of general input and output signals and read voltage data from the first register when the first register state represents updated voltage data.

7. The method of claim 3, wherein the voltage data is stored in a second register in the complex programmable logic device, and wherein notifying a processor in a server to read the voltage data comprises:

and continuously sending a plurality of paths of general input and output signals to a processor in the server, so that the processor in the server acquires a second register state of the second register according to the plurality of paths of general input and output signals, and reads the voltage data from the second register when the second register state represents the updated voltage data.

8. A server voltage monitoring apparatus, applied to a complex programmable logic device, the complex programmable logic device being connected to a power supply of a server, the apparatus comprising:

the control unit is used for sending a control signal to the voltage acquisition module when the server is monitored to be powered on so as to enable the voltage acquisition module to acquire the mainboard voltage of the server;

the data receiving unit is used for receiving and storing the voltage data returned by the voltage acquisition module;

and the data forwarding unit is used for sending the voltage data to a target object and informing the BMC to read the voltage data.

9. A server voltage monitoring system, comprising: the system comprises a complex programmable logic device, a voltage acquisition module and a BMC, wherein the complex programmable logic device is connected with a power supply of a server and is respectively in communication connection with the voltage acquisition module and the BMC; the complex programmable logic device having stored thereon computer instructions for causing the complex programmable logic device to thereby perform the method of any of claims 1-7.

10. The system of claim 9, further comprising:

the state monitoring module is in communication connection with the complex programmable logic device and is used for collecting state signals of each power supply module on the server mainboard;

the complex programmable logic device is in communication connection with a processor of the server.