CN103532728A - Method and device for resetting fault digital signal processor (DSP) chip - Google Patents
Method and device for resetting fault digital signal processor (DSP) chip Download PDFInfo
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- CN103532728A CN103532728A CN201210230442.6A CN201210230442A CN103532728A CN 103532728 A CN103532728 A CN 103532728A CN 201210230442 A CN201210230442 A CN 201210230442A CN 103532728 A CN103532728 A CN 103532728A
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Abstract
The invention belongs to the data communication field and relates to a method for resetting a fault digital signal processor (DSP) chip and a device for resetting the fault digital signal processor (DSP) chip. The method and the device for resetting the fault digital signal processor (DSP) chip are used for improving the utilization rate of digital signal processor (DSP) resource. The method for resetting the fault digital signal processor (DSP) chip comprises the following steps that: each digital signal processor (DSP) chip automatically acquires a first address identity (ID) of the chip, and then reports the first address identity (ID) to a system main control processor; and when the system main control processor finds that a fault occurs on a digital signal processor (DSP) chip, and software reset performed on the fault digital signal processor (DSP) chip fails, and no intra-board control processor exists in a digital signal processor (DSP) board, the system main control processor transmits a command for resetting the fault digital signal processor (DSP) chip to at least one non-fault digital signal processor (DSP) chip which is in the same digital signal processor (DSP) board with the fault digital signal processor (DSP) chip; and the fault digital signal processor (DSP) chip can be reset through the non-fault digital signal processor (DSP) chips. By means of the above technical schemes of the invention, influence on the work of the non-fault digital signal processor (DSP) chips in the same digital signal processor (DSP) board with the fault digital signal processor (DSP) chip, which is caused by resetting performed on the fault digital signal processor (DSP) chip, can be avoided, and therefore, the utilization rate of the digital signal processor (DSP) chip resource can be improved.
Description
Technical field
The present invention relates to data communication field, particularly a kind of method and device that fault dsp chip is resetted.
Background technology
Along with the development of the communication technology, the application of 3G and IP technology is more and more extensive, also more and more higher to the requirement of the disposal ability of telecommunication system and flexibility.Because the system architecture of telecommunication system is huger, therefore, for the ease of maintenance and the upgrading of telecommunication system, generally all telecommunication system is carried out to modularized design, wherein, part of module can add as required or reduce.
In the modularized design of telecommunication system, take digital signal processing module for being example, every digital signal panel, i.e. DSP(Digital Signal Processor, Digital Signal Processing) plate, there are a plurality of dsp processors the inside.In order to meet different traffic carrying capacity needs, in each telecommunication system, need again flexible configuration polylith dsp board.At present, conventionally with one, be independent of dsp board powerful external host processor in addition and manage and control a large amount of dsp boards, this external host processor is called " system master processor ".Fig. 1 is the structural representation of current telecommunication system.As shown in Figure 1, telecommunication system comprises: system master processor and dsp board.
System master processor is connected by serial high-speed-differential bus with dsp board, and system master processor carries out the operations such as program loading, condition monitoring and management, task distribution, fault detect and recovery to the dsp board in telecommunication system by serial high-speed-differential bus.
Conventionally, every dsp board inside has a processor, in this plate, control processor is responsible for reporting to system master processor the state information of each dsp chip in this dsp board, when having monitored dsp chip, break down, and when system master processor carries out software reset's failure by serial high-speed-differential bus to fault dsp chip, system master processor need to carry out external hardware reset to fault dsp chip by control processor in the plate of dsp board.
Because the program of dsp board loads and state monitoring and management can be completed by serial high-speed-differential bus by system master processor, therefore, in the plate of dsp board, control processor is not very important, be that some dsp board has control processor in plate, some dsp board is without control processor in plate, Fig. 2 is without the schematic diagram of the dsp board of control processor in plate, comprising: DSP address distributor, dsp chip, reseting logic unit.If dsp board is without control processor in plate, in dsp board, there is dsp chip to break down, when system master processor carries out software reset's failure by serial high-speed-differential bus to the dsp chip breaking down, system master processor can only carry out power-on and power-off reset operation to the monoblock dsp board at fault dsp chip place.Now, in the dsp board at fault dsp chip place, all dsp chips all will reset, and the fault dsp chip in this dsp board and non-fault dsp chip all will reset, and are unfavorable for so the efficient utilization of DSP resource.
Therefore, dsp board without plate in control processor, and system master processor carries out in the situation of software reset's failure by serial high-speed-differential bus to the dsp chip breaking down, if adopt prior art to reset to fault DSP, the normal operation of meeting impact and the non-fault dsp chip of fault dsp chip in same dsp board, the utilance of reduction DSP resource.
Summary of the invention
The embodiment of the present invention provides a kind of method and device that fault dsp chip is resetted, so that system master processor is when reset to fault dsp chip, do not affect the normal operation with the non-fault dsp chip of fault dsp chip in same dsp board, improve the utilance of DSP resource.
The concrete technical scheme that the embodiment of the present invention provides is as follows:
A method to fault digital signal processing DSP chip reset, comprising:
System master processor receives the first address designation ID that each dsp chip reports;
When system master processor has detected dsp chip and breaks down, the first address ID reporting based on each dsp chip, searches and the non-fault dsp chip of fault dsp chip in same dsp board;
System master processor, by with fault dsp chip at least one non-fault dsp chip in same dsp board, the indication that resets being sent to the reset logic module in described dsp board, indicates described reset logic module to reset to this fault dsp chip.
A method to fault digital signal processing DSP chip reset, comprising:
Dsp board reports the first address designation ID of each dsp chip of this plate to system master processor;
When the dsp chip in dsp board breaks down, at least one non-fault dsp chip being found by system master processor in described dsp board receives after the reset indication of system master processor transmission, described reset indication is mail to the reset logic module in this dsp board, indicate described reset logic module to reset to this fault dsp chip.
A processor, comprising:
Receiving element, the first address designation ID reporting for receiving each dsp chip;
Detecting unit, for detection of when having dsp chip to break down, the first address ID reporting based on each dsp chip, searches and the non-fault dsp chip of fault dsp chip in same dsp board;
Reset unit, for by with fault dsp chip at least one non-fault dsp chip in same dsp board, the indication that resets being sent to the reset logic module in described dsp board, indicates described reset logic module to reset to this fault dsp chip.
A dsp board, comprising:
DSP address distributor, is used to each dsp chip on dsp board to distribute the first address designation ID;
Dsp chip, for obtain first address ID of this dsp chip from described DSP address distributor, and reports described the first address ID to system master processor;
Reset logic module, while having dsp chip to break down for detecting when system master processor on dsp board, receiving system main control processor by send in the non-fault dsp chip of at least one of same dsp board with reset logic module, be used to indicate by the reset of non-fault dsp chip reset fault dsp chip and indicate, and according to described reset indication, fault dsp chip is resetted.
A device to fault digital signal processing DSP chip reset, comprising:
At least one dsp board, reports the first address designation ID of each dsp chip of this plate for the system master processor to this device;
System master processor, by serial high-speed-differential bus, be connected with described at least one dsp board, for detection of when having dsp chip to break down, the first address ID reporting based on each dsp chip, by with fault dsp chip at least one non-fault dsp chip in same dsp board, the indication that resets being sent to the reset logic module in described dsp board, indicate described reset logic module to reset to this fault dsp chip.
In the embodiment of the present invention, each dsp chip can this chip of automatic acquisition the first address ID (Identity, sign), then report system master processor, when system master processor has monitored dsp chip and has broken down, the dsp board at fault dsp chip place without plate in control processor, and system master processor resets in failed situation to fault dsp chip by software reset, the first address ID that system master processor reports to system master processor based on each dsp chip, order to the non-fault dsp chip transmission of at least one in the same dsp board reset fault dsp chip with fault dsp chip, by non-fault dsp chip, fault dsp chip is resetted.Thereby avoided dsp board at fault dsp chip place without plate in control processor, and system master processor carries out in the situation of software reset's failure by serial high-speed-differential bus to the dsp chip breaking down, because reset fault dsp chip carries out whole sheet reset to the dsp board at fault dsp chip place, thereby the work of impact and the non-fault dsp chip of fault dsp chip in same dsp board, has realized the effect that improves DSP resource utilization.
Accompanying drawing explanation
Fig. 1 is the structural representation of telecommunication system in the embodiment of the present invention;
Fig. 2 is without the structural representation of the digital signal panel (being dsp board) of control processor in plate in the embodiment of the present invention;
Fig. 3 is the illustrative view of functional configuration of system master processor in the embodiment of the present invention;
Fig. 4 is the illustrative view of functional configuration of dsp board in the embodiment of the present invention;
Fig. 5 is the flow chart that in the embodiment of the present invention, system master processor resets to fault dsp chip by non-fault dsp chip;
Fig. 6 is the structural representation of DSP treatment system in the embodiment of the present invention;
Fig. 7 is that in the embodiment of the present invention, dsp chip the first address ID is obtained schematic diagram.
Embodiment
When fault dsp chip is resetted, do not affect the work with the non-fault dsp chip of fault dsp chip in same dsp board, improve the utilance of DSP resource, in the embodiment of the present invention, each dsp chip can this chip of automatic acquisition the first address ID (Identity, sign), then report system master processor, when having monitored dsp chip, system master processor breaks down, the dsp board at fault dsp chip place without plate in control processor, and by software reset, fault dsp chip is resetted in failed situation, the first address ID that system master processor reports to system master processor based on each dsp chip, to send the order of reset fault dsp chip at least one non-fault dsp chip of same dsp board with fault dsp chip, by non-fault dsp chip, fault dsp chip is resetted.Thereby avoided dsp board at fault dsp chip place without plate in control processor, and system master processor carries out in the situation of software reset's failure by serial high-speed-differential bus to the dsp chip breaking down, because reset fault dsp chip carries out whole sheet reset to the dsp board at fault dsp chip place, thereby the work of impact and the non-fault dsp chip of fault dsp chip in same dsp board, realized the effect that improves DSP resource utilization, wherein, serial high-speed-differential bus can be Ethernet mode, also can be SRIO(Serial Rapid Input/Output, the input and output of serial high speed) mode or PCIE(Peripheral Component Interconnect Express, periphery component interconnection standard) mode, in actual applications, system master processor is generally connected with dsp board by Ethernet mode, be specially, system master processor is connected with dsp board by two passes, above-mentioned two passes can be divided into service channel and management channels function, service channel is used for service data transmission, management channels is used for transfer management data.In following examples, by ethernet management passage, be example.
Below in conjunction with accompanying drawing, the preferred embodiment of the present invention is elaborated.
Consult shown in Fig. 3, in the embodiment of the present invention, system master processor 10 comprises receiving element 101, detecting unit 102, reset unit 103, wherein,
Receiving element 101: the first address ID reporting for receiving each dsp chip;
Detecting unit 102: for detection of when having dsp chip to break down, the first address ID reporting based on each dsp chip, searches and the non-fault dsp chip of fault dsp chip in same dsp board;
Reset unit 103: for by with fault dsp chip at least one non-fault dsp chip in same dsp board, the indication that resets being sent to the reset logic module in described dsp board, make described reset logic module reset to this fault dsp chip.
Consult shown in Fig. 4, in the embodiment of the present invention, dsp board 11 comprises DSP address distributor 111, dsp chip 112, reset logic module 113, wherein,
Based on technique scheme, consult shown in Fig. 5, in the embodiment of the present invention, when the dsp board at fault dsp chip place without plate in the situation of control processor, system master processor is as follows by detailed process fault dsp chip being resetted with fault dsp chip at least one non-fault dsp chip in same dsp board:
Step 500: each dsp chip obtains first address ID of this chip from DSP address distributor.
When system starts, each dsp chip obtains first address ID of this chip from DSP address distributor.The first address ID is at least comprised of two parts, and a part is groove position ID, and another part is ID in plate.Groove position ID refers to the groove position at the dsp board place at dsp chip place, and dsp chip can be set pin according to the ID of dsp board groove position and directly read groove position ID.In plate, ID refers to the position of dsp chip on dsp board, and in plate, ID can represent with the low and high level of resistance setting, but is not limited to this expression mode.Dsp chip can obtain by the specific pin of this chip ID in the groove position ID of dsp board at this dsp chip place and the plate of this dsp chip place dsp board from DSP address distributor, then combine the first address ID of cost chip, specifically as shown in Figure 7, the first address ID of each dsp chip is unique in dsp system.The first address ID of each dsp chip, can change according to the change of the physical location of dsp chip (residing board and residing groove position thereof).
Step 510: each dsp chip reports first address ID of this chip to system master processor.
System master processor is connected with dsp board in Ethernet mode.After dsp system starts, each dsp chip is reported first address ID of this chip to system master processor by Ethernet in-band management passage.System master processor processed obtains after the first address ID of each dsp chip, is stored as the list of a DSP address ID, and is kept at holder the inside.System master processor can be grasped rapidly the topological structure of dsp chip by the list of DSP address ID.When a certain dsp board power-off, the address information of all dsp chips in the list of DSP address ID on the dsp board of power-off will be deleted.
Step 520: system master processor detects the operating state of each dsp chip by Ethernet in-band management passage, dsp chip detected and broken down.
The modes such as system master processor can be inquired about by heartbeat, access detect the state of each dsp chip.
Step 530: the first address ID that system master processor reports based on each dsp chip, search and the non-fault dsp chip of fault dsp chip in same dsp board.
When system master processor has detected dsp chip and has broken down, first by Ethernet in-band management passage, fault dsp chip is carried out to software reset, when resetting unsuccessfully by software reset to fault dsp chip, system master processor is searched the list of DSP address ID, finds out and the non-fault dsp chip of fault dsp chip in same dsp board.
Step 540: system master processor is by sending to reset logic module the indication that resets with fault dsp chip at least one non-fault dsp chip in same dsp board, and indication reset logic module resets to fault dsp chip.
On every dsp board, be all provided with a reset logic module, preferably, when dsp chip quantity on a dsp board is more, reset logic module can be used CPLD(Complex Programmable Logic Device, CPLD), during dsp chip negligible amounts on a dsp board, reset logic module can be used decoder logic device.
Dsp chip on same dsp board is by several IO(Input/Output, input and output) pin is controlled the input pin that pin is connected to reset logic module as resetting, reset logic module is all exported a pin to each dsp chip, is connected to the hardware reset pin of each dsp chip.
When system master processor is when resetting to fault dsp chip with the non-fault dsp chip of fault dsp chip in same dsp board, system master processor is told the second address ID of fault dsp chip and the non-fault dsp chip of fault dsp chip in same dsp board, non-fault dsp chip is controlled pin by reset and is told reset logic module the second address ID of fault dsp chip, reset logic module is carried out decoding according to the second address ID receiving, decision to which dsp chip resets, wherein, the second address ID that reset logic module receives can be the first address ID at least being combined by ID in groove position ID and plate, also can be only ID in plate.
The reset of dsp chip is controlled pin and is connected with the output pin of at least one dsp chip of this dsp chip in same dsp board by reset logic module, and the dsp chip in same dsp board can mutually be resetted.Therefore,, in same dsp board, the non-fault dsp chip that each fault dsp chip can be positioned at same dsp board by least one resets.
Further, if system master processor by searching the list of DSP address ID, without non-fault DSP and fault DSP being detected in same dsp board time, system master processor carries out whole sheet reset by the dsp board at fault dsp chip place.
System master processor has multiple by mode fault dsp chip being resetted with fault dsp chip at least one non-fault dsp chip in same dsp board.
For example, system master processor resets to fault dsp chip with the non-fault dsp chip of fault dsp chip in same dsp board by one.
For example, system master processor resets to fault dsp chip with the non-fault dsp chip of fault dsp chip in same dsp board successively by a plurality of.
Again for example, system master processor resets to fault dsp chip with the non-fault dsp chip of fault dsp chip in same dsp board by a plurality of simultaneously.
Further, if all dsp chips on a dsp board all break down, system master processor will carry out whole sheet reset to this dsp board.
Further, if after fault dsp chip being resetted with fault dsp chip at least one non-fault dsp chip in same dsp board, fault dsp chip is still during cisco unity malfunction, and system master processor carries out whole sheet reset by the dsp board at fault dsp chip place.
The generation of this misoperation situation resetting for fear of fault dsp chip pair and the non-fault dsp chip of fault dsp chip in same dsp board, can be in reset logic module, do certain constraint, for example, take when the non-fault dsp chip of at least two in same dsp board resets to fault dsp chip with fault dsp chip, this resets just effective.
Based on above-described embodiment, with the fault DSP3 chip of the dsp board 1B in Fig. 6, reset above-described embodiment is described further below.
When system starts, each dsp chip obtains first address ID of this chip from DSP address distributor.System master processor is connected with dsp board in Ethernet mode, after system starts, each dsp chip reports first address ID of this chip to system master processor by Ethernet in-band management passage, system master processor obtains after the first address ID of each dsp chip, is stored as the list of a DSP address ID.System master processor is inquired about with heartbeat by Ethernet in-band management passage, and the modes such as access detect the state of each dsp chip, and the DSP3 chip that dsp board 1B detected breaks down.
After the DSP3 chip that system master processor detects dsp board 1B breaks down, first by Ethernet in-band management passage 1A, fault DSP3 chip is carried out to software reset, when failed to fault DSP3 chip reset by software reset, system master processor is searched the list of DSP address ID, find the DSP1 chip that moving and fault DSP3 chip in same dsp board 1B, system master processor, by Ethernet in-band management passage 1A, sends the order of reset fault DSP3 chip to non-fault DSP1 chip.Non-fault DSP1 chip receives after the order of the reset fault DSP3 chip that system master processor sends, by reset control line 1S, to reset logic module, send the second address ID of fault DSP3 chip, wherein, the second address ID that reset logic module receives can be,, by the first address ID that in the groove position ID at the dsp board 1B place at fault DSP3 chip place and the plate of fault DSP3 chip in dsp board 1B, ID combines, can be at least only also ID in the plate of fault DSP3 chip in dsp board 1B.Reset logic module receives the laggard row decoding of the second address ID of fault DSP3 chip, then by reset control line 3R, fault DSP3 chip is resetted.
System master processor has multiple by mode fault DSP3 chip being resetted with fault DSP3 chip at least one non-fault dsp chip in same dsp board 1B.
For example, system master processor resets to fault DSP3 chip with the non-fault dsp chip of fault DSP3 chip in same dsp board 1B by one.
For example, system master processor resets to fault DSP3 chip with the non-fault dsp chip of fault DSP3 chip in same dsp board 1B successively by a plurality of.
Again for example, system master processor resets to fault DSP3 chip with the non-fault dsp chip of fault DSP3 chip in same dsp board 1B by a plurality of simultaneously.
Further, if system master processor by searching the list of DSP address ID, without non-fault DSP and fault DSP3 being detected in same dsp board 1B time, system master processor carries out whole sheet reset by the dsp board 1B at fault DSP3 chip place.
Further, if all dsp chips on monoblock dsp board 1B all break down, system master processor will carry out whole sheet reset monoblock dsp board 1B.
Further, if after fault DSP3 chip being resetted with the non-fault DSP1 chip of fault DSP3 chip in same dsp board 1B, fault DSP3 chip is still during cisco unity malfunction, and system master processor is carrying out whole sheet reset on the dsp board 1B at fault DSP3 chip place.
In sum, in the embodiment of the present invention, each dsp chip can this chip of automatic acquisition the first address ID (Identity, sign), then report system master processor, when finding that there is dsp chip, system master processor breaks down, by software reset, fault dsp chip is resetted unsuccessfully, and in the situation that the dsp board at fault dsp chip place is without control processor in plate, the first address ID that system master processor reports to system master processor based on each dsp chip, to send the order of reset fault dsp chip at least one non-fault dsp chip of same dsp board with fault dsp chip, by non-fault dsp chip, fault dsp chip is resetted.Thereby avoided because reset fault dsp chip carries out whole sheet reset to the dsp board at fault dsp chip place, thereby the work of impact and the non-fault dsp chip of fault dsp chip in same dsp board has realized the effect that improves DSP resource utilization.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (31)
1. the method to fault digital signal processing DSP chip reset, is characterized in that, comprising:
System master processor receives the first address designation ID that each dsp chip reports;
When system master processor has detected dsp chip and breaks down, the first address ID reporting based on each dsp chip, searches and the non-fault dsp chip of fault dsp chip in same dsp board;
System master processor, by with fault dsp chip at least one non-fault dsp chip in same dsp board, the indication that resets being sent to the reset logic module in described dsp board, indicates described reset logic module to reset to this fault dsp chip.
2. the method for claim 1, it is characterized in that, described the first address ID that system master processor receives is obtained from DSP address distributor by each dsp chip, and the first address ID of any one dsp chip at least comprises the groove position ID of dsp board and the interior ID of the plate of this any one dsp chip at this any one dsp chip place.
3. the method for claim 1, is characterized in that, system master processor search with the non-fault dsp chip of fault dsp chip in same dsp board before, also comprise:
First by serial high-speed-differential bus, fault dsp chip is carried out to software reset, confirm software reset's failure.
4. method as claimed in claim 3, is characterized in that, also comprises:
System master processor is being searched less than during the non-fault dsp chip in same dsp board, the dsp board at fault dsp chip place being carried out to whole sheet reset with fault dsp chip.
5. the method as described in claim 1,2 or 3, is characterized in that, system master processor is sent to the reset logic module in described dsp board by the indication that resets, and comprising:
System master processor is by a non-fault dsp chip in same dsp board is sent to the reset logic module in described dsp board by the indication that resets with fault dsp chip; Or
System master processor by with a plurality of non-fault dsp chip of fault dsp chip in same dsp board by the indication synchronized transmission that resets to the reset logic module in described dsp board; Or
System master processor is by being sent to successively the reset logic module in described dsp board with a plurality of non-fault dsp chip of fault dsp chip in same dsp board by the indication that resets.
6. the method as described in claim 1,2 or 3, is characterized in that, also comprises:
If system master processor is sent to the reset logic module in described dsp board by the indication that resets, after indicating described reset logic module to reset to this fault dsp chip, fault dsp chip is still during cisco unity malfunction, and system master processor carries out whole sheet reset by the dsp board at fault dsp chip place.
7. the method to fault digital signal processing DSP chip reset, is characterized in that, comprising:
Dsp board reports the first address designation ID of each dsp chip of this plate to system master processor;
When the dsp chip in dsp board breaks down, at least one non-fault dsp chip being found by system master processor in described dsp board receives after the reset indication of system master processor transmission, described reset indication is mail to the reset logic module in this dsp board, indicate described reset logic module to reset to this fault dsp chip.
8. method as claimed in claim 7, it is characterized in that, described first address ID of each dsp chip of this plate that dsp board reports to system master processor, by each dsp chip, from DSP address distributor, obtained, and the first address ID of any one dsp chip at least comprises the groove position ID of dsp board and the interior ID of the plate of this any one dsp chip at this any one dsp chip place.
9. method as claimed in claim 7, is characterized in that, also comprises:
If system master processor does not find the non-fault dsp chip in described dsp board, the reset logic module in described dsp board, according to the further indication of system master processor, is carried out whole sheet reset by this dsp board.
10. method as claimed in claim 7 or 8, is characterized in that, at least one non-fault dsp chip is sent to the reset logic module in this dsp board by described reset indication, comprising:
A non-fault dsp chip is sent to the reset logic module in this dsp board by described reset indication; Or
A plurality of non-fault dsp chips are sent to the reset logic module in this dsp board by described reset indication successively; Or
A plurality of non-fault dsp chips are synchronously sent to the reset logic module in this dsp board by described reset indication.
11. methods as claimed in claim 10, is characterized in that, when the reset logic module in dsp board determines that receiving system master processor indicates by the reset of at least two non-fault dsp chips transmissions of this plate, determine this reset indication effectively.
12. methods as claimed in claim 10, is characterized in that, also comprise:
If the reset logic module in dsp board receives system master processor and indicates by the reset of at least one non-fault dsp chip transmission of this plate, after fault dsp chip is resetted, fault dsp chip is still during cisco unity malfunction,, according to the indication of system master processor, this plate is carried out to whole sheet reset.
13. 1 kinds of system master processors, is characterized in that, comprising:
Receiving element, the first address designation ID reporting for receiving each dsp chip;
Detecting unit, for detection of when having dsp chip to break down, the first address ID reporting based on each dsp chip, searches and the non-fault dsp chip of fault dsp chip in same dsp board;
Reset unit, for by with fault dsp chip at least one non-fault dsp chip in same dsp board, the indication that resets being sent to the reset logic module in described dsp board, indicates described reset logic module to reset to this fault dsp chip.
14. system master processors as claimed in claim 13, it is characterized in that, described the first address ID that receiving element receives is obtained from DSP address distributor by each dsp chip, and the first address ID of any one dsp chip at least comprises the groove position ID of dsp board and the interior ID of the plate of this any one dsp chip at this any one dsp chip place.
15. system master processors as claimed in claim 13, is characterized in that, reset unit is further used for:
Detecting unit search with the non-fault dsp chip of fault dsp chip in same dsp board before, first by serial high-speed-differential bus, fault dsp chip is carried out to software reset, confirm software reset's failure.
16. system master processors as claimed in claim 15, is characterized in that, reset unit is further used for:
At detecting unit, search less than during the non-fault dsp chip in same dsp board, the dsp board at fault dsp chip place being carried out to whole sheet reset with fault dsp chip.
17. system master processors as described in claim 13,14 or 15, is characterized in that, reset unit is used for:
While being sent to the reset logic module in described dsp board by indicating resetting with fault dsp chip at least one non-fault dsp chip in same dsp board, by a non-fault dsp chip in same dsp board is sent to the reset logic module in described dsp board by the indication that resets with fault dsp chip; Or, by the indication that resets being sent to the reset logic module in described dsp board successively with a plurality of non-fault dsp chip of fault dsp chip in same dsp board; Or, by with a plurality of non-fault dsp chip of fault dsp chip in same dsp board by the indication synchronized transmission that resets to the reset logic module in described dsp board.
18. system master processors as claimed in claim 17, is characterized in that, reset unit is further used for:
The first address ID reporting based on each dsp chip, when the non-fault dsp chip of at least two in same dsp board is sent to the reset logic module in described dsp board by the indication that resets with fault dsp chip, make reset that described reset logic module carries out this fault dsp chip just effectively.
19. system master processors as claimed in claim 18, is characterized in that, reset unit is further used for:
If indication is sent to the reset logic module in described dsp board by resetting, after indicating described reset logic module to reset to this fault dsp chip, fault dsp chip still during cisco unity malfunction, carries out whole sheet reset by the dsp board at fault dsp chip place.
20. 1 kinds of Digital Signal Processing dsp boards, is characterized in that, comprising:
DSP address distributor, is used to each dsp chip on dsp board to distribute the first address designation ID;
Dsp chip, for obtain first address ID of this dsp chip from described DSP address distributor, and reports described the first address ID to system master processor;
Reset logic module, while having dsp chip to break down for detecting when system master processor on dsp board, receiving system main control processor by send in the non-fault dsp chip of at least one of same dsp board with reset logic module, be used to indicate by the reset of non-fault dsp chip reset fault dsp chip and indicate, and according to described reset indication, fault dsp chip is resetted.
21. dsp boards as claimed in claim 20, is characterized in that, DSP address distributor is the groove position ID of dsp board and the interior ID of the plate of each dsp chip that the first address ID of each dsp chip distribution on described dsp board at least comprises each dsp chip place.
22. dsp boards as claimed in claim 20, is characterized in that, reset logic module is further used for:
The first address ID reporting based on each dsp chip when system master processor, search in the process of the non-fault dsp chip in described dsp board, if do not find non-fault dsp chip,, according to the further indication of system master processor, this dsp board is carried out to whole sheet reset.
23. dsp boards as described in claim 20 or 21, is characterized in that, reset logic module is further used for:
Receiving system main control processor is indicated by the reset that the non-fault dsp chip of in same dsp board sends with reset logic module; Or receiving system main control processor is by indicating with the reset of a plurality of non-fault dsp chip transmission of reset logic module in same dsp board successively; Or synchronous receiving system main control processor is by indicating with the reset of a plurality of non-fault dsp chip transmission of reset logic module in same dsp board.
24. dsp boards as claimed in claim 23, is characterized in that, reset logic module is further used for:
When system master processor has detected dsp chip and has broken down, determine while receiving the reset indication that system master processor sends by the non-fault dsp chip of at least two in same dsp board with reset logic module, determine that this resets indication is effective.
25. dsp boards as claimed in claim 23, is characterized in that, reset logic module is further used for:
According to system master processor, by the reset sending in the non-fault dsp chip of at least one of same dsp board with reset logic module, indicate, after fault dsp chip is resetted, fault dsp chip is still during cisco unity malfunction,, according to the further indication of system master processor, this dsp board is carried out to whole sheet reset.
26. 1 kinds of devices to fault digital signal processing DSP chip reset, is characterized in that, comprising:
At least one dsp board, reports the first address designation ID of each dsp chip of this plate for the system master processor to this device;
System master processor, by serial high-speed-differential bus, be connected with described at least one dsp board, for detection of when having dsp chip to break down, the first address ID reporting based on each dsp chip, by with fault dsp chip at least one non-fault dsp chip in same dsp board, the indication that resets being sent to the reset logic module in described dsp board, indicate described reset logic module to reset to this fault dsp chip.
27. devices as claimed in claim 26, is characterized in that, described dsp board comprises DSP address distributor, a plurality of dsp chip and reset logic module, wherein
DSP address distributor, by IO pin, be connected with each dsp chip, be used to each dsp chip on the dsp board at DSP address distributor place to distribute the first address ID, wherein, described the first address ID at least comprises ID in the groove position ID of dsp board at each dsp chip place and the plate of each dsp chip;
Dsp chip, by IO pin, be connected with described DSP address distributor, by IO pin, be connected with described reset logic module with hardware reset pin, and be connected with described system master processor by serial high-speed-differential bus, for obtaining first address ID of this dsp chip from described DSP address distributor, and this first address ID is reported to described system master processor;
Reset logic module, by IO input pin, be connected with the IO pin of each dsp chip, and be connected with the hardware reset pin of each dsp chip by IO output pin, while having dsp chip to break down for detecting when system master processor on dsp board, receiving system main control processor by send in the non-fault dsp chip of at least one of same dsp board with reset logic module, be used to indicate by the reset of non-fault dsp chip reset fault dsp chip and indicate, and according to described reset indication, fault dsp chip is resetted.
28. devices as claimed in claim 26, is characterized in that, described system master processor is used for:
While being sent to the reset logic module in described dsp board by indicating resetting with fault dsp chip at least one non-fault dsp chip in same dsp board, by a non-fault dsp chip in same dsp board is sent to the reset logic module in described dsp board by the indication that resets with fault dsp chip; Or, by with a plurality of non-fault dsp chip of fault dsp chip in same dsp board by the indication synchronized transmission that resets to the reset logic module in described dsp board; Or, by the indication that resets being sent to the reset logic module in described dsp board successively with a plurality of non-fault dsp chip of fault dsp chip in same dsp board.
29. devices as claimed in claim 28, is characterized in that, described system master processor is further used for:
By the indication that resets being sent to the reset logic module in described dsp board with fault dsp chip at least one non-fault dsp chip in same dsp board, make before described reset logic module resets to this fault dsp chip, first by serial high-speed-differential bus, fault dsp chip is carried out to software reset, confirm software reset's failure.
30. devices as claimed in claim 29, is characterized in that, described system master processor is further used for:
System master processor is being searched less than during the non-fault dsp chip in same dsp board, the dsp board at fault dsp chip place being carried out to whole sheet reset with fault dsp chip.
31. devices as described in claim 28 or 29, is characterized in that, described system master processor is further used for:
By the indication that resets being sent to the reset logic module in described dsp board with fault dsp chip at least one non-fault dsp chip in same dsp board, after indicating described reset logic module to reset to this fault dsp chip, fault dsp chip still during cisco unity malfunction, carries out whole sheet reset by the dsp board at fault dsp chip place.
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| CN201210230442.6A CN103532728B (en) | 2012-07-04 | 2012-07-04 | A kind of method and device resetted to failure dsp chip |
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| CN201210230442.6A CN103532728B (en) | 2012-07-04 | 2012-07-04 | A kind of method and device resetted to failure dsp chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105279133A (en) * | 2015-10-20 | 2016-01-27 | 电子科技大学 | VPX parallel DSP signal processing board card based on SoC online reconstruction |
| CN108228374A (en) * | 2017-12-28 | 2018-06-29 | 华为技术有限公司 | A kind of fault handling method of equipment, apparatus and system |
| CN111669220A (en) * | 2020-05-22 | 2020-09-15 | 中国人民解放军国防科技大学 | RapidIO communication blockage repair method and system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1311960A (en) * | 1998-08-06 | 2001-09-05 | 艾利森电话股份有限公司 | Fault control and restoration in a data communication system |
| CN101662791A (en) * | 2009-09-29 | 2010-03-03 | 中兴通讯股份有限公司 | Failure information processing method, device and system |
| CN101820359A (en) * | 2010-03-09 | 2010-09-01 | 杭州华三通信技术有限公司 | Fault processing method and equipment for network equipment |
| CN102004535A (en) * | 2009-09-02 | 2011-04-06 | 康佳集团股份有限公司 | Electronic system and resetting method thereof |
-
2012
- 2012-07-04 CN CN201210230442.6A patent/CN103532728B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1311960A (en) * | 1998-08-06 | 2001-09-05 | 艾利森电话股份有限公司 | Fault control and restoration in a data communication system |
| CN102004535A (en) * | 2009-09-02 | 2011-04-06 | 康佳集团股份有限公司 | Electronic system and resetting method thereof |
| CN101662791A (en) * | 2009-09-29 | 2010-03-03 | 中兴通讯股份有限公司 | Failure information processing method, device and system |
| CN101820359A (en) * | 2010-03-09 | 2010-09-01 | 杭州华三通信技术有限公司 | Fault processing method and equipment for network equipment |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105279133A (en) * | 2015-10-20 | 2016-01-27 | 电子科技大学 | VPX parallel DSP signal processing board card based on SoC online reconstruction |
| CN105279133B (en) * | 2015-10-20 | 2017-10-31 | 电子科技大学 | VPX Parallel DSP Signal transacting board analysis based on SoC on-line reorganizations |
| CN108228374A (en) * | 2017-12-28 | 2018-06-29 | 华为技术有限公司 | A kind of fault handling method of equipment, apparatus and system |
| US11144416B2 (en) | 2017-12-28 | 2021-10-12 | Huawei Technologies Co., Ltd. | Device fault processing method, apparatus, and system |
| CN111669220A (en) * | 2020-05-22 | 2020-09-15 | 中国人民解放军国防科技大学 | RapidIO communication blockage repair method and system |
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| CN103532728B (en) | 2018-05-29 |
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