CN114510891A - Circuit simulation method, circuit simulation device, medium, and electronic apparatus - Google Patents
Circuit simulation method, circuit simulation device, medium, and electronic apparatus Download PDFInfo
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
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Abstract
The invention provides a circuit simulation method, a circuit simulation device, a medium and an electronic device. The circuit simulation method comprises the following steps: acquiring a circuit netlist of the target integrated circuit as a first circuit netlist, wherein the first circuit netlist comprises internal nodes and port nodes; processing the first circuit netlist to obtain a node to be reserved in the first circuit netlist, wherein the RC time constant of the node to be reserved is larger than the average RC time constant of the internal nodes of the first circuit netlist; removing the node to be reserved from the internal node of the first circuit netlist, and adding the node to be reserved into a port node of the first circuit netlist to generate a second circuit netlist; carrying out reduction processing on the second circuit netlist to obtain an equivalent circuit; and performing circuit simulation on the equivalent circuit through a circuit simulator of the electronic equipment. The method can reduce the calculation amount in the simulation process of the large-scale integrated circuit and reduce the simulation complexity.
Description
Technical Field
The present invention relates to a circuit simulation method, and more particularly, to a circuit simulation method, a circuit simulation apparatus, a medium, and an electronic device.
Background
Post-circuit simulation typically simulates a full circuit, typically using an emulated circuit simulator, where the full circuit contains a logic circuit and an RC network built after parasitic extraction. In an integrated circuit, the presence of a parasitic network greatly increases the scale of the circuit network, thus resulting in a substantial increase in the cost of simulation calculations.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a circuit simulation method, a circuit simulation apparatus, a medium and an electronic device, which are used to solve the problem of excessive simulation computation cost in the prior art.
To achieve the above and other related objects, a first aspect of the present invention provides a circuit simulation method applied to an electronic device for simulating a target integrated circuit, the method comprising: acquiring a circuit netlist of the target integrated circuit as a first circuit netlist, wherein the first circuit netlist comprises internal nodes and port nodes; processing the first circuit netlist to obtain a node to be reserved in the first circuit netlist, wherein the RC time constant of the node to be reserved is larger than the average RC time constant of the internal nodes of the first circuit netlist; removing the node to be reserved from the internal node of the first circuit netlist, and adding the node to be reserved into a port node of the first circuit netlist to generate a second circuit netlist; performing a reduction process on the second circuit netlist to obtain an equivalent circuit, the reduction process comprising: obtaining equivalent capacitance and/or equivalent resistance between port nodes of the second circuit netlist, eliminating internal nodes of the second circuit netlist and resistance and/or capacitance elements connected with the internal nodes of the second circuit netlist, and adding the equivalent capacitance and/or the equivalent resistance between the port nodes of the second circuit netlist; and performing circuit simulation on the equivalent circuit through a circuit simulator of the electronic equipment.
In an embodiment of the first aspect, the equivalent circuit is a passive RC circuit.
In an embodiment of the first aspect, an implementation method for processing the first circuit netlist to obtain a node to be reserved therein includes: obtaining the average RC time constant; and searching internal nodes in the first circuit netlist according to the average RC time constant to obtain nodes with RC time constants larger than the average RC time constant as the nodes to be reserved.
In an embodiment of the first aspect, an implementation method for searching internal nodes in the first circuit netlist according to the average RC time constant to obtain a node with an RC time constant greater than the average RC time constant as the node to be reserved includes: step S1, randomly acquiring a node in the first circuit netlist as a random internal node, judging whether the RC time constant of the random internal node is smaller than the average RC time constant, and if the RC time constant of the random internal node is smaller than the average RC time constant, re-acquiring the random internal node; step S2, searching the first circuit netlist through a breadth-first search algorithm based on the random internal nodes and the search radius, and judging whether the nodes searched by the breadth-first search algorithm meet the conditions, if the searched nodes belong to the points to be reserved, the searched nodes and/or the non-ground port nodes, judging that the searched nodes do not meet the conditions, otherwise, judging that the searched nodes meet the conditions; step S3, when the searched node meets the condition, the searched node is marked as the searched node, and the random internal node is marked as the node to be reserved and the searched node; and step S4, if the times that the searched nodes meet the conditions are different from the preset times, the step S1 is switched to, otherwise, the nodes to be reserved are obtained.
In an embodiment of the first aspect, the circuit simulation method further includes: the search radius is obtained in response to the received instruction.
In an embodiment of the first aspect, the method for obtaining an equivalent capacitance and/or an equivalent resistance between port nodes of the second circuit netlist includes: acquiring a conductance matrix and a capacitance matrix of an internal circuit of the second circuit netlist, and a conductance connection matrix and a capacitance connection matrix of the internal circuit and a port node of the second circuit netlist; and obtaining the equivalent resistance and/or the equivalent capacitance according to the conductance matrix, the capacitance matrix, the conductance connection matrix and the capacitance connection matrix.
In an embodiment of the first aspect, the circuit simulation method further includes: and displaying a circuit simulation result by using a display of the electronic equipment.
A second aspect of the present invention provides a circuit simulation apparatus, comprising: a circuit netlist obtaining unit, configured to obtain a circuit netlist of the target integrated circuit as a first circuit netlist, where the first circuit netlist includes an internal node and a port node; the first circuit netlist processing unit is used for processing the first circuit netlist to obtain a node to be reserved in the first circuit netlist, and the RC time constant of the node to be reserved is larger than the average RC time constant of internal nodes of the first circuit netlist; the second circuit netlist generation unit is used for removing the node to be reserved from the internal node of the first circuit netlist and adding the node to be reserved into the port node of the first circuit netlist to generate a second circuit netlist; a second circuit netlist processing unit, configured to perform reduction processing on the second circuit netlist to obtain an equivalent circuit, where the reduction processing includes: obtaining equivalent capacitance and/or equivalent resistance between port nodes of the second circuit netlist, eliminating internal nodes of the second circuit netlist and resistance and/or capacitance elements connected with the internal nodes of the second circuit netlist, and adding the equivalent capacitance and/or the equivalent resistance between the port nodes of the second circuit netlist; and the circuit simulation unit is used for carrying out circuit simulation on the equivalent circuit through a circuit simulator of the electronic equipment.
A third aspect of the invention provides a computer readable storage medium, which when executed by a processor implements the circuit simulation method of any of the first aspects of the invention.
A fourth aspect of the present invention provides an electronic apparatus, comprising: a memory having a computer program stored thereon; a processor, communicatively coupled to the memory, for executing the circuit simulation method according to any of the first aspect of the present invention when the computer program is invoked.
As described above, the circuit simulation method, the circuit simulation apparatus, the medium, and the electronic device according to the present invention have the following advantageous effects:
the circuit simulation method can obtain a second circuit netlist according to a first circuit netlist of a target integrated circuit, and obtain an equivalent circuit of the target integrated circuit according to the second circuit netlist. The process of obtaining the equivalent circuit comprises the steps of carrying out reduction processing on the second circuit netlist, eliminating internal nodes of the second circuit netlist and the like, so that the complexity of the equivalent circuit is lower than that of the target integrated circuit, and therefore, the calculation amount in the simulation process can be reduced and the simulation complexity can be reduced by carrying out circuit simulation based on the equivalent circuit.
Drawings
FIG. 1 is a flow chart of a circuit simulation method according to an embodiment of the present invention.
Fig. 2 is a flowchart illustrating an implementation of a method for acquiring a node to be removed according to an embodiment of the present invention.
Fig. 3 is a flowchart illustrating an implementation of a method for obtaining a node with an RC time constant greater than an average RC time constant according to an embodiment of the present invention.
FIG. 4 is a flowchart of an embodiment of a method for reducing a second netlist according to the present invention.
FIG. 5 is a flow chart of a circuit simulation method according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a circuit simulation apparatus according to an embodiment of the invention.
Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the invention.
Description of the element reference numerals
600 circuit simulation device
610 circuit netlist obtaining unit
620 first circuit netlist processing unit
630 second circuit netlist generation unit
640 second circuit netlist processing unit
650 circuit simulation unit
700 electronic device
710 memory
720 processor
S11-S15 steps
S21-S22 steps
S31-S34 steps
S41-S42 steps
S51-S55 steps
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, amount and proportion of each component in actual implementation can be changed freely, and the layout of the components can be more complicated.
In the existing circuit simulation method, the cost of simulation calculation is too high, so that the method is difficult to be directly applied to large-scale simulation. In view of the above problems, the present invention provides a circuit simulation method, which is capable of obtaining a second circuit netlist according to a first circuit netlist of a target integrated circuit, and obtaining an equivalent circuit of the target integrated circuit according to the second circuit netlist. The process of obtaining the equivalent circuit comprises the steps of carrying out reduction processing on the second circuit netlist, eliminating internal nodes of the second circuit netlist and the like, so that the complexity of the equivalent circuit is lower than that of the target integrated circuit, and therefore, the calculation amount in the simulation process can be reduced and the simulation complexity can be reduced by carrying out circuit simulation based on the equivalent circuit.
In an embodiment of the invention, the circuit simulation method is applied to an electronic device for simulating a target integrated circuit. Specifically, referring to fig. 1, the circuit simulation method includes:
s11, obtaining the circuit netlist of the target integrated circuit as a first circuit netlist, wherein the first circuit netlist comprises internal nodes and port nodes. The first circuit netlist is an undirected graph, and a ground node in the first circuit netlist is a port node.
Optionally, in this embodiment, the internal nodes of the first circuit netlist may be internal nodes sequentially numbered according to a range 1-K, and the port nodes of the first circuit netlist may be port nodes sequentially numbered according to a range 1-M, where K is a total number of the internal nodes of the first circuit netlist and M is a total number of the port nodes of the first circuit netlist.
S12, processing the first circuit netlist to obtain a node to be reserved therein, wherein the RC time constant of the node to be reserved is larger than the average RC time constant of the internal nodes of the first circuit netlist. The RC time constant represents a constant of a time process of a transient reaction, and in an RC circuit, it is a product of resistance and capacitance, and the RC circuit is also called a resistance-capacitance circuit, and a primary RC circuit is composed of a resistor and a capacitor.
Optionally, this embodiment may search the first circuit netlist through a breadth-first algorithm to obtain the node to be reserved, where an RC time constant of the node to be reserved is greater than an average RC time constant of the first circuit netlist.
S13, removing the node to be reserved from the internal node of the first circuit netlist, and adding the node to be reserved into the port node of the first circuit netlist to generate a second circuit netlist. Since the node to be reserved is a node which seriously affects the precision of the reduced RC circuit, the precision of the reduced RC circuit can be improved by removing the node to be reserved and adding the node to be reserved to the port node of the first circuit netlist.
S14, performing a reduction process on the second circuit netlist to obtain an equivalent circuit, where the reduction process includes: and acquiring equivalent capacitance and/or equivalent resistance between port nodes of the second circuit netlist, eliminating internal nodes of the second circuit netlist and resistance and/or capacitance elements connected with the internal nodes of the second circuit netlist, and adding the equivalent capacitance and/or the equivalent resistance between the port nodes of the second circuit netlist.
By eliminating the internal nodes of the second circuit netlist and the resistance and/or capacitance elements connected with the internal nodes of the second circuit netlist and adding additional resistance and/or capacitance elements between the port nodes of the second circuit netlist, the number of state variables of the target integrated circuit can be reduced, thereby realizing the reduction of the circuit model and improving the calculation efficiency of the simulation. In addition, the equivalent circuit has performance similar to that of the target integrated circuit, can ensure passivity, and can be conveniently applied to integrated circuit simulation scenes.
And S15, performing circuit simulation on the equivalent circuit through a circuit simulator of the electronic equipment.
Optionally, the circuit simulation method in this embodiment may further include: and displaying a circuit simulation result by using a display of the electronic equipment.
As can be seen from the above description, the circuit simulation method according to this embodiment can obtain the second circuit netlist according to the first circuit netlist of the target integrated circuit, and obtain the equivalent circuit of the target integrated circuit according to the second circuit netlist. The process of obtaining the equivalent circuit comprises the steps of reducing the second circuit netlist, eliminating internal nodes of the second circuit netlist and the like, so that the complexity of the equivalent circuit is lower than that of the target integrated circuit, the calculation amount in the simulation process can be reduced by performing circuit simulation based on the equivalent circuit, and the simulation complexity is reduced.
Referring to fig. 2, in an embodiment of the present invention, an implementation method for processing the first circuit netlist to obtain a node to be reserved therein includes:
and S21, acquiring the average RC time constant. Wherein the average RC time constant is an average value of RC time constants of internal nodes in the first circuit netlist.
And S22, searching the internal nodes in the first circuit netlist according to the average RC time constant to obtain the nodes with the RC time constants larger than the average RC time constant as the nodes to be reserved.
Optionally, in the present embodiment, in an iterative process of breadth-first search, it may be determined whether an RC time constant of an initial search starting point is smaller than the average RC time constant, if not, the search process is continued, and if yes, the initial search starting point is regenerated, where the initial search starting point is an internal node of the first circuit netlist.
As can be known from the above description, the algorithm of this embodiment can search internal nodes in the first circuit netlist according to the average RC time constant to obtain nodes with RC time constants greater than the average RC time constant as the nodes to be retained, where the nodes to be retained are nodes that seriously affect the precision of the reduced RC circuit.
Referring to fig. 3, in an embodiment of the present invention, an implementation method for searching internal nodes in the first circuit netlist according to the average RC time constant to obtain a node with an RC time constant greater than the average RC time constant as the node to be reserved includes:
s31, randomly acquiring a node in the first circuit netlist as a random internal node, judging whether the RC time constant of the random internal node is smaller than the average RC time constant, and if the RC time constant of the random internal node is smaller than the average RC time constant, re-acquiring the random internal node. The method for generating the random internal node may be: acquiring the total number K of internal nodes of the first circuit netlist, wherein the internal nodes of the first circuit netlist are the internal nodes which are sequentially numbered according to the range of 1-K; acquiring a random number i generated according to the average probability, wherein the value range of i is 1-K; and acquiring the internal node with the number i as the random internal node.
S32, searching the first circuit netlist through a breadth-first search algorithm based on the random internal nodes and the search radius, judging whether the nodes searched by the breadth-first search algorithm meet the conditions, if the searched nodes belong to the points to be reserved, the searched nodes and/or the non-ground port nodes, judging that the searched nodes do not meet the conditions, and if not, judging that the searched nodes meet the conditions.
Optionally, in the search process of the breadth-first search algorithm, node search may be expanded based on the search radius, if the searched node is a node to be reserved, a searched node, and/or a non-ground port node, the number of times of search failure is increased by 1, and if the number of times of search failure reaches an upper limit, the search radius is decreased by 1, the number of times of search failure is initialized, and search is expanded again.
S33, when the searched node meets the condition, the searched node is marked as the searched node, and the random internal node is marked as the node to be reserved and the searched node.
And S34, if the times that the searched nodes meet the conditions are different from the preset times, turning to the step S1, otherwise, acquiring the nodes to be reserved.
As can be seen from the above description, the algorithm described in this embodiment searches the first circuit netlist through a breadth-first search algorithm to obtain nodes to be retained, the algorithm can obtain a plurality of nodes to be retained at one time, and because the algorithm is based on search radius expansion search, the obtained nodes to be retained are far away from each other, so that the accuracy of the reduced RC circuit can be improved.
Referring to fig. 4, in an embodiment of the present invention, the method for obtaining the equivalent capacitance and/or the equivalent resistance between the port nodes of the second circuit netlist includes:
s41, acquiring a conductance matrix and a capacitance matrix of an internal circuit of the second circuit netlist, and a conductance connection matrix and a capacitance connection matrix of the internal circuit and a port node of the second circuit netlist;
and S42, obtaining the equivalent resistance and/or the equivalent capacitance according to the conductance matrix, the capacitance matrix, the conductance connection matrix and the capacitance connection matrix.
Optionally, an implementation method for obtaining the equivalent resistance and/or the equivalent capacitance in this embodiment may include the following steps: and acquiring constant items of the port admittance matrix of the second circuit netlist and a first moment of the port admittance matrix of the second circuit netlist based on the conductance matrix, the capacitance matrix, the conductance connection matrix and the capacitance connection matrix. Wherein the conductance connection matrix describes a relationship between the port nodes and the internal nodes, the number of rows of the conductance connection matrix may be the number of internal nodes of the second circuit netlist, the number of columns of the conductance connection matrix may be the number of port nodes of the second circuit netlist, and the elements of the conductance connection matrix are determined by the resistive elements between the corresponding port nodes and internal nodes, for example, the conductance connection matrix may be represented by the following equation:
the first row of which represents the internal node numbered 3, the second row represents the internal node numbered 4, the first column of which represents the port node numbered 1, the second column represents the port node numbered 2, wherein g1,3Representing a resistive element between an internal node numbered 3 and a port node numbered 1, a matrix of conductive connections U0Element U in (1)0(2, 2) a matrix of electrically conductive connections U determined by resistive elements between internal nodes numbered 4 and port nodes numbered 20Element U in (1)0(1, 1) is determined by a resistive element between the internal node numbered 3 and the port node numbered 1, and the elements of the capacitive connection matrix are determined by capacitive elements between the corresponding port node and the internal node, connected to the electrical conduction momentsThe same principle is not repeated herein. Judging whether the lower triangular element of the constant term of the port admittance matrix is larger than 0, if so, obtaining the equivalent resistance between the corresponding port nodes; and judging whether the lower triangular element of the first moment of the port admittance matrix is larger than 0, and if so, obtaining the equivalent capacitance between the corresponding port nodes. For example, if the element in the fourth row and the fifth column in the constant term of the port admittance matrix is greater than 0, the equivalent resistance between the port node numbered 4 and the port node numbered 5 is obtained, and the magnitude of the equivalent resistance is determined by the element value of the constant term of the port admittance matrix.
Optionally, the implementation method for obtaining the constant term of the port admittance matrix of the second circuit netlist and the first moment of the port admittance matrix of the second circuit netlist based on the conductance matrix, the capacitance matrix, the conductance connection matrix, and the capacitance connection matrix may be represented by the following formula:
wherein
Is the first moment, U, of the port admittance matrix of the second circuit netlist1Is the capacitance connection matrix, and C is the capacitance matrix. Additionally, the constant terms of the port admittance matrix of the second circuit netlist may be represented by:
wherein
Constant term, U, of the port admittance matrix of the second circuit netlist0And G is the conductance connection matrix.
As can be seen from the above description, the algorithm described in this embodiment can obtain the equivalent capacitance and/or the equivalent resistance between the port nodes of the second circuit netlist by obtaining the correlation matrix of the internal circuit of the second circuit netlist.
Referring to fig. 5, in an embodiment of the invention, the circuit simulation method includes:
s51, obtaining the circuit netlist of the target integrated circuit as a first circuit netlist, wherein the first circuit netlist comprises internal nodes and port nodes. Wherein the set of port nodes of the first circuit netlist is P ═ {1,2, …, M }, and the set of internal nodes of the first circuit netlist is P ═ 2, …, M }
Wherein M is the total number of port nodes of the first circuit netlist, K is the total number of internal nodes of the first circuit netlist, and N isxRepresenting the xth internal node.
S52, processing the first circuit netlist to obtain a node to be reserved therein, wherein the RC time constant of the node to be reserved is larger than the average RC time constant of the internal nodes of the first circuit netlist.
Optionally, the first circuit netlist may be processed through a breadth-first search algorithm, and the processing procedure may be:
s521, obtaining the average value and the search radius of the RC time constant of the internal node, and setting success times, failure times, the upper limit of the success times and the upper limit of the failure times, wherein the success times and the failure times can be set to be 0.
S522, randomly generating a [1, K ] according to the average probability]And obtains the internal node N with the number ii。
S523, judging the internal node NiIf the preset condition is satisfied, if so, executing S525, otherwise, executing S524. Wherein the internal node NiThe preset condition is met by: internal node NiFor nodes to be reserved or searched for, or for the internal node NiIs less than the average RC time constant.
S524, searching the nodes in the first circuit netlist through a breadth-first search algorithm according to the search radius, executing S525 if the searched nodes are nodes to be reserved, searched nodes or non-ground port nodes, otherwise marking the searched nodes as searched nodes, and marking the internal nodes N as searched nodesiAnd marking the nodes as searched nodes and nodes to be reserved, adding 1 to the success times, and entering step S526.
And S525, adding 1 to the failure times, judging whether the failure times reach the upper limit of the failure times, if so, subtracting 1 from the search radius, setting the failure times as 0, and executing the step S522. If not, execution continues with step S522.
S526, judging whether the success frequency reaches the upper limit of the success frequency, if so, stopping the iteration process, and if not, continuing to execute S522.
S53, removing the node to be reserved from the internal node of the first circuit netlist, and adding the node to be reserved into the port node of the first circuit netlist to generate a second circuit netlist.
S54, performing a reduction process on the second circuit netlist to obtain an equivalent circuit, where the reduction process includes: and acquiring equivalent capacitance and/or equivalent resistance between port nodes of the second circuit netlist, eliminating internal nodes of the second circuit netlist and resistance and/or capacitance elements connected with the internal nodes of the second circuit netlist, and adding the equivalent capacitance and/or the equivalent resistance between the port nodes of the second circuit netlist.
Optionally, in this embodiment, the equivalent resistance and/or the equivalent capacitance between corresponding port nodes may be obtained by obtaining a conductance matrix and a capacitance matrix of the internal circuit of the second circuit netlist, a conductance connection matrix and a capacitance connection matrix of the internal circuit and the port of the second circuit netlist, a constant term of the port admittance matrix of the second circuit netlist and a first order moment of the port admittance matrix of the second circuit netlist, and traversing lower triangular elements of the constant term of the port admittance matrix and the first order moment of the port admittance matrix. Wherein the relationship between the constant terms of the port admittance matrix and the conductance matrix, the capacitance matrix, the conductance connection matrix, and the capacitance connection matrix can be represented by the following equation:
wherein
Constant term, U, of the port admittance matrix of the second circuit netlist0And G is the conductance connection matrix. In addition, the first moment of the port admittance matrix can be represented by:
wherein
Is the first moment, U, of the port admittance matrix of the second circuit netlist1Is the capacitance connection matrix, and C is the capacitance matrix.
In addition, the values of the equivalent resistance and the equivalent capacitance are determined by the value of the lower triangular element. For example, if the element in the ith row and jth column of the constant term of the port admittance matrix is
The equivalent resistance between the corresponding port node i and port node j is of the same magnitude
Similarly, if the element in the ith row and the jth column of the first moment of the port admittance matrix is
The corresponding port nodeThe equivalent capacitance between point i and port node j is of the magnitude
Since the values of the equivalent resistance and the equivalent capacitance are non-negative, when the lower triangular element is a negative value, the value is directly discarded.
Optionally, the equivalent capacitance and/or the equivalent resistance are/is added between the port nodes of the second circuit netlist, where the corresponding relationship between the equivalent capacitance and the equivalent resistance and the port nodes is already described in S54, and is not described here again. By eliminating the internal nodes of the second circuit netlist and the resistors and/or elements connected with the internal nodes of the second circuit netlist and adding additional resistors and/or capacitive elements between the port nodes of the second circuit netlist, the number of state variables of the target integrated circuit can be reduced, thereby realizing the reduction of the circuit model and improving the calculation efficiency of the simulation.
And S55, performing circuit simulation on the equivalent circuit through a circuit simulator of the electronic equipment.
As can be seen from the above description, the circuit simulation method according to this embodiment can obtain the second circuit netlist according to the first circuit netlist of the target integrated circuit, and obtain the equivalent circuit of the target integrated circuit according to the second circuit netlist. The process of obtaining the equivalent circuit comprises the steps of carrying out reduction processing on the second circuit netlist, eliminating internal nodes of the second circuit netlist and the like, so that the complexity of the equivalent circuit is lower than that of the target integrated circuit, and therefore, the calculation amount in the simulation process can be reduced and the simulation complexity can be reduced by carrying out circuit simulation based on the equivalent circuit.
Referring to fig. 6, the present invention further provides a circuit simulation apparatus, including: a circuit netlist obtaining unit, configured to obtain a circuit netlist of the target integrated circuit as a first circuit netlist, where the first circuit netlist includes an internal node and a port node;
the first circuit netlist processing unit is used for processing the first circuit netlist to obtain a node to be reserved in the first circuit netlist, and the RC time constant of the node to be reserved is larger than the average RC time constant of internal nodes of the first circuit netlist; the second circuit netlist generation unit is used for removing the node to be reserved from the internal node of the first circuit netlist and adding the node to be reserved into the port node of the first circuit netlist to generate a second circuit netlist; a second circuit netlist processing unit, configured to perform reduction processing on the second circuit netlist to obtain an equivalent circuit, where the reduction processing includes: obtaining equivalent capacitance and/or equivalent resistance between port nodes of the second circuit netlist, eliminating internal nodes of the second circuit netlist and resistance and/or capacitance elements connected with the internal nodes of the second circuit netlist, and adding the equivalent capacitance and/or the equivalent resistance between the port nodes of the second circuit netlist; and the circuit simulation unit is used for carrying out circuit simulation on the equivalent circuit through a circuit simulator of the electronic equipment.
It should be noted that, each module of the circuit simulation apparatus corresponds to a corresponding step in the circuit simulation method shown in fig. 1 one by one, and redundant description is not repeated here for saving the description space.
Based on the above description of the circuit simulation method, the present invention also provides a computer-readable storage medium having stored thereon a computer program. The computer program, when executed by a processor, implements the circuit simulation method shown in fig. 1 or 5.
Based on the description of the circuit simulation method, the invention also provides electronic equipment. Referring to fig. 7, in an embodiment of the invention, the electronic apparatus 700 includes: a memory 710 having a computer program stored thereon; a processor 720, communicatively coupled to the memory 710, is configured to execute the computer program and implement the circuit simulation method shown in fig. 1 or fig. 5.
Optionally, the electronic device further includes a display, and the display is used for displaying a GUI interactive interface related to the circuit simulation method.
The protection scope of the circuit simulation method according to the present invention is not limited to the execution sequence of the steps illustrated in this embodiment, and all the schemes of adding, subtracting, and replacing steps in the prior art according to the principles of the present invention are included in the protection scope of the present invention.
In summary, the circuit simulation method, the circuit simulation apparatus, the medium, and the electronic device according to the present invention are used for simulating a target integrated circuit, and can improve the simulation efficiency of a large-scale integrated circuit and improve the accuracy of a reduced RC circuit. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A circuit simulation method applied to an electronic device for simulating a target integrated circuit, the circuit simulation method comprising:
acquiring a circuit netlist of the target integrated circuit as a first circuit netlist, wherein the first circuit netlist comprises internal nodes and port nodes;
processing the first circuit netlist to obtain a node to be reserved in the first circuit netlist, wherein the RC time constant of the node to be reserved is larger than the average RC time constant of the internal nodes of the first circuit netlist;
removing the node to be reserved from the internal node of the first circuit netlist, and adding the node to be reserved into a port node of the first circuit netlist to generate a second circuit netlist;
performing a reduction process on the second circuit netlist to obtain an equivalent circuit, the reduction process comprising: obtaining equivalent capacitance and/or equivalent resistance between port nodes of the second circuit netlist, eliminating internal nodes of the second circuit netlist and resistance and/or capacitance elements connected with the internal nodes of the second circuit netlist, and adding the equivalent capacitance and/or the equivalent resistance between the port nodes of the second circuit netlist;
and performing circuit simulation on the equivalent circuit through a circuit simulator of the electronic equipment.
2. The circuit simulation method of claim 1, wherein the equivalent circuit is a passive RC circuit.
3. The circuit simulation method of claim 1, wherein the implementation method for processing the first circuit netlist to obtain the nodes to be preserved therein comprises:
obtaining the average RC time constant;
and searching internal nodes in the first circuit netlist according to the average RC time constant to obtain nodes with RC time constants larger than the average RC time constant as the nodes to be reserved.
4. The circuit simulation method according to claim 3, wherein the implementation method for searching the internal nodes in the first circuit netlist according to the average RC time constant to obtain the nodes with RC time constants larger than the average RC time constant as the nodes to be preserved comprises:
step S1, randomly acquiring a node in the first circuit netlist as a random internal node, judging whether the RC time constant of the random internal node is smaller than the average RC time constant, and if the RC time constant of the random internal node is smaller than the average RC time constant, re-acquiring the random internal node;
step S2, searching the first circuit netlist through a breadth-first search algorithm based on the random internal nodes and the search radius, and judging whether the nodes searched by the breadth-first search algorithm meet the conditions, if the searched nodes belong to the points to be reserved, the searched nodes and/or the non-ground port nodes, judging that the searched nodes do not meet the conditions, otherwise, judging that the searched nodes meet the conditions;
step S3, when the searched node meets the condition, the searched node is marked as the searched node, and the random internal node is marked as the node to be reserved and the searched node;
and step S4, if the times that the searched nodes meet the conditions are different from the preset times, the step S1 is switched to, otherwise, the nodes to be reserved are obtained.
5. The circuit simulation method of claim 4, further comprising: the search radius is obtained in response to the received instruction.
6. The circuit simulation method according to claim 1, wherein the method of obtaining the equivalent capacitance and/or the equivalent resistance between the port nodes of the second circuit netlist comprises:
acquiring a conductance matrix and a capacitance matrix of an internal circuit of the second circuit netlist, and a conductance connection matrix and a capacitance connection matrix of the internal circuit and a port node of the second circuit netlist;
and obtaining the equivalent resistance and/or the equivalent capacitance according to the conductance matrix, the capacitance matrix, the conductance connection matrix and the capacitance connection matrix.
7. The circuit simulation method of claim 1, further comprising: and displaying a circuit simulation result by using a display of the electronic equipment.
8. A circuit emulation apparatus, comprising:
a circuit netlist obtaining unit, configured to obtain a circuit netlist of the target integrated circuit as a first circuit netlist, where the first circuit netlist includes an internal node and a port node;
the first circuit netlist processing unit is used for processing the first circuit netlist to obtain nodes to be reserved in the first circuit netlist, and RC time constants of the nodes to be reserved are larger than an average RC time constant of internal nodes of the first circuit netlist;
the second circuit netlist generation unit is used for removing the node to be reserved from the internal node of the first circuit netlist and adding the node to be reserved into the port node of the first circuit netlist to generate a second circuit netlist;
a second circuit netlist processing unit, configured to perform reduction processing on the second circuit netlist to obtain an equivalent circuit, where the reduction processing includes: obtaining equivalent capacitance and/or equivalent resistance between port nodes of the second circuit netlist, eliminating internal nodes of the second circuit netlist and resistance and/or capacitance elements connected with the internal nodes of the second circuit netlist, and adding the equivalent capacitance and/or the equivalent resistance between the port nodes of the second circuit netlist;
and the circuit simulation unit is used for carrying out circuit simulation on the equivalent circuit through a circuit simulator of the electronic equipment.
9. A computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program, when executed by a processor, implements the circuit simulation method of any of claims 1-7.
10. An electronic device, characterized in that the electronic device comprises:
a memory storing a computer program;
a processor, communicatively coupled to the memory, that executes the circuit simulation method of any of claims 1-7 when the computer program is invoked.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114841010A (en) * | 2022-05-19 | 2022-08-02 | 南方电网科学研究院有限责任公司 | Equivalent conductance matrix storage quantization method, device, equipment and readable storage medium |
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| CN114841010A (en) * | 2022-05-19 | 2022-08-02 | 南方电网科学研究院有限责任公司 | Equivalent conductance matrix storage quantization method, device, equipment and readable storage medium |
| CN114841010B (en) * | 2022-05-19 | 2023-03-24 | 南方电网科学研究院有限责任公司 | Equivalent conductance matrix storage quantization method, device, equipment and readable storage medium |
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