CN114492289A - Method and device for positioning and extracting capacitor in circuit layout - Google Patents
Method and device for positioning and extracting capacitor in circuit layout Download PDFInfo
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- CN114492289A CN114492289A CN202210132707.2A CN202210132707A CN114492289A CN 114492289 A CN114492289 A CN 114492289A CN 202210132707 A CN202210132707 A CN 202210132707A CN 114492289 A CN114492289 A CN 114492289A
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Abstract
The invention provides an automatic positioning device for an extraction capacitor in a circuit layout, which comprises a positioning device, a positioning device and a positioning device, wherein the positioning device comprises a positioning device and a positioning device; an acquisition unit for acquiring an integrated circuit layout including K (K is not less than 2) layers of metal wiring; an extraction unit for extracting capacitance values between at least two metal wirings of the plurality of metal wirings in the integrated circuit layout, and storing graphic information in design of the integrated circuit layout in a kd-tree; a setting unit configured to set a framing pattern covering at least two metal wirings in a capacitance extraction area preset in the integrated circuit layout, and calculate coordinate information of the set framing pattern; and a capacitance positioning part which searches the metal wiring associated with the selected pattern, acquires a label corresponding to the searched metal wiring, associates each capacitance value extracted by the extraction part with the label corresponding to the searched metal wiring based on the pattern information in the integrated circuit layout design stored in the kd-tree, and generates an extraction capacitance positioning table.
Description
Technical Field
The invention belongs to the field of automatic design of semiconductor integrated circuits, and mainly relates to rear-end layout design and capacitance extraction.
Background
The development of Flat Panel Display (FPD) process technology, especially the popularity of In Cell touch screen design process, poses a serious challenge to full panel design tools. When layout design is performed in the field of flat panel display, capacitance extraction needs to be performed on a layout so as to determine loads of pixel voltage or touch signals and the like. After the capacitance is extracted, the wirings designed in the layout need to be in one-to-one correspondence with the extracted capacitance value. In the existing method, label is marked on a corresponding metal film layer in a layout, and the label is identified as an electrode name. After the capacitance is extracted, the capacitance value between the electrodes is displayed.
Disclosure of Invention
Problems to be solved by the invention
In the layout design in the field of flat panel display, after the capacitors are extracted, the wiring in the layout needs to be in one-to-one correspondence with the extracted capacitance values. Due to the complex design patterns of pixels, touch electrodes and the like in the layout and the large number of film layers, it is very difficult to position the capacitor by observing various routing lines in the layout by people.
Therefore, an object of the present invention is to provide a method and apparatus for extracting capacitance by fast positioning in a circuit layout.
Means for solving the problems
An automatic positioning device for extracting capacitance in a circuit layout is used for associating capacitance extracted from an integrated circuit layout with corresponding metal wiring in the integrated circuit layout, and is characterized by comprising the following steps of;
an acquisition unit configured to acquire an integrated circuit layout including K (K ≧ 2) metal wirings, each metal wiring layer including M × N metal wirings, M, N being 1, 2, 3 …;
an extraction unit, configured to extract capacitance values between at least two metal wirings in a plurality of metal wirings in the integrated circuit layout, and store graph information in the integrated circuit layout design in a kd-tree, where the graph information at least includes sizes, shapes, coordinates, and labels of the metal wirings in the integrated circuit layout;
a setting unit configured to set a framing pattern covering at least two metal wirings in a capacitance extraction area preset in the integrated circuit layout, and calculate coordinate information of the set framing pattern;
and a capacitance positioning unit which searches for the metal wiring associated with the framed pattern, acquires a label corresponding to the searched metal wiring, associates each capacitance value extracted by the extraction unit with the label corresponding to the searched metal wiring based on pattern information in the design of the integrated circuit layout stored in the kd-tree, and generates an extracted capacitance positioning table.
In one implementation, the graphic information further includes information on whether or not the floating metal wiring of the tag is not set.
In one implementation, the obtaining unit further obtains a circuit netlist, a circuit simulation result, and design rule data related to the integrated circuit layout.
In one implementation, the extraction section extracts a capacitance value between at least two metal wirings in the same layer and/or different layer metal layers.
In one implementation, the framing pattern covers an area of interest that includes all of the metal wiring.
In one implementation, the capacitance positioning portion uses a random walk algorithm or model to make the framing pattern traverse all metal wires in the capacitance extraction area to obtain a label of each metal wire associated with the framing pattern.
In one implementation manner, the device for extracting and positioning the capacitance further comprises an output part, and the output part outputs or prints the capacitance positioning result through an excel table or a text.
In one implementation, the circuit layout includes floating metal wirings with no tags set, and the setting unit automatically names the floating metal wirings with no tags set as "RCE _ UNCONN", so that the capacitance positioning unit performs capacitance positioning on a region of interest including the floating metal wirings in the circuit layout.
The invention also provides a method for automatically positioning the extracted capacitance in the circuit layout, which is used for associating the capacitance extracted from the integrated circuit layout with the corresponding metal wiring in the integrated circuit layout, and the method is characterized by comprising the following steps of;
an obtaining step, configured to obtain the integrated circuit layout, where the integrated circuit layout includes K (K is greater than or equal to 2) layers of metal wirings, each metal wiring layer includes M × N metal wirings, and M, N is 1, 2, 3 …;
an extraction step, which is used for extracting capacitance values between at least two metal wirings in a plurality of metal wirings in the integrated circuit layout and storing graphic information in the design of the integrated circuit layout into a kd-tree, wherein the graphic information at least comprises the size, the shape, the coordinates and the labels of the metal wirings in the circuit layout;
a setting step of setting a framing pattern covering at least two metal wirings in a capacitance extraction area preset in the integrated circuit layout, and calculating coordinate information of the set framing pattern; and
and a capacitance positioning step of searching the metal wiring associated with the selected pattern, acquiring a label corresponding to the searched metal wiring, and associating each extracted capacitance value with the label corresponding to the searched metal wiring based on the pattern information in the integrated circuit layout design stored in the kd-tree to generate a capacitance positioning table.
The invention also includes a computer readable storage medium storing instructions executable to cause one or more processors to perform operations including the above-described method of automatically locating extraction capacitors in a circuit layout.
ADVANTAGEOUS EFFECTS OF INVENTION
According to the invention, the metal wiring and the extraction capacitor in the integrated circuit layout can be quickly positioned, a circuit layout designer can conveniently analyze the load in the layout design, and the efficiency of the circuit layout design is improved.
Drawings
Fig. 1 is a diagram showing an example of a hardware configuration of a computer terminal according to the present invention.
Fig. 2 is a diagram showing an example of a functional configuration of a computer terminal according to the present invention.
FIG. 3 is a flow chart of the circuit layout capacitance automatic positioning of the present invention.
Fig. 4 is a schematic diagram of the present invention connecting different layers of metal wiring by vias.
Fig. 5 is a schematic diagram of the same and different layer metal wiring connections of the present invention.
Fig. 6 is a schematic cross-sectional view of the present invention connecting different layers of metal wiring by vias.
FIG. 7 is an example of a circuit layout design interface according to the present invention.
Fig. 8 is an example of a capacitance extraction result interface according to the present invention.
FIG. 9 is an example of a frame-selected graphical setting interface according to the present invention.
Fig. 10 shows an example of a capacitance extraction result interface according to the present invention.
Fig. 11 is an example of the positioning of capacitance values associated with Floating metal wiring according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present disclosure.
The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.
In layout design, the area capacitance extraction is carried out on a pixel or a touch unit. The extracted electrodes include labeling; and no labeling; the floating metal layer. The capacitance values extracted may be tens of groups, or even hundreds or thousands of groups. After the capacitance value is extracted, the wiring in the layout needs to be in one-to-one correspondence with the extracted capacitance value. Hereinafter, embodiments of quickly positioning a capacitor in a layout will be described with reference to the drawings.
The method for quickly locating a capacitor in a layout according to the present invention is implemented, for example, by a computer terminal to which dedicated application software (a plurality of application programs such as a layout design program and a layout capacitor extraction degree according to the present invention) is installed. The computer terminal can implement each function described later, including hardware resources necessary for implementing each function, by executing processing related to a plurality of application programs.
The hardware configuration of the computer terminal 10 according to the present embodiment will be described with reference to fig. 1. Fig. 1 is a diagram showing an example of a hardware configuration of a computer terminal 10 according to the present embodiment.
As shown in fig. 1, the computer terminal 10 according to the present embodiment is realized by a general computer or a computer system, and includes an input device 11, a display device 12, an external I/F13, a communication I/F14, a processor 15, and a memory device 16. These hardware components are connected to each other so as to be able to communicate via the bus 17.
The input device 11 is, for example, a keyboard, a mouse, a touch panel, or the like. The display device 12 is, for example, a display or the like.
The external I/F13 is an interface with an external device such as the recording medium 13 a. The monitoring device 10 can read from and write to the recording medium 13a via the external I/F13. Examples of the recording medium 13a include a CD (Compact Disc), a DVD (Digital Versatile Disc), an SD memory card (Secure Digital memory card), and a USB (Universal Serial Bus) memory card.
The communication I/F14 is an interface for connecting the monitoring apparatus 10 to a communication network. The processor 15 is, for example, various arithmetic devices such as a CPU (Central Processing Unit). The Memory device 16 is a variety of storage devices such as an HDD (hard disk Drive), an SSD (Solid State Drive), a RAM (Random Access Memory), a ROM (Read Only Memory), and a flash Memory.
The computer terminal 10 according to the present embodiment has a hardware configuration shown in fig. 1, and can realize various processes described later. Note that the hardware configuration shown in fig. 1 is an example, and the computer terminal 10 may have another hardware configuration. For example, the computer terminal 10 may have a plurality of processors 15 and may also have a plurality of memory devices 16.
Next, a functional configuration of the computer terminal 10 according to the present embodiment will be described with reference to fig. 2. Fig. 2 is a diagram showing an example of a functional configuration of the computer terminal 10 according to the present embodiment.
As shown in fig. 2, the computer terminal 10 according to the present embodiment includes an acquisition unit 101, an extraction unit 102, a setting unit 103, a positioning unit 104, and an output unit 105. These units are realized by, for example, causing the processor 15 to execute one or more programs installed in the computer terminal 10.
The computer terminal 10 according to the present embodiment includes a history storage unit 106 and a positioning storage unit 107. These components are realized by the memory device 16, for example. Further, at least one of these respective parts may be realized by a storage device (e.g., a database server or the like) connected to the computer terminal 10 via a communication network.
The acquisition unit 101 acquires a circuit layout of an integrated circuit. The circuit layout of the integrated circuit can be generated by the computer terminal 10 through relevant integrated circuit design software based on the IC design rule, and can also be obtained through communication with a remote server or a cloud server through an external I/F13 through a wired or wireless network.
The circuit layout of an integrated circuit may be composed of one layout area or divided plural layout areas. In practical applications, for example, the first layout area is an RF circuit layout area, the RF circuit layout area is composed of an inductor and a plurality of capacitors and transistors, and the capacitors and the transistors are symmetrically distributed with the inductor as a central axis; the second layout area is a Sigma-delta modulator layout area which automatically generates layout wiring through a digital flow, a deep N-well isolation band is arranged around the Sigma-delta modulator layout area, and the position of the deep N-well isolation band is a certain distance away from other layout areas, so that digital noise of the Sigma-delta modulator layout area can be prevented from interfering other analog/radio frequency modules through capacitive coupling or a substrate, and the third layout area is an input/output interface layout area and specifically comprises a plurality of parallel input/output interface layouts; the plurality of parallel input and output interface layouts are evenly distributed around the IC chip layout.
In one implementation, the acquisition unit 101 receives as input data such as a circuit netlist, a circuit simulation result, a physical layout of a circuit, and a design rule, and stores the data in the history storage unit 106.
The extraction unit 102 derives a circuit layout of one or more integrated circuits from the history storage unit 106, extracts capacitances between a plurality of metal wirings on the integrated circuit layout based on the derived integrated circuit layout, and stores graphic information in the integrated circuit layout design in the kd-tree. The kd-tree is a binary tree with each node being a k-dimensional point, is a tree data structure for storing instance points in a k-dimensional space so as to quickly retrieve the instance points, and is mainly applied to searching of key data in a multi-dimensional space.
The graphic information in the integrated circuit layout design includes, but is not limited to, for example, graphic information of metal wirings (size, shape, coordinates, etc. of the metal wirings), labels of the metal wirings, whether unnamed metal wirings are included (floating metal wirings), and the like.
The extraction method of the capacitor described in the present invention can be implemented in various ways: (1) a library search method: the method is an improvement of the traditional pattern matching, and applies a model library with larger scale and good adaptability, and a pre-obtained combination pattern library or an analytic formula is stored in the model libraries; (2) the random method comprises the following steps: stacking of statistical model samples, such as the method of calculating the capacitance problem using random walk method "(3) 3-dimensional field: is a method of discretizing the geometric model under study and applying a weighted residue method to solve the laplace equation used to describe the quasi-static problem.
The search method based on the library is a capacitance extraction algorithm of a very large scale integrated circuit which is widely applied, the algorithm has the advantages of high speed and high precision, is more consistent with the actual process environment, and is more suitable for extracting the circuit parameters of the large scale circuit in industry.
The overall idea of the library searching method is as follows: firstly, preparing, selecting a plurality of representative statistical models, respectively bringing the plurality of models into different parameters (best value, worst value and the like), carrying out numerical simulation to obtain capacitance data of the plurality of models under different conditions, applying the capacitance data to carry out optimization to form interpolation models, and performing 2D/3D lookup libraries on the models for capacitance extraction. When parameters are actually extracted, firstly, the wiring is divided and extracted to form small units, and corresponding capacitance is obtained by applying a library lookup method for interpolation of each unit. Finally, these capacitances are mapped in nodes to an equivalent circuit, resulting in a file output that SPICE can recognize.
For the multilayer wiring, if three-dimensional spatial structure numerical calculation is adopted, the calculation amount is quite large because the function between different layers is quite complicated. Consider the idea of electric field shielding and superposition, which is decomposed into several equivalent models. Then, an empirical algorithm is applied to each simple model which is known, and satisfactory results can be obtained. The specific process is as follows: first, using the shielding principle, it is considered that for wirings larger than 5-layer pitch, the roles of each other are negligible due to the shielding effect of the electric field. Therefore, the first layer and the last layer of the multilayer model can be equivalent to a shielding flat plate, the problem of calculation becomes three layers, the workload is reduced, and the three-layer model can be equivalent to a plurality of two-dimensional models again to be calculated by means of a two-dimensional algorithm.
In the invention, for example, the capacitance between the metal wirings on the circuit layout can be extracted by using a library search method or a three-dimensional field method to obtain a circuit layout capacitance extraction report.
The setting unit 03 sets a framing pattern in the extraction capacitance region of the circuit layout design interface, and calculates coordinate information of the set framing pattern.
The user can select a "box" icon in a menu area of the circuit layout design interface through an input device 11 such as a keyboard, a mouse, a touch panel, or the like, and then set a box graphic, for example, presented as a dotted line box, in a predetermined area in the capacitance extraction area. The framing pattern can be circular, oval, square, rectangular, etc. The size of the frame-selected graphic can be dynamically increased or decreased according to the control of the input device 11, or the size of the frame-selected graphic can be preset as a fixed value. The user can drag the set frame selection graphic to an arbitrary position in the capacitance extraction area through the input device 11.
When the framing pattern is set at a predetermined position in the capacitance extraction area where the metal wiring is included, the setting section 03 automatically calculates coordinate information (x) of the framing pattern in the capacitance extraction areai，yi)。
When the framing pattern is set at a predetermined position including the metal wiring in the capacitance extraction area, the positioning portion 104 searches the Kd-tree for a plurality of metal wirings corresponding to the framing pattern that is set, and further acquires the tags a, b, c … corresponding to the respective metal wirings.
The positioning unit 104 associates the capacitances extracted by the extraction unit 102 with the tags a, b, and c … of the corresponding metal wirings obtained based on the Kd-tree, and automatically generates a capacitance positioning table. One or more capacitance localization tables generated by the localization section 104 are stored in the localization storage section 107.
The output unit 105 includes, for example, a visualization unit, and displays a screen in which various kinds of information such as the extracted capacitance and the tags a, b, and c … of the corresponding metal wirings obtained based on the Kd-tree are visualized. The output unit 105 may output information such as a capacitance positioning table by text or the like. The output unit 105 may display various screens on the visualization means, and may display various screens such as a circuit layout, a capacitance extraction, and a capacitance localization, for example, on a display device (for example, a large-screen device) connected to the computer terminal 10 via a communication network.
The history storage unit 106 stores various data such as circuit layout design, capacitance extraction, framing pattern setting, and capacitance extraction. The positioning storage unit 107 stores a capacitance positioning table 1000.
Table 1 is a diagram of an example of the capacitance positioning table 1000.
As shown in table 1, the extracted capacitance value corresponds to the metal wiring associated with the capacitance value. As for extracted capacitance value 0.894, its associated metal routing label is a, b, for extracted capacitance value 161.058, its associated metal routing label is a, c, and for extracted capacitance value 161.292, its associated metal routing label is b, c.
TABLE 1
| ID | Metal wiring label (from) | Metal wiring label (to) | Capacitance value |
| 0 | a | c | 0.894 |
| 1 | a | b | 161.058 |
| 2 | b | c | 161.292 |
Therefore, the automatic positioning device for the circuit layout capacitor can realize the quick positioning of metal wiring and extraction capacitor results in the circuit layout, is convenient for a circuit layout designer to analyze the load in the layout design, and improves the efficiency of the circuit layout design.
Next, a specific process of the automatic positioning device for circuit layout capacitance according to the present invention will be described with reference to fig. 3. Fig. 3 is a flowchart showing an example of automatic positioning of circuit layout capacitance according to the present embodiment.
Specifically, the specific process of the method for automatically positioning the layout capacitance of the invention comprises the following steps:
step S01: an acquisition unit 101 acquires a circuit layout of an integrated circuit;
step S01 specifically includes: according to the design rule and the requirement of the integrated circuit, such as the market requirement of the 5G/IoT special integrated circuit, the design method of the circuit layout is determined, and the circuit layout is generated on a circuit layout design interface by utilizing integrated circuit design software.
In one implementation, the circuit layout comprises K (K ≧ 2) layers of metal wirings, and each metal wiring layer comprises M × N (M, N ≧ 1, 2, 3 …) metal wirings. The circuit layout typically includes one or more electrodes, which may be formed by multiple layers of metal wiring connected by vias, as shown in fig. 4. The multiple electrodes need to be connected to another layer of metal wiring through the via holes to realize signal transmission. As shown in fig. 5, the electrode may also be formed by a plurality of metal wirings on the same layer, two or more metal wirings above and below may be directly connected, and two or more metal wirings on the left and right need to jump to other metal layers through vias to achieve connection between the metal wirings.
Fig. 6 is a schematic cross-sectional view of the connection of the metal layer 1 and the metal layer 2 through a via. During the fabrication process, the insulating layer is etched away at the location of the via. And the metal layer 1 on the upper layer is filled into the via hole, so that the connection between the metal layer 1 and the metal layer 2 is realized.
Optionally, the obtaining unit 101 stores the obtained data of the integrated circuit layout and/or circuit netlist, the circuit simulation result, the design rule, and the like in the history storage unit 106.
In another embodiment, the computer terminal 10 obtains a file including the integrated circuit layout from an external device (e.g., storage medium, server …).
Step S02: the extracting part 102 extracts the capacitance among a plurality of metal wirings on the integrated circuit layout according to the acquired integrated circuit layout, and stores the graphic information in the integrated circuit layout design into a kd-tree;
for simplicity, in an embodiment of the present invention, a 2-layer circuit layout including 3 metal wirings is taken as an example, and a method for quickly positioning a capacitor is described with reference to the accompanying drawings. It will be appreciated that although the process described below with respect to the flowchart is exemplified with a 2-layer circuit layout containing 3 metal wires, the application of the process can be extended to the rapid positioning of capacitance for a multi-layer (3 layers or more) circuit layout containing N (N ≧ 3) metal wires.
As shown in fig. 7, a dashed line box in the circuit layout design interface shows a to-be-extracted capacitance region, which includes 3 metal wirings a, b, and c. The metal wirings a and b are in the same layer, the metal wiring c is a metal wiring in a different layer from the metal wirings a and b, and for the convenience of identification and positioning, the labels a, b and c are respectively marked on the metal wirings in fig. 10. The metal wiring layers may or may not have an insulating layer therebetween (connected by jumpers).
In practical application, the capacitance extraction theory used by the invention is based on Maxwell equation set, the Laplace equation in a certain area is simplified under the condition of an electrostatic field, and the normal electric field intensity of the conductor surface under a certain bias voltage is solved. The laplace equation is solved, using the boundary element method. In one implementation of the present invention, the specific process of capacitance extraction is as follows:
1. the derived circuit layout process data is processed to perform necessary geometric operations on the features (i.e., all metal wiring, insulating layer, etc.) in the circuit layout to form insulating layer and metal wiring surface. 2. And dividing boundary elements on the surface of the body.
3. And integrating the boundary elements to generate a matrix and a vector of a linear algebraic equation system.
4. And solving the Laplace equation set to obtain the normal electric field intensity of the metal wiring surface.
5. The parasitic capacitance between the metal wirings is calculated from the normal electric field intensity of the metal wiring surface.
The present invention is not limited to the above capacitance extraction method, and other capacitance extraction techniques may be adopted.
The capacitance extraction result interface is shown in fig. 8. When the capacitance extraction result interface is started, the background program of the computer terminal 10 stores the graphic information (the graphic information of the metal wiring (the size, the shape, the coordinates, and the like of the metal wiring), the label of the metal wiring, whether the unnamed metal wiring is included (floating metal wiring), and the like) in the integrated circuit layout design into the kd-tree.
Step S03: the setting unit 103 sets a framing pattern in the capacitance extraction area of the circuit layout design interface, and calculates coordinate information of the set framing pattern;
specifically, in the capacitance extraction result interface shown in fig. 8, it is assumed that a cursor, a touch, and the like are used to click a "frame selection" icon on a menu, and a frame selection icon clicking operation performed on the capacitance extraction result interface triggers a Socket signal to be sent to a circuit layout design interface window program, so as to activate a "frame selection" button function on the menu of the circuit layout design interface window.
And as the 'box selection' icon is selected, the 'box selection' icon is highlighted or dynamically flickered to prompt further operation. The setting unit 103 sets a framing pattern in a region of interest including metal wirings in a capacitance extraction region of the circuit layout design interface. The size of the frame selection pattern can cover part of metal wiring in the circuit layout or can cover all the metal wiring in the circuit layout.
Fig. 9 shows a box pattern provided in an extraction capacitance region of a circuit layout design interface by a "box" icon click operation, the box pattern being arranged on a region of interest including two metal wirings. The setting unit 103 calculates or acquires coordinate information of the frame selection pattern. The coordinates of the boxed graphic on the computer screen may be calculated or obtained based on computer graphics in a variety of existing ways, which are not limiting of the invention.
Step S04: the positioning section 104 searches the kd-tree for a plurality of metal wirings associated with the outlined pattern, and acquires tags corresponding to the searched plurality of metal wirings.
When the framing icon is released, the circuit layout design interface window program sends a socket signal to the capacitance extraction result interface program, the signal contains framing graphic coordinate information, a framing function in the circuit layout design interface is closed, and then signal communication between the programs is disconnected.
At this time, the frame selection pattern covers a part or the whole of the region of interest including the metal wiring,
and searching a plurality of metal wirings related to the framed graph in the kd-tree through the coordinate information of the framed graph, the graph information already stored by the kd-tree and the searched interface by a background capacitance positioning program of the capacitance extraction result interface, and further acquiring the labels a, b and c … corresponding to the metal wirings. Wherein the pattern information stored in the kd-tree includes predetermined labels corresponding to the respective metal wirings, such as a, b, c …,
in one implementation, if the set size of the framing pattern is small, e.g., only covers a portion of the metal wires, the background capacitance positioning program makes the framing pattern traverse all the metal wires in the capacitance extraction area, e.g., using a random walk (random walk) algorithm or model, to obtain the labels corresponding to the metal wires. In another implementation, the size of the framing pattern is set to cover all the metal wirings, and the background capacitance positioning program extracts the labels corresponding to the metal wirings associated with the framing pattern at one time.
After extracting the labels corresponding to the metal wirings associated with the selected pattern in the above manner, the positioning unit 104 associates the capacitances extracted by the extraction unit 102 with the labels a, b, and c … of the metal wirings acquired in the above manner based on the pattern information in the integrated circuit layout design stored in the Kd-tree, and automatically generates a capacitance positioning table as shown in fig. 10. One or more capacitance localization tables generated by the localization section 104 are stored in the localization storage section 107.
Step S05: the output unit 105 outputs the capacitance extraction value in the circuit layout and the positioning result of each metal wiring.
If the tag labels of the framed plurality of metal wirings include a, b, and c, the capacitance extraction result highlights the capacitances of a and b, b and c, and a and c, as shown in fig. 10. The capacitance extraction result can be displayed through a visual computer terminal interface, and the generated capacitance positioning table can be output through an excel table, a text or printed.
In another embodiment of the present invention, fig. 11 is a circuit layout design in which only two metal lines have set tag A, B, and the remaining metal lines are floating metal layers with more non-set tags.
In the invention, after the capacitance is extracted from the circuit layout shown in fig. 11 by using the capacitance extraction method, the floating metal wiring without the label is automatically named as 'RCE _ UNCONN'. The capacitance between the floating metal wirings is usually difficult to locate, but in the present invention, after the framing pattern is set in the circuit layout shown in fig. 11 by the method shown above, the floating metal wirings can be easily identified and the capacitance between the metal wirings including the floating metal wirings in the circuit layout can be located. For example, if it is desired to obtain the capacitance between the metal wiring B and the right floating metal wiring not provided with a tag, but there are many floating metal wirings not provided with a tag, and if all the floating metal wirings not provided with a tag are automatically named "RCE _ nonconn", there are many metal wirings labeled "RCE _ nonconn", it is difficult to determine which floating metal wiring on the right corresponds to the extracted capacitance value. At this time, the invention sets the frame selection graph in the circuit layout to the attention area containing the metal wiring B and the predetermined floating metal wiring on the right, so that the capacitance value between the two metal wirings can be conveniently, quickly and clearly known.
As described above, the embodiment of the invention can quickly identify and position the capacitance extraction result in the circuit layout design, and improve the efficiency of the integrated circuit layout design.
The invention further provides a readable storage medium, wherein a program or an instruction is stored on the readable storage medium, and when the program or the instruction is executed by a processor, each process of the circuit layout capacitance positioning method is realized, and the same technical effect can be achieved, and in order to avoid repetition, the description is omitted here.
The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like.
While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (17)
1. An automatic positioning device for extracting capacitance in a circuit layout is used for associating capacitance extracted from an integrated circuit layout with corresponding metal wiring in the integrated circuit layout, and is characterized by comprising the following steps of;
an acquisition unit configured to acquire the integrated circuit layout, where the integrated circuit layout includes K (K ≧ 2) metal wirings, each metal wiring layer includes M × N metal wirings, and M, N ═ 1, 2, 3 …;
an extraction unit, configured to extract capacitance values between at least two metal wirings in a plurality of metal wirings in the integrated circuit layout, and store graphic information in design of the integrated circuit layout into a kd-tree, where the graphic information at least includes a size, a shape, coordinates, and a label of the metal wirings in the integrated circuit layout;
a setting unit configured to set a framing pattern covering at least two metal wirings in a capacitance extraction area preset in the integrated circuit layout, and calculate coordinate information of the set framing pattern;
and a capacitance positioning part which searches the metal wiring associated with the selected pattern, acquires a label corresponding to the searched metal wiring, associates each capacitance value extracted by the extraction part with the label corresponding to the searched metal wiring based on the pattern information in the integrated circuit layout design stored in the kd-tree, and generates an extraction capacitance positioning table.
2. The extraction capacitance positioning device of claim 1,
the graphic information also includes information on whether or not the floating metal wiring of the tag is not set.
3. The extraction capacitance positioning device of claim 1,
the acquisition unit also acquires a circuit netlist, a circuit simulation result, and design rule data related to the integrated circuit layout.
4. The extraction capacitance positioning device of claim 1,
the extraction section extracts a capacitance value between at least two metal wirings in the same layer and/or different layer metal layers.
5. The extraction capacitance positioning device of claim 1,
the framing pattern covers a region of interest that includes all of the metal wiring.
6. The extraction capacitance positioning device of claim 1,
and the capacitance positioning part enables the framing graph to traverse all metal wirings in the capacitance extraction area by adopting a random walk algorithm or a model so as to obtain the labels of all the metal wirings related to the framing graph.
7. The extraction capacitance positioning device of claim 1,
the extraction capacitor positioning device further comprises an output part, and the output part outputs or prints the positioning result of the extraction capacitor through an excel table and a text.
8. The extraction capacitance positioning device of claim 2,
the integrated circuit layout comprises the floating metal wiring without the set label, and the setting part automatically names the floating metal wiring without the set label as 'RCE _ UNCONN', so that the capacitance positioning part performs capacitance positioning on a region of interest containing the floating metal wiring in the integrated circuit layout.
9. A method for automatically locating an extracted capacitor in a circuit layout, which is used for associating a capacitance value extracted from an integrated circuit layout with a corresponding metal wiring in the integrated circuit layout, is characterized by comprising the following steps of;
an obtaining step, configured to obtain the integrated circuit layout, where the integrated circuit layout includes K (K is greater than or equal to 2) layers of metal wirings, each metal wiring layer includes M × N metal wirings, and M, N is 1, 2, 3 …;
an extraction step, which is used for extracting capacitance values between at least two metal wirings in a plurality of metal wirings in the integrated circuit layout and storing graphic information in the design of the integrated circuit layout into a kd-tree, wherein the graphic information at least comprises the size, the shape, the coordinates and the labels of the metal wirings in the integrated circuit layout;
a setting step of setting a framing pattern covering at least two metal wirings in a capacitance extraction area preset in the integrated circuit layout, and calculating coordinate information of the set framing pattern; and
and a capacitance positioning step of searching the metal wiring associated with the selected pattern, acquiring a label corresponding to the searched metal wiring, and associating each extracted capacitance value with the label corresponding to the searched metal wiring based on the pattern information in the integrated circuit layout design stored in the kd-tree to generate a capacitance positioning table.
10. The method of claim 9,
the graphic information also includes information on whether or not the floating metal wiring of the tag is not set.
11. The method of claim 9,
the obtaining step also obtains a circuit netlist, a circuit simulation result and design rule data related to the integrated circuit layout.
12. The method of claim 9,
the extracting step extracts a capacitance value between at least two metal wirings in the same layer and/or different layers of metal layers.
13. The method of claim 9,
the framing pattern covers a region of interest that includes all of the metal wiring.
14. The method of claim 9,
the capacitance positioning step employs a random walk algorithm or model to traverse the boxed graph through all metal wires in the capacitance extraction area to obtain labels of the metal wires associated with the boxed graph.
15. The method of claim 9,
and the method also comprises an output step, wherein the capacitance positioning result is output or printed through an excel table and a text.
16. The method of claim 9,
the integrated circuit layout comprises floating metal wiring of which the label is not set, and the setting step automatically names the floating metal wiring of which the label is not set as 'RCE _ UNCONN', so that the concerned area containing the floating metal wiring in the integrated circuit layout is automatically positioned in a capacitance mode.
17. A computer-readable storage medium storing instructions executable to cause one or more processors to perform operations comprising the method of automatically locating extracted capacitances in a circuit layout of any of claims 9-16.
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| CN202210132707.2A CN114492289A (en) | 2022-02-14 | 2022-02-14 | Method and device for positioning and extracting capacitor in circuit layout |
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| CN202210132707.2A CN114492289A (en) | 2022-02-14 | 2022-02-14 | Method and device for positioning and extracting capacitor in circuit layout |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114662445A (en) * | 2022-05-25 | 2022-06-24 | 杭州行芯科技有限公司 | Random walking method and device for parasitic capacitance extraction and electronic device |
| CN115934980A (en) * | 2022-12-02 | 2023-04-07 | 珠海芯聚科技有限公司 | Layout graph search processing method, device, equipment and storage medium |
| CN116881515A (en) * | 2023-09-07 | 2023-10-13 | 杭州行芯科技有限公司 | Method and electronic equipment for comparing capacitance results solved by different algorithms |
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- 2022-02-14 CN CN202210132707.2A patent/CN114492289A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114662445A (en) * | 2022-05-25 | 2022-06-24 | 杭州行芯科技有限公司 | Random walking method and device for parasitic capacitance extraction and electronic device |
| CN115934980A (en) * | 2022-12-02 | 2023-04-07 | 珠海芯聚科技有限公司 | Layout graph search processing method, device, equipment and storage medium |
| CN115934980B (en) * | 2022-12-02 | 2023-09-08 | 珠海芯聚科技有限公司 | Layout graph search processing method and device, equipment and storage medium |
| CN116881515A (en) * | 2023-09-07 | 2023-10-13 | 杭州行芯科技有限公司 | Method and electronic equipment for comparing capacitance results solved by different algorithms |
| CN116881515B (en) * | 2023-09-07 | 2023-12-19 | 杭州行芯科技有限公司 | Method and electronic equipment for comparing capacitance results solved by different algorithms |
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