CN114417754B

CN114417754B - Formalized identification method of combinational logic unit and related equipment

Info

Publication number: CN114417754B
Application number: CN202210328018.9A
Authority: CN
Inventors: 席海涛
Original assignee: Xinxingji Technology Co ltd
Current assignee: Xinxingji Technology Co ltd
Priority date: 2022-03-31
Filing date: 2022-03-31
Publication date: 2022-07-01
Anticipated expiration: 2042-03-31
Also published as: CN114417754A

Abstract

The application provides a formal identification method of a combined logic unit and related equipment. The method comprises the following steps: receiving input data; analyzing the number of output pins in the input data; analyzing the number of input pins in the input data in response to determining that the number of output pins is 1; performing symmetry clustering based on input pins in response to determining that the number of input pins is not 1; and calling a corresponding recognition algorithm according to the symmetrical clustering result, and performing formal recognition of the combinational logic unit on the input data to obtain a recognition result.

Description

Formalized identification method of combinational logic unit and related equipment

Technical Field

The present application relates to the field of chip technologies, and in particular, to a formal identification method for a combinational logic unit and a related device.

Background

In the design flow of digital integrated circuits currently in the mainstream, designers typically implement complex designs based on Standard Cell Library (Standard Cell Library) provided by foundries (foundries). In practice, the standard Cell library will be used as input to Electronic Design Automation (EDA) software by a user, and circuit Synthesis (Synthesis), Technology Mapping (Technology Mapping) and Optimization (Optimization) are performed by the EDA software based on the Logic cells (Logic cells) provided by the standard Cell library. The functional identification of the logic cells provided in the standard cell library is therefore one of the indispensable functions of mainstream EDA software.

However, the inventors of the present application have found that the current EDA software function identification method for a Combinational logic Cell (combinatorial Cell) has a contradiction that both accuracy and operating efficiency cannot be achieved.

Disclosure of Invention

In view of the above, an object of the present application is to provide a formal identification method of a combinational logic unit and a related device.

In a first aspect of the present application, a formal identification method for a combinational logic unit is provided, including:

receiving input data;

analyzing the number of output pins in the input data;

analyzing the number of input pins in the input data in response to determining that the number of output pins is 1;

performing symmetry clustering based on input pins in response to determining that the number of input pins is not 1; and

and calling a corresponding recognition algorithm according to the symmetrical clustering result, and performing formal recognition of the combinational logic unit on the input data to obtain a recognition result.

In a second aspect of the application, a computer device is provided, comprising one or more processors, memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, the programs comprising instructions for performing the method according to the first aspect.

In a third aspect of the application, a non-transitory computer-readable storage medium containing a computer program is provided, which, when executed by one or more processors, causes the processors to perform the method of the first aspect.

In a fourth aspect of the present application, there is provided a computer program product comprising computer program instructions which, when run on a computer, cause the computer to perform the method of the first aspect.

According to the formal identification method and the relevant equipment of the combinational logic unit, the number of the output pins and the number of the input pins are preliminarily analyzed, the clustering is carried out based on the input pins by utilizing the symmetric clustering, and then the corresponding identification algorithm is called for each clustering result to carry out the formal identification of the combinational logic unit, so that the corresponding identification result is obtained, on one hand, the correctness is ensured, and on the other hand, the high efficiency of the operation efficiency is also ensured.

Drawings

In order to more clearly illustrate the technical solutions in the present application or the related art, the drawings needed to be used in the description of the embodiments or the related art will be briefly introduced below, and it is obvious that the drawings in the following description are only embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 shows a schematic diagram of a computer device according to an embodiment of the application.

Fig. 2 shows a basic structural diagram of an EDA tool according to an embodiment of the application.

Fig. 3 shows a flow diagram of an exemplary method provided by an embodiment of the present application.

Fig. 4A illustrates a flow diagram of an exemplary method according to an embodiment of the present application.

Fig. 4B illustrates a flow diagram of an exemplary method according to an embodiment of the present application.

Fig. 4C shows a flow diagram of an exemplary method according to an embodiment of the present application.

Fig. 5A illustrates a flow diagram of an exemplary method according to an embodiment of the present application.

FIG. 5B illustrates a flowchart of an exemplary method according to an embodiment of the application.

Fig. 5C shows a flow diagram of an exemplary method according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below with reference to the accompanying drawings in combination with specific embodiments.

It should be noted that technical terms or scientific terms used in the embodiments of the present application should have a general meaning as understood by those having ordinary skill in the art to which the present application belongs, unless otherwise defined. The use of "first," "second," and similar terms in the embodiments of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

Generally, a Standard Cell Library (Standard Cell Library) describes two main types of basic Logic cells (Logic cells), namely a Combinational Logic Cell (combinatorial Cell) and a Sequential Cell (Sequential Cell). The function identification may be to classify the combinational logic unit according to the function type. In general, combinational logic functions may include the following types: a normally High gate (Tie High Cell), a normally Low gate (Tie Low Cell), an AND gate (AND), an OR gate (OR), an inverter gate (INV), a NAND gate (NAND), an XOR gate (XOR), an XNOR gate (XNOR), a main vector gate (Majority), a multi-way select gate (MUX), a composite gate, AND a complex gate. Wherein the composite door may further include: and or not (AOI), and or not (AIO), or not and (OAI), or not and (OIA), not and (IAO), not or and (IOA); the complex door may further comprise: multiple output gates, other logic units not of any of the types described above.

After the logic classification is completed, the function of the input pins may be further confirmed. For example, if a Logic Cell is classified as a MUX, the classification algorithm also needs to return whether each input pin belongs to a data pin or a control pin. In the case of a data pin, it is also desirable to return what combinations of input signals can be strobed.

Typically, Standard Cell Library defines the behavior of each type of logic gate by a logic expression. Formally, a Boolean logic variable x e {0, 1}, f: {0, 1} is definedⁿ→ {0, 1} is a Boolean function from n-dimensional Boolean variables to 1-dimensional. Defining basic logical operators: AND, OR, INV, XOR, it can be shown that any logical expression can be implemented by the above described basic logical operators of no more than two inputs.

There are two broad categories of methods for functional identification of a combinatorial Cell.

One is an unformed process. For example, the function of the combinatorial Cell is determined by capturing its name feature or by using a footer (footer) reserved in the standard Cell library. Therefore, software based on this method typically has very high running speeds, but sacrifices mathematical guarantees on the correctness of the results.

The other is a formal-based authentication method. Generally, a formal verification method is a verification method based on formalized steps of logical reasoning, equivalence verification, and the like. The correctness of the formalization method can be guaranteed by mathematical proofs and is therefore a very reliable method. However, software based on formal methods is generally disadvantageous in terms of running speed. One of the reasons for this is that the core problem of formal verification is that it belongs to NP Complete problem (NP-Complete). Currently, no algorithm for polynomial complexity for this class of problems has been found by humans. However, the more important reason is that for the functional identification of the combinatorial Cell, the pin mapping relationship of the logical Cell needs to be enumerated before running the core formal verification algorithm because the correct pin mapping relationship of the logical Cell is not known. However, the enumeration number of the mapping relationship is usually positively correlated with the factorization of the pin number of the Logic Cell. Therefore, these methods inevitably run factorial kernel formalization algorithms, with the complexity of each formalization algorithm being exponential in magnitude.

Due to the defects of the two methods at present, namely the contradiction that the correctness and the operation efficiency cannot be considered at the same time. The application provides a formal identification method of a combined logic unit, which comprises the following steps: receiving input data; analyzing the number of output pins in the input data; analyzing the number of input pins in the input data in response to determining that the number of output pins is 1; performing symmetry clustering based on the input pins in response to determining that the number of the input pins is not 1; calling a corresponding recognition algorithm according to the symmetrical clustering result, and performing formal recognition of a combinational logic unit on the input data; and outputting the recognition result.

According to the formal identification method of the combinational logic unit, the number of the output pins and the number of the input pins are preliminarily analyzed, the clustering is carried out based on the input pins by utilizing the symmetrical clustering, and then the corresponding identification algorithm is called for each clustering result to carry out the formal identification of the combinational logic unit, so that the corresponding identification result is obtained, on one hand, the correctness is ensured, and on the other hand, the high efficiency of the operation efficiency is also ensured.

FIG. 1 shows a schematic diagram of a computer device 100 according to an embodiment of the application. The computer device 100 may be an electronic device running EDA software and may retrieve and formally recognize data in a Standard Cell Library (Standard Cell Library). As shown in fig. 1, the computer device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Wherein the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively coupled to each other within the electronic device via a bus 110.

The processor 102 may be a Central Processing Unit (CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits. The processor 102 may be used to perform functions associated with the techniques described herein. In some embodiments, processor 102 may also include multiple processors integrated into a single logic component. As shown in FIG. 1, the processor 102 may include a plurality of processors 102a, 102b, and 102 c.

The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, the formal identification of the combinational logic cells may be a computer program stored in memory 104. As shown in fig. 1, the data stored by the memory may include program instructions as well as data to be processed. The processor 102 may also access memory-stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include volatile memory devices or non-volatile memory devices. In some embodiments, the memory 104 may include Random Access Memory (RAM), Read Only Memory (ROM), optical disks, magnetic disks, hard disks, Solid State Disks (SSDs), flash memory, memory sticks, and the like.

The network interface 106 may be configured to provide communications with other external devices to the computer device 100 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the above. It is to be understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, and the like.

Peripheral interface 108 may be configured to connect computer device 100 with one or more peripheral devices for the input and output of information. For example, the peripheral devices may include input devices such as keyboards, mice, touch pads, touch screens, microphones, various sensors, and output devices such as displays, speakers, vibrators, indicator lights, and the like.

The bus 110 may be configured to transfer information between various components of the computer device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (a USB port, a PCI-E bus), and so forth.

It should be noted that although the host architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in a specific implementation, the architecture of the computer device 100 may also include other components necessary for normal operation. Moreover, those skilled in the art will appreciate that the architecture of the computer device 100 described above may also include only the components necessary to implement the embodiments of the present application, and need not include all of the components shown in the figures.

The EDA tool 200 may be run on the computer device 100 shown in FIG. 1. As shown in FIG. 2, the EDA tool may perform circuit Synthesis (Synthesis), for example, converting a Register Transfer Level (RTL) description of a circuit to a true gate level Netlist (Netlist). As shown in FIG. 2, the EDA tool 200 may process the RTL file into a final gate level netlist. The gate-level netlist can be a data structure composed of specific logic gates (instances) and connecting lines (nets) and used to describe the logic structure of a circuit.

In some embodiments, as shown in FIG. 2, the EDA tool 200 may include several modules of syntax analysis 202, Technology Mapping 204, and circuit Optimization 206.

The EDA tool 200 may first parse the RTL file through the parsing 202 to generate an abstract syntax tree. The abstract syntax tree is process independent, and therefore, it is necessary to read each Cell (Cell) from the standard Cell library through the technology map 204 and identify its logic function, and then generate a real netlist from its logic function. In the finally generated gate level network table, the type of the standard Cell (Cell) corresponding to each gate instance needs to be specified. For example, for an abstract description of an AND gate, assign z = x & y, technology map 204 may identify and find an AND gate from within the standard cell library and generate a corresponding netlist based on the AND gate.

After the technology mapping 204 generates the intermediate gate-level netlist, the EDA tool 200 may also optimize the intermediate gate-level netlist using circuit optimization 206 and generate a final gate-level netlist.

In some embodiments, the circuit optimization 206 may further include steps of circuit remapping, standard cell replacement, pin swapping, and the like.

By circuit remapping, it may be meant that the EDA tool 200 reconstructs the topology of the circuit to promote PPA (Power, Performance, Area, i.e., Power consumption, Performance, Area, and generally in chip design, it is desirable to minimize Power consumption and Area and maximize Performance) for a given whole circuit or a small sub-circuit (commonly referred to as logic cone) therein, while ensuring logic equivalence. In general, upon circuit remapping, the EDA tool 200 may render an equivalent abstract representation of the intermediate netlist corresponding to the specified logic con, AND then convert the equivalent abstract representation into an expression, an abstract syntax tree, or NAND Graph (AIG), Majority logic Graph (Majority Graph), AND so on. Similar to the circuit synthesis technology map 204, the EDA tool 200 may generate the target circuit from the recognition results of the standard cell library when the circuit is remapped.

When replacing a standard Cell, the EDA tool 200 may retrieve an equivalent (i.e., logically equivalent) Cell from the library of standard cells based on a given logic gate, thereby providing an optional list of cells, and may derive the cells that meet the PPA requirements based on a selection algorithm based on the optional list of cells. In the step of retrieving equivalent cells, the EDA tool 200 may quickly obtain a list of alternative cells of the same function (i.e., logical equivalent) by identifying the function of the Cell itself.

So-called pin swapping is the swapping of connections for certain pins based on the functional characteristics of the Cell itself. The EDA tool 200 further obtains the symmetry relationship of each pin by querying the functional characteristics of the standard Cell library Cell. The symmetry is facilitated, and the links of the wire nets can be interchanged. The speed of pin swapping is faster relative to replacing a standard cell, and there is also no need to relocate the current gate, with less impact on PPA.

In some embodiments, the EDA tool 200 may also provide a Graphical User Interface (GUI), and the schematic may be displayed in the graphical user interface. Table 1 below shows some symbols of logical units displayed in the graphical user interface.

TABLE 1

It follows that if the EDA tool 200 is unable to obtain the exact Cell function, the drawing in the interface will be erroneous, making it difficult for the user to identify the correct logic unit from the interface.

In addition, the user can also obtain the function of a certain Cell through the graphical user interface provided by the EDA tool 200, and the function also needs to accurately identify the Cell.

As mentioned above, in the operation process of the EDA tool 200, the logic unit needs to be identified many times, and therefore, the accuracy and the operation efficiency of identifying the logic unit both affect the normal operation of the EDA tool 200.

Fig. 3 shows a flow diagram of an exemplary method 300 provided herein. The method 300 may be implemented by the EDA tool 200 of fig. 2 and may formally identify a combinational logic cell. As illustrated in fig. 3, the method 300 may further include the following steps.

At step 302, the EDA tool 200 may receive input data. The input data may correspond to a combinational logic cell for representing a combinational logic cell. The input data may be a netlist. In some embodiments, if the input data is a logic expression, it can be converted into a netlist by parsing (parsing).

At step 304, the EDA tool 200 may analyze the number of output pins in the input data so that the initialization classification may be done based on the output pins. For example, the abstract description assign y = x for an and gate₁ & x₂It can be determined that the input data includes two input pins (x)₁、x₂) And an output pin (y). Therefore, by analyzing the input data, the number of input pins and output pins therein can be determined.

In some embodiments, if the number of output pins in the input data is greater than 1, the EDA tool 200 may recognize the input data as a complex gate and end the recognition process of the input data, and may further output the recognition result. Alternatively, if the number of output pins in the input data is 0, the EDA tool 200 may recognize the input data as an unknown logic gate, end the recognition process of the input data, and may further output the recognition result.

At step 306, if the number of output pins in the input data is 1, the EDA tool 200 may further analyze the number of input pins in the input data.

In some embodiments, if the number of input pins in the input data is 1, it may be determined that the logic function of the Cell corresponding to the input data may be a direct gate (BUF) or an Inverter (INV). Therefore, it is necessary to further determine whether the input data is specifically a unidirectional gate (BUF) or an inverter gate (INV).

Fig. 4A shows a flow diagram of an exemplary method 402 according to an embodiment of the present application. As shown in fig. 4A, the method 402 of determining whether the input data is specifically a unidirectional gate (BUF) or an Inverter (INV) may further include the following steps.

In step 4022, the EDA tool 200 may determine a Boolean function f (x) and a corresponding reference function f for the input data_refAnd (= x). In the present embodiment, since the number of input pins is 1, the boolean function f (x) is only a function on a single input pin x. Reference function f_refAnd (= x) denotes a function of the equidirectional gate.

At step 4024, the EDA tool 200 may be based on the Boolean function f (x) and the reference function f_ref= x construct Bipartite Decision Diagrams (BDDs), respectively.

In step 4026, the EDA tool 200 may divide the decision map according to the Boolean function f (x) and the reference function f_refA bipartite decision diagram of = x, determining the Boolean function f (x) and the reference function f_ref= x is equivalent. For example, the boolean function f (x) may be determined by comparing the bipartite decision graph of the boolean function f (x) with the reference function f_ref= x whether the bipartite decision graph is the same for determining the boolean function f (x) and the reference function f_ref= x is equivalent.

In step 4028, if the Boolean function f (x) and the reference function f_ref= x equivalents, the EDA tool 200 may recognize the input data as a codirectional gate and end the recognition process of the input data, and may further output the recognition result.

Alternatively, in step 4030, if the Boolean function f (x) and the reference function f_ref= x not equivalent, the EDA tool 200 may recognize the input data as not gate and end the recognition process of the input data, and may further output the recognitionAnd (6) obtaining the result.

At step 308, if the number of input pins in the input data is not 1, the EDA tool 200 may further perform symmetry clustering based on the input pins.

Fig. 4B illustrates a flow diagram of an exemplary method 404 according to an embodiment of the present application. As shown in fig. 4B, in some embodiments, the method 404 of symmetry clustering based on input pins may further include the following steps.

At step 4042, the input pin is set to a variable of the Boolean function f of the input data.

At step 4044, the variables are sorted by how close the input pins are to the output pins. For example, the output pins may be used as a source point, a breadth-first search (BFS) traversal may be performed on the input data, so as to obtain a distance between each input pin and the output pin, and then the variables may be sorted based on the distance. The order of all variables is the increasing order of their distance from the source point, i.e., closer to the source point, the higher the order, based on their distance from the source point as a criterion.

At step 4046, a binary decision diagram is constructed based on the Boolean function f of the input data according to the sorted variables. It can be shown that for any boolean function, there is and only one form of BDD corresponding to it, given the order of the variables. Therefore, in this step, the binary decision diagram constructed based on the sorted variables is unique. Also, in some embodiments, the bipartite Decision graph belongs to a common Reduced Ordered Binary Decision graph (SROBDD). Where Shared may mean that multiple functions can share a BDD node, Reduced may mean that the BDD being built can no longer be simplified, and Ordered may mean that variables in the BDD have a certain order. According to the characteristics of the BDD, when two boolean functions are both described by using SROBDD, the equivalence of the two boolean functions can be realized by comparing whether the root nodes of the SROBDD corresponding to the two boolean functions are equal, that is, the equivalence determination result can be obtained by one-time comparison. In view of this, the embodiments of the present application utilize this characteristic of the BDD to perform logic gate recognition, thereby enabling high efficiency that is not available in the existing formalized recognition methods.

In some embodiments, after constructing the binary decision diagram based on the boolean function f of the input data, the method further comprises: if the number of input pins of the input data is 0, the EDA tool 200 may determine whether the boolean function f is a constant 0 or a constant 1 according to the binary decision diagram. For example, if the binary decision diagram only includes nodes with a constant 0, the boolean function f may be considered as a constant 0; similarly, the binary decision diagram includes only nodes with a constant 1, and the boolean function f may be considered as a constant 1.

If the boolean function f is a constant of 0, the EDA tool 200 may recognize the input data as a normally low gate and end the recognition process of the input data, and may further output the recognition result. If the boolean function f is a constant of 1, the EDA tool 200 may recognize the input data as a normally high gate and end the recognition process of the input data, and may further output the recognition result. Alternatively, if the boolean function f is neither constant 0 nor constant 1, the EDA tool 200 may identify the input data as an unknown logic gate and end the identification process of the input data, and may further output the identification result.

At step 4048, the EDA tool 200 may perform symmetry clustering according to the binary decision diagram if the number of input pins of the input data is greater than 1. By carrying out symmetrical clustering, the input data is divided into one of three possible large classes, so that each type is prevented from being traversed and identified, the processing time is saved, and the operation efficiency is improved.

Fig. 4C shows a flow diagram of an exemplary method 406 according to an embodiment of the application. As shown in fig. 4C, in some embodiments, the method 406 of symmetric clustering according to the binary decision diagram may further include the following steps.

In step 4062, the sorted variables are set as an initial set U, and the initial set is divided into a target set C_iAnd comparing the set R, initializing iAnd = 1. Wherein the target set C_iIncluding a first variable, which is the first variable in the initial set U, and the comparison set R includes the remaining variables except the first variable, i.e., the comparison set R is the target set C_iThe complement on the initial set U.

Next, a set of targets C can be assembled_iAnd (5) expanding.

In step 4064, according to the binary decision diagram, determining a variable in the comparison set R that is symmetric to the first variable. It will be appreciated that if the variables x, y are symmetric within the Boolean function f, then

Based on this, it can be judged whether the two variables are symmetrical.

In step 4066, the variables in the alignment set R that are symmetric to the first variable are moved into the target set C_iAnd collecting the target set C_iAs an element in the final set C.

At step 4068, the remaining variables in the alignment set R are formed into a new initial set U, i.e., U ⟸ R, i ⟸ i + 1. Then, steps 4062 and 4068 are repeated until the latest initial set U is empty.

At step 4070, a final set C = { C) including at least one element is obtained₁ C₂ … C_i …C_n)}。

Thus, in the subsequent step, it can be determined whether the input data is of a symmetric class based on this final set C.

Next, in step 310, the EDA tool 200 may call a corresponding recognition algorithm according to the symmetric clustering result, and perform a formal recognition of the combinational logic unit on the input data to obtain a recognition result. Because the clustering is performed on the basis of the input pins, the corresponding algorithm can be called for each large class to perform identification without traversing all algorithms, and therefore, the identification efficiency is improved.

In some embodiments, invoking a corresponding recognition algorithm according to the symmetric clustering result, and performing formal recognition of the combinational logic unit on the input data includes:

in response to the fact that the symmetrical clustering result is that the input data belong to a symmetrical class, calling an identification algorithm of a symmetrical type combinational logic unit, and identifying the symmetrical type combinational logic unit for the input data; as an alternative embodiment, if the number of elements of the final set C is 1 (| C | =1), it may be determined that the symmetry clustering result is that the input data belongs to a symmetry class;

in response to the fact that the symmetry clustering result is that the input data belong to a completely asymmetric class, calling an identification algorithm of a completely asymmetric type combinational logic unit, and identifying the completely asymmetric type combinational logic unit for the input data; as an alternative, if the number of elements of the final set C is equal to the number of the sorted variables (i.e. the number of elements of the final set C is equal to the number of variables of the boolean function f), it may be determined that the symmetric clustering result is that the input data belongs to a completely asymmetric class;

in response to the fact that the symmetry clustering result is that the input data belong to partial asymmetric classes, calling an identification algorithm of partial asymmetric type combinational logic units, and identifying the partial asymmetric type combinational logic units for the input data; as an optional embodiment, if the number of elements of the final set C is greater than 1 and less than the number of the sorted variables, it may be determined that the symmetric clustering result is that the input data belongs to a partial asymmetric class.

After determining the broad class to which the input data belongs, the specific type of input data may be further identified.

Fig. 5A shows a flow diagram of an exemplary method 502 according to an embodiment of the present application. In some embodiments, as shown in fig. 5A, the method 502 for performing symmetric type combinational logic cell identification on the input data by invoking an identification algorithm of symmetric type combinational logic cells may further include the following steps.

At step 5022, a plurality of recognition algorithms for the initialized symmetric type combinational logic cells are determined. For example, the plurality of recognition algorithms may include algorithms that recognize an AND gate (AND), an OR gate (OR), an exclusive OR gate (XOR), a NAND gate (NAND), a NOR gate (NOR), an exclusive OR gate (XNOR), a Majority gate (Majority). In some embodiments, the plurality of recognition algorithms are formed as a list of algorithms, and each algorithm includes an initialization ordering in the list of algorithms, which may be, for example, an ordering based on the complexity of the recognition algorithm or how often the algorithm's corresponding logic gates appear in the circuit. For example, the list of initially ordered algorithms may be { AND, OR, XOR, NAND, NOR, XNOR, Majority }.

At step 5024, the plurality of recognition algorithms are reordered (e.g., the list of algorithms is reordered) based on name features in the input data. For example, if a name feature of a certain Logic Cell (Logic Cell), such as an exclusive-nor gate, is recognized from the input data, the recognition algorithm of the exclusive-nor gate can be advanced to the top of the algorithm list, and then the exclusive-nor gate is recognized first. If no name feature is recognized from the input data or the logical unit corresponding to the name feature is not a symmetric type combinational logical unit, the algorithm list may not be reordered.

At step 5026, the input data is sequentially identified by the symmetric type combinational logic units according to the sorted identification algorithm (e.g., the sorted algorithm list).

In some embodiments, the algorithm to identify the AND gate (AND) may include:

according to the binary decision diagram of the primitive function f constructed in the previous step 4046, the last two variables x and y (i.e., the variables corresponding to the leaf node with the lowest order in the binary decision diagram) are selected from the ordered variables, and the other variables except x and y in the ordered variables are set to be 1. Typically, the size of a BDD is O (m), where m is the number of nodes of the BDD. Since the variables used to construct the BDD are sorted when the BDD is constructed in step 4046, it can be considered that o (m) = o (n) and n is the number of the sorted variables in the normal case.

Based on the boolean function f (x, y, others =1), in combination with the bipartite decision graph of the primitive function f, the BDD of the first subgraph, i.e. the calculation function f (x, y, others =1), is calculated. Due to the special choice of variables, the first sub-graph corresponding to the function f (x, y, others =1) is a sub-graph (also a binary decision graph) of the BDD of the primitive function f, and the method for finding this sub-graph is to trace down from its root node along the high (Hi) edge (the edge whose variable is positive (1)) of the BDD of the primitive function f until x or y is encountered, at which time, all BDD nodes along this path are the roots of the first sub-graph, that is, the first sub-graph corresponding to f (x, y, others = 1). This step may be completed within O (n) time, depending on the characteristics of the BDD.

Based on a reference function f_ref= x · y, construction of the reference function f_refA binary decision diagram of = x · y, it being understood that the variables x, y are in the corresponding order, with reference to the function f_refThe bipartite decision diagram of = x · y is also unique; this step can be done within O (1) time, depending on the characteristics of the BDD.

Based on the first subgraph and the reference function f_ref= x · y bipartite decision diagram, determining a boolean function f (x, y, others =1) and a reference function f_refAnd (d) = x · y is equivalent. If the Boolean function f (x, y, others =1) is compared with the reference function f_ref= x · y, etc., the input data may be determined to be an AND gate (AND). According to the characteristics of the BDD, when both boolean functions are described by SROBDD, their equivalence can be known by comparing whether the root nodes of their SROBDD are equal (i.e., one comparison), and therefore, this step can be done in O (1) time.

It is understood that if the boolean function f (x, y, others =1) is compared with the reference function f_ref= x · y is not equivalent, the next algorithm in the list of algorithms may continue to be called to identify the input parameter.

Therefore, the algorithm of the embodiment is adopted to identify the AND gate, because the well-constructed BDD is utilized, the identification can be completed only by spending O (n) + O (1) + O (1), and compared with the original identification algorithm, the algorithm has the double effects of high accuracy and high operation efficiency.

Specifically, since the present embodiment adopts a formalized method, and the correctness of each step of operation can be mathematically proven, the method of the present embodiment can be used to obtain a correct result, which is an and gate or not an and gate. Compared with other general formalization methods, the method has the advantages that: the matching process of the permutation and combination of the input pins is avoided because the input pins are matched with O (n |) possibilities in the worst case. The present embodiment makes full use of the symmetry of the and gate pins, so only one kind of matching is needed. At the same time, the recognition of the n-input AND gate is converted into a two-input AND gate recognition, i.e. the reference function f, by the characteristics of the AND gate_refThe = x · y can be a two-input and function, requiring only O (1) time to construct its BDD.

In some embodiments, except that a corresponding function needs to be constructed when constructing the reference function, the algorithm for identifying an exclusive or gate (XOR) and a NAND gate (NAND) is similar to the aforementioned algorithm for identifying an and gate, and has similar technical effects, and details are not repeated herein.

In some embodiments, the algorithm to identify an OR gate (OR) may include:

according to the binary decision diagram of the primitive function f constructed in the previous step 4046, two last variables x and y are selected from the sorted variables, and the other variables except x and y in the sorted variables are set to be 0.

Calculating a first subgraph, namely calculating the BDD of the function f (x, y, others =0), based on the Boolean function f (x, y, others =0) and combining the bipartite decision diagram of the primary function f; due to the special choice of variables, the first sub-graph corresponding to the function f (x, y, others =0) is a sub-graph (also a binary decision graph) of the BDD of the primitive function f, and the method for finding this sub-graph is to trace down from its root node along the low (Lo) edge (the edge with the variable being negative (0)) of the BDD of the primitive function f until x or y is encountered, at which time, all BDD nodes along this path are the roots of the first sub-graph, that is, the first sub-graph corresponding to f (x, y, others = 0). This step may be completed within o (n) time, depending on the characteristics of the BDD.

Based on a reference function f_ref= x + y, constructing the reference function f_refA bipartite decision diagram of = x + y, it being understood that the variables x, y, because they have a corresponding order, are referenced to a function f_refThe bipartite decision diagram of = x + y is also unique; this step can be done within O (1) time, depending on the characteristics of the BDD.

Based on the first subgraph and the reference function f_ref= x + y bipartite decision diagram, determining boolean function f (x, y, others =0) and reference function f_ref= x + y is equivalent; if the Boolean function f (x, y, others =0) and the reference function f_ref= x + y is equivalent, the input data may be determined to be an OR gate (OR). According to the characteristics of the BDD, when both boolean functions are described by SROBDD, their equivalence can be known by comparing whether the root nodes of their SROBDD are equal (i.e., one comparison), and therefore, this step can be done in O (1) time.

It can be understood that if the boolean function f (x, y, others =0) is compared with the reference function f_ref= x + y is not equivalent, the next algorithm in the list of algorithms may continue to be called to identify the input parameter.

Therefore, the algorithm of the embodiment is adopted to identify the or gate, because the constructed BDD is utilized, the identification can be completed only by spending O (n) + O (1) + O (1), and compared with the original identification algorithm, the algorithm has the double effects of high accuracy and high operation efficiency. In particular, the present embodiment avoids the matching process of the permutation and combination of the input pins, because the worst case input pin matching is possible with a kind of O (n!). The present embodiment takes full advantage of the symmetry of the or gate pins, so only one match is needed. At the same time, the identification of the n-input or-gate is converted into a two-input or-gate identification by means of the characteristics of the or-gate, i.e. the reference function f_ref= x + y may be a two-input or function, requiring only O (1) time to construct its BDD.

In some embodiments, except that a corresponding function needs to be constructed when constructing the reference function, the algorithm for identifying the exclusive or gate (XNOR) and the NOR gate (NOR) is similar to the algorithm for identifying the exclusive or gate, and has similar technical effects, and is not described herein again.

In some embodiments, the algorithm for identifying the master authority (major) may include:

since the output of major is 1 and only if more than 50% of the variables are all 1, the first half of the ordered variables are selected according to the binary decision diagram that has been constructed in step 4046 (

) The variable of (3) is set to 1, and the other variables are unchanged.

Based on the Boolean function f: (

highest =1), and calculating a first subgraph by combining the binary decision diagram; this step may be completed within O (n) time.

Determining a Boolean function f (based on the first subgraph)

highest =1) is constantly equal to 1; for example, by determining a Boolean function f (

highest =1) whether the corresponding BDD expression has only one root node and its root node is a constant 1 node to determine the boolean function f (1)

highest =1) is constantly equal to 1; in response to determining the Boolean function f (

highest =1) is always equal to 1, and the input data is determined to be the master quantum gate. This step can be completed within O (1) time.

It will be appreciated that if the master quantum gate is not identified, the next algorithm in the list of algorithms may continue to be called to identify the input parameter.

Therefore, the algorithm of the embodiment is adopted to identify the or gate, because the constructed BDD is utilized, the identification can be completed only by spending O (n) + O (1) + O (1), and compared with the original identification algorithm, the algorithm has the double effects of high accuracy and high operation efficiency.

It will be appreciated that the EDA tool 200 may end the recognition process of the input data after any algorithm in the algorithm list identifies the corresponding combinational logic cell, and may further output the recognition result. When each algorithm in the algorithm list is used and cannot recognize the input data as any symmetric type combinational logic cell, the EDA tool 200 may recognize the input data as a complex gate and end the recognition process of the input data, and may further output the recognition result.

In some embodiments, invoking an identification algorithm of a completely asymmetric type combinational logic unit to identify the completely asymmetric type combinational logic unit for the input data comprises: and calling an identification algorithm of a multiplex gate (MUX) to identify the multiplex gate for the input data.

Fig. 5B shows a flowchart diagram of an exemplary method 504 according to an embodiment of the application. As shown in FIG. 5B, in some embodiments, the method 504 of identifying the mux gate for the input data may further include the following steps.

At step 5042, the sorted variables are divided into k control signals andldata signal (i.e. k +l= n), wherein k andlsatisfies the following conditions: 2^k≥lAnd > k. In this step, a feasible pair of k,lThe value and ensure that k is minimal. Specifically, k can be tried from 1 to n if 2 is satisfied^k≥lK > k can be stopped and a feasible pair of k,lOtherwise, the method continues until a feasible pair of k,lThe value is obtained. When the end loop is k = n, the input data may be determined as a complex gate, and the recognition process of the input data may be ended, and the recognition result may be further output.

At step 5044, responsive to determining that k is less than the number of the ordered variables (i.e., resulting in a pair of k satisfying a condition,lValue), the difference ∂ f/∂ x of the boolean function f may be calculated in turn for the sorted variables according to the binary decision diagram that has been constructed in the previous step 4046. That is, from this step, the difference ∂ f/∂ x of the boolean function f (assuming that the current variable is x) is calculated sequentially (ordered from high to low) for each of the ordered variables. This step may be completed at O (n) time.

According to Shannon's expansion principle, for any n-ary Boolean function f (x)₁ x₂ … x_i … x_n) According to the Shannon's unfolding principle, f (x)₁ x₂ … x_i … x_n)=x_i∙f(x₁ x₂ … x_i=1 … x_n)+

∙f(x₁ x₂ … x_i=0 … x_n) (ii) a Wherein the Positive cofactor (Positive cofactor) is fx = f (x)₁ x₂ … x_i=1 … x_n) Negative cofactors (Negative cofactors)

=f(x₁ x₂ … x_i=0 … x_n)。

The Boolean Difference (Boolean Difference) is calculated as:

。

at step 5046, it is determined whether the number of valid variables in the difference ∂ f/∂ x of the Boolean function for the current variable x is greater than k. Wherein a valid variable may refer to a variable that is not 0 or 1.

At step 5048, in response to determining that the number of valid variables is greater than k, the current variable x is marked as a control variable.

In step 5050, in response to determining that the number of valid variables is less than or equal to k, the current variable is marked as a data variable and it is determined whether there is and only one path from the root node of the BDD of the difference ∂ f/∂ x of the Boolean function to the node of logic 1.

In step 5052, in response to determining that there is and only one path from the root node of the first subgraph to the node of logic 1, all variables on the path are marked as control variables.

At step 5054, a determination is made as to whether a tag conflict exists. That is, whether there is a variable that has been marked is marked as both a control variable and a data variable.

In response to determining that no marker conflict exists, at step 5056, processing of a next variable of the sorted variables continues until the sorted variables are all processed and no marker conflict exists, the input data may be determined to be a multi-way select gate, the identification process of the input data may be ended, and the identification result may be further output. Meanwhile, according to the information obtained in the previous step, it can be obtained under the coordination of which control signal each data variable is gated.

Steps 5046-5056 may be completed within O (mn) time.

It is to be understood that, in the above processing procedure, if there is a tag conflict after the execution of any step is finished, it may be determined that the input data is a complex gate, and the identification process of the input data is finished, and the identification result may be further output.

Therefore, the algorithm of the embodiment is adopted to identify the multi-way selection gate, and because the constructed BDD is utilized, the identification can be completed only by spending O (n) + O (mn), and compared with the original identification algorithm, the algorithm has the double effects of high accuracy and high operation efficiency.

In some embodiments, invoking an identification algorithm for a partially asymmetric type combinational logic cell to identify the partially asymmetric type combinational logic cell for the input data comprises: and calling an identification algorithm of the composite gate to identify the composite gate for the input data.

Fig. 5C shows a flow diagram of an exemplary method 506 according to an embodiment of the application. As shown in FIG. 4C, in some embodiments, the method 506 of identifying composite gates on the input data may further include the following steps.

In some embodiments, invoking a recognition algorithm of a composite gate to perform composite gate recognition on the input data specifically includes:

at step 5062, j groups (cluster) of the input data are determined. For example, j can be determined according to the number of elements of the aforementioned final set C, in other words, the number of elements of the final set C is j.

The function of each group may then be determined, and this step may be completed at O (m) time. Specifically, the method comprises the following steps:

at step 5064, it is determined whether the function of each group is an AND (AND) OR an OR (OR) based on the binary decision map.

If there is only one variable inside cluster, the function of this group can be considered as AND OR OR (OR).

If more than two variables exist in the cluster, it is further determined whether the function of the cluster is an AND (AND) OR (OR).

=f(x₁ x₂ … x_i=0 … x_n)。

The Boolean Difference (Boolean Difference) is calculated as:

。

if it is determined whether the group of functions is an AND function, the following steps may be performed:

selecting variable x in current group and highest sequence in the binary decision diagram, and calculating

. This step may be completed at O (m) time. The variable x in the current group is ranked according to the variable sequence in the binary decision diagram of the original function f, and the variable x in the current group has the highest sequence.

Then, the variable y in the current group and in the order of the second highest in the binary decision diagram is selected and calculated

. This step may be completed at O (m) time. The variable in the current group is ranked according to the variable sequence in the binary decision diagram of the original function f, and the variable y is the second highest in the sequence in the current group.

If it is

Then the function of the group may be determined to be and. This step may be done at O (1) time.

If it is determined whether the function of the group is yes, the following steps may be performed:

the variable x in the current group and with the highest order in the binary decision diagram is selected and fx is calculated. This step may be completed at O (m) time.

The variable y within the current group and sequentially next in the binary decision diagram is then selected and ∂ fx/∂ y is calculated. This step may be completed at O (m) time.

If it is

Then the group's function may be determined to be or. This step may be done at O (1) time.

If the function of any one cluster is neither AND nor OR, the input data is recognized as a complex gate, otherwise the next step is entered.

At step 5066, it is determined whether the function between the groups is NAND or NOR. This step may be completed at O (m) time. Specifically, the method comprises the following steps:

if the function of cluster is AND, then select one of the lowest BDD order variables from the cluster and set the other variables to 1.

If the function of the cluster is 'or', selecting a variable with the lowest BDD sequence from the cluster, and setting other variables as '1'.

With the foregoing NOR and NAND identification methods, it is confirmed whether the logic is NOR or NAND determined according to the two variables selected.

At step 5068, in response to determining that the function of the bank is OR and the function between the banks is NAND, determining that the input data is OR-NAND. In some embodiments, for a group with only one variable, its logical type may be considered the same as that of another group. Here, if there are two groups whose interclass function is nand and one group has an or function, then if the other group is a univariate group, the logic type of the univariate group can be considered to be also or, and further the input data can be determined to be an or nand gate.

At step 5070, in response to determining that the function of the group is AND and the function between the groups is NOR, the input data is determined to be an AND NOR gate. Similar to step 5068, in some embodiments, for a group having only one variable, its logic type may be considered the same as that of another group. Here, if there are two groups whose interclass function is nor and one of the two groups has an and function, then if the other group is a univariate group, the logic type of the univariate group can be considered to be also and, and the input data can be determined to be an and nor gate.

In some embodiments, in response to determining that the input data is not an or-nand gate or an and-nor gate, the input data is determined to be a complex gate, and the identification process of the input data is ended, and the identification result may be further output.

Therefore, the algorithm of the embodiment is adopted to identify the composite gate (particularly the nand gate and the nor gate), and because the well-constructed BDD is utilized, the identification can be completed only by spending o (m) + o (m), and compared with the original identification algorithm, the algorithm has the double effects of high accuracy and high operating efficiency.

In some embodiments, the recognition result may be output by the EDA tool 200 to an interface provided by the EDA tool 200, and may be used for the EDA tool 200 to perform circuit synthesis, circuit optimization, and other processing steps to realize functions such as circuit layout, circuit simulation, and the like.

It can be seen from the foregoing embodiments that the embodiments of the present application adopt a formalized method, and each operation of the steps can be mathematically proven to be correct, so that correct results can be obtained by using the methods of the embodiments of the present application. The high efficiency is realized compared with other general formalization methods: the matching process of the permutation and combination mode of the input pins is avoided, and the input pins are possibly matched in the worst case. Because the embodiment of the application makes full use of the symmetry of the pins of the logic unit, only one matching is needed. Meanwhile, the identification of the n-input logic gate is converted into the identification of the two-input logic gate by utilizing the characteristics of the logic unit, and the BDD is constructed only in a short time.

It should be noted that the method of the embodiment of the present application may be executed by a single device, such as a computer or a server. The method of the embodiment can also be applied to a distributed scene and completed by the mutual cooperation of a plurality of devices. In such a distributed scenario, one of the multiple devices may only perform one or more steps of the method of the embodiment, and the multiple devices interact with each other to complete the method.

It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Based on the same inventive concept, corresponding to any of the above-described embodiment methods, the present application also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the method 300 according to any of the above embodiments.

Computer-readable media of the present embodiments, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the method 300 according to any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, and are not described herein again.

The present application also provides a computer program product comprising a computer program, corresponding to any of the embodiment methods 300 described above, based on the same inventive concept. In some embodiments, the computer program is executable by one or more processors to cause the processors to perform the method 300. Corresponding to the execution subject corresponding to each step in the embodiments of the method 300, the processor executing the corresponding step may be the corresponding execution subject.

The computer program product of the foregoing embodiment is used for enabling a processor to execute the method 300 according to any of the foregoing embodiments, and has the advantages of corresponding method embodiments, which are not described herein again.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the context of the present application, features from the above embodiments or from different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.

In addition, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the embodiments of the application. Further, devices may be shown in block diagram form in order to avoid obscuring embodiments of the application, and this also takes into account the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the application are to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that the embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.

While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic ram (dram)) may use the discussed embodiments.

The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present application are intended to be included within the scope of the present application.

Claims

1. A formalized identification method of a combined logic unit comprises the following steps:

receiving input data;

analyzing the number of output pins in the input data;

calling a corresponding recognition algorithm according to the symmetrical clustering result, and performing formal recognition of a combinational logic unit on the input data to obtain a recognition result;

wherein, carry out symmetry clustering based on input pin, include:

setting an input pin as a variable of a Boolean function f of the input data;

sorting the variables according to the distance between the input pin and the output pin;

constructing a binary decision diagram based on a Boolean function f of the input data according to the sorted variables; and

and carrying out symmetry clustering according to the bipartite decision diagram to obtain a final set comprising at least one element, judging whether the input data is a symmetry class or not based on the final set, and determining a symmetry clustering result.

2. The method of claim 1, wherein invoking a corresponding recognition algorithm to formally recognize a combinational logic unit for the input data according to the symmetric clustering result comprises:

in response to the fact that the symmetrical clustering result is that the input data belong to a symmetrical class, calling an identification algorithm of a symmetrical type combinational logic unit, and identifying the symmetrical type combinational logic unit for the input data;

in response to the fact that the symmetry clustering result is that the input data belong to a completely asymmetric class, calling an identification algorithm of a completely asymmetric type combinational logic unit, and identifying the completely asymmetric type combinational logic unit for the input data; or

And calling an identification algorithm of a part of asymmetric type combinational logic units to identify the part of asymmetric type combinational logic units of the input data in response to the fact that the symmetry clustering result is that the input data belong to the part of asymmetric classes.

3. The method of claim 1, wherein after analyzing the number of output pins in the input data, further comprising:

identifying the input data as a complex gate in response to determining that the number of output pins is greater than 1; or

In response to determining that the number of output pins is 0, identifying the input data as an unknown logic gate.

4. The method of claim 1, wherein symmetrically clustering according to the bipartite decision graph comprises:

setting the sorted variables as an initial set, and dividing the initial set into a target set and a comparison set, wherein the target set comprises a first variable, the first variable is a first sorted variable in the initial set, and the comparison set comprises the remaining variables except the first variable;

determining variables symmetrical to the first variable in the comparison set according to the binary decision diagram;

shifting variables symmetrical to the first variable in the comparison set into the target set, and taking the target set as one element in a final set;

forming the remaining variables in the comparison set into a new initial set, and repeatedly executing the steps of dividing the initial set into a target set and a comparison set until the remaining variables in the comparison set are formed into the new initial set until the latest initial set is empty;

a final set comprising at least one element is obtained.

5. The method of claim 4, wherein invoking a corresponding recognition algorithm to formally recognize the combinational logic unit of the input data according to the symmetric clustering result comprises:

in response to determining that the number of elements of the final set is 1, determining that the symmetric clustering result is that the input data belongs to a symmetric class;

in response to determining that the number of elements of the final set is equal to the number of the sorted variables, determining that the symmetric clustering result is that the input data belongs to a completely asymmetric class; or

And in response to determining that the number of elements of the final set is greater than 1 and less than the number of the sorted variables, determining that the symmetric clustering result is that the input data belongs to a partially asymmetric class.

6. The method of claim 5, wherein invoking an identification algorithm for symmetric type combinational logic cells to identify symmetric type combinational logic cells on the input data comprises:

determining a plurality of identification algorithms for the initialized symmetric type combinational logic cells;

sorting the plurality of recognition algorithms according to name features in the input data; and

and sequentially identifying the symmetrical type combination logic units of the input data according to the sorted identification algorithm.

7. The method of claim 6, wherein the plurality of identification algorithms comprises at least two of an algorithm to identify an AND gate, an algorithm to identify an OR gate, an algorithm to identify an XOR gate, an algorithm to identify an XNOR gate, an algorithm to identify a NAND gate, an algorithm to identify a NOR gate, and an algorithm to identify a majority gate.

8. The method of claim 5, wherein invoking an identification algorithm for a completely asymmetric type combinational logic cell to identify the completely asymmetric type combinational logic cell on the input data comprises:

and calling an identification algorithm of a multi-way selection gate to identify the multi-way selection gate for the input data.

9. The method of claim 5, wherein invoking an identification algorithm for a partially asymmetric type combinational logic cell to identify the partially asymmetric type combinational logic cell on the input data comprises:

and calling an identification algorithm of the composite gate to identify the composite gate for the input data.

10. A computer device comprising one or more processors, memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, the programs comprising instructions for performing the method of any of claims 1-9.

11. A non-transitory computer-readable storage medium containing a computer program which, when executed by one or more processors, causes the processors to perform the method of any one of claims 1-9.

12. A computer program product comprising computer program instructions which, when run on a computer, cause the computer to perform the method of any one of claims 1-9.