CN114387936B - Pixel structure and display panel - Google Patents
Pixel structure and display panel Download PDFInfo
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- CN114387936B CN114387936B CN202210146175.8A CN202210146175A CN114387936B CN 114387936 B CN114387936 B CN 114387936B CN 202210146175 A CN202210146175 A CN 202210146175A CN 114387936 B CN114387936 B CN 114387936B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
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Abstract
The invention discloses a pixel structure and a display panel. The pixel structure comprises a first pixel, a second pixel, a scanning line, a first data line and a second data line: the first pixel comprises a first main pixel area and a first sub pixel area; the second pixel comprises a second main pixel area and a second secondary pixel area; the scanning line is positioned between the first main pixel area and the first sub pixel area and is simultaneously positioned between the second main pixel area and the second sub pixel area; the first data line comprises a first data line main area part and a first data line sub area part; the second data line includes a second data line main area portion and a second data line sub area portion; the first data line sub-area part and the second data line sub-area part are simultaneously positioned on the first sub-pixel area; the signal electrical property of the first data line is opposite to the signal electrical property of the second data line. The invention can counteract the coupling effect of the first data line and the second data line on the first pixel so as to relieve the crosstalk problem between two adjacent pixels.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a pixel structure and a display panel.
Background
The 1G1D3Tpulse architecture (a scan line-data line three transistor thin film transistor architecture) has been increasingly used in lcd panels. In a conventional display panel of 1G1D3Tpulse architecture, a data line for controlling the display brightness of the pixel is disposed on each pixel.
On two adjacent pixels, the corresponding voltage transient variation in two data lines can cause a capacitive coupling effect with the pixels, so that the two adjacent pixels generate crosstalk phenomenon.
Disclosure of Invention
Based on the above-mentioned shortcomings in the prior art, an object of the present invention is to provide a pixel structure and a display panel, which can alleviate the problem of crosstalk between two adjacent pixels.
To achieve the above object, the present invention provides a pixel structure including:
a first pixel including a first main pixel region and a first sub pixel region;
the second pixel is arranged adjacent to the first pixel and comprises a second main pixel area and a second sub pixel area;
the scanning line is positioned between the first main pixel area and the first sub pixel area and is simultaneously positioned between the second main pixel area and the second sub pixel area;
the first data line comprises a first data line main area part and a first data line sub-area part, the first data line main area part is positioned on the first main pixel area, and the first data line sub-area part is positioned on the first sub-pixel area;
the second data line comprises a second data line main area part and a second data line sub-area part, the second data line main area part is positioned on the second main pixel area, and the second data line sub-area part is positioned on the first sub-pixel area;
the signal electrical property of the first data line is opposite to the signal electrical property of the second data line.
Optionally, the display device further includes a first shared discharging rod, the first shared discharging rod is located on the first pixel, and the first data line sub-area portion and the second data line sub-area portion are symmetrical with respect to the first shared discharging rod.
Optionally, the first data line sub-area portion and the second data line sub-area portion are both located on the opening area of the first sub-pixel area.
Optionally, the first data line main region portion is located on the opening region of the first main pixel region.
Optionally, the second data line main region portion is located on the opening region of the second main pixel region.
Optionally, the circuit breaker further comprises a short circuit detection module, and the metal layers where the first data line sub-area part and the second data line sub-area part are located are electrically connected with the short circuit detection module.
Optionally, the length of the first data line sub-area portion is greater than the length of the first data line main area portion.
Optionally, the length of the second data line secondary section is greater than the length of the second data line primary section.
Optionally, a second shared discharge bar is further included, the second shared discharge bar being located on the second pixel.
The invention also provides a display panel which comprises a substrate and the pixel structure, wherein the pixel structure is arranged on the substrate.
Compared with the prior art, the invention has the beneficial effects that: the invention provides a pixel structure, which comprises a first pixel, a second pixel, a scanning line, a first data line and a second data line; the first pixel comprises a first main pixel area and a first sub pixel area; the second pixel is arranged adjacent to the first pixel and comprises a second main pixel area and a second sub pixel area; the scanning line is positioned between the first main pixel area and the first sub pixel area and is simultaneously positioned between the second main pixel area and the second sub pixel area; the first data line comprises a first data line main area part and a first data line sub-area part, the first data line main area part is positioned on the first main pixel area, and the first data line sub-area part is positioned on the first sub-pixel area; the second data line comprises a second data line main area part and a second data line sub-area part, the second data line main area part is positioned on the second main pixel area, and the second data line sub-area part is positioned on the first sub-pixel area; the signal electrical property of the first data line is opposite to the signal electrical property of the second data line. In the invention, the first data line sub-area part and the second data line sub-area part are simultaneously positioned on the first sub-pixel area and are opposite in electrical property, so that the coupling effect of the first data line and the second data line on the first pixel can be counteracted or reduced. And, the distance that first data line subregion part and second data line subregion part are adjacent is nearer, offset coupling effect's effect can be better.
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In order to more clearly illustrate the embodiments or the technical solutions in the prior art, the following description will briefly introduce the drawings that are needed in the embodiments or the description of the prior art, it is obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a top view of a pixel structure according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a data line layout according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an opening region of a pixel structure according to an embodiment of the invention;
fig. 4 is a circuit diagram of an embodiment 1G1D3Tpulse architecture of the present invention.
Detailed Description
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
The embodiment of the invention provides a pixel structure, as shown in fig. 1 and 2, which comprises a first pixel 1, a second pixel 2, a scanning line 3, a first data line 4 and a second data line 5. Wherein the first pixel 1 includes a first main pixel region 11 and a first sub pixel region 12; the second pixel 2 is disposed adjacent to the first pixel 1, and the second pixel 2 includes a second main pixel region 21 and a second sub pixel region 22; the scanning line 3 is located between the first main pixel area 11 and the first sub pixel area 12 and is located between the second main pixel area 21 and the second sub pixel area 22 at the same time; the first data line 4 includes a first data line main area portion 41 and a first data line sub area portion 42, the first data line main area portion 41 being located on the first main pixel area 11, the first data line sub area portion 42 being located on the first sub pixel area 12; the second data line 5 includes a second data line main area portion 51 and a second data line sub area portion 52, the second data line main area portion 51 being located on the second main pixel area 21, the second data line sub area portion 52 being located on the first sub pixel area 12; the signal electrical property of the first data line 4 is opposite to the signal electrical property of the second data line 5.
In this embodiment, the first data line sub-area portion 42 and the second data line sub-area portion 52 are located on the first sub-pixel area 12 at the same time, and the signals of the two signals are opposite, so that the coupling effect of the first data line 4 and the second data line 5 on the first pixel 1 can be counteracted or reduced. In addition, compared with the prior art, the adjacent two data lines are all located in the corresponding pixel regions, and the distance between the first data line sub-region 42 and the second data line sub-region 52 is closer, so that the effect of counteracting the coupling is stronger.
In one embodiment, the first data line 4 and the second data line 5 are parallel to each other, and the scan line 3 is perpendicular to both the first data line 4 and the second data line 5. This structure facilitates the layout of the traces within the pixel structure.
In an embodiment the pixel structure further comprises a first shared discharge rod 6. The first common discharging rod 6 is used for adjusting the voltage difference in the first sub-pixel area 12 and the first main pixel area 11 to adjust the overall brightness of the first pixel 1. The first shared discharge bar 6 is located on the first pixel 1, and the first data line sub-area portion 42 and the second data line sub-area portion 52 are symmetrical with respect to the first shared discharge bar 6.
In the above structure, the first data line sub-area portion 42 and the second data line sub-area portion 52 are symmetrically arranged on the first sub-pixel area 12, and the distances between the first data line sub-area portion and the first common discharging rod 6 are equal, so that the effect of counteracting the coupling effect can be further enhanced.
In one embodiment, the first shared discharging rod 6 may be located on the center line or the symmetry axis of the first pixel 1, so that the routing of the first data line sub-area portion 42 and the second data line sub-area portion 52 may be more regular, and the effect of counteracting the coupling effect may be further enhanced.
In one embodiment, as shown in fig. 3, the first data line sub-area portion 42 and the second data line sub-area portion 52 are both located on the opening area 121 of the first sub-pixel area 12. Compared with the prior art, the data lines are located in the non-opening area, so that the area of the non-opening area is increased, the area of the opening area is reduced, and the first data line sub-area portion 42 and the second data line sub-area portion 52 of the present embodiment are both located in the opening area 121 of the first sub-pixel area 12, so that the corresponding areas of the first data line sub-area portion 42 and the second data line sub-area portion are combined into the opening area, the area ratio of the opening area of the first sub-pixel area 12 is increased, the opening ratio of the first sub-pixel area 12 is increased, and the light transmittance is increased.
In one embodiment, the first data line main region portion 41 is located on the opening region 111 of the first main pixel region 11. In this way, the area corresponding to the first data line main area portion 41 can be incorporated into the opening area 111 of the first main pixel area 11, the opening area ratio of the first main pixel area 11 can be enlarged, and the opening ratio of the first main pixel area 11 can be improved.
In one embodiment, the second data line main region portion 51 is located on the opening region 211 of the second main pixel region 21. In this way, the area corresponding to the second data line main area portion 51 can be incorporated into the opening area 211 of the second main pixel area 21, the opening area ratio of the second main pixel area 21 can be enlarged, and the opening ratio of the second main pixel area 21 can be improved.
In one embodiment, the short circuit detection module further includes a metal layer where the first data line sub-area portion 42 and the second data line sub-area portion 52 are located, and is electrically connected to the short circuit detection module. The first data line sub-area portion 42 and the second data line sub-area portion 52 are located on the first sub-pixel area 12 at the same time, and the first data line sub-area portion 42 is separated from the second data line sub-area portion 52 by a relatively short distance, so that there is a possibility that the metal layers where the first data line sub-area portion 42 and the second data line sub-area portion 52 are located are in contact to cause a short circuit. According to the embodiment, the short circuit detection module can be arranged in the frame area of the display panel so as to monitor the short circuit condition of the metal layer, and when the short circuit occurs, the short circuit detection module can be used for timely processing.
In one embodiment, the length of the first data line sub-section 42 is greater than the length of the first data line main section 41. Correspondingly, the area of the first sub-pixel region 12 is larger than the area of the first main pixel region 11. Therefore, the duty ratio of the first data line sub-area part 42 in the first data line 4 can be improved, the wiring length of the first data line sub-area part 42 is longer, and the effect of counteracting the coupling effect is better.
In one embodiment, the length of the second data line secondary section 52 is greater than the length of the second data line primary section 51. Correspondingly, the area of the second sub-pixel area 22 is larger than the area of the second main pixel area 21. This can increase the duty ratio of the second data line sub-area portion 52 in the second data line 5, so that the trace length of the second data line sub-area portion 52 is longer and the effect of counteracting the coupling effect is better.
In one embodiment, the first data line sub-section 42 may have a 60% to 80% duty ratio in the first data line 4, and the second data line sub-section 52 may have a 60% to 80% duty ratio in the second data line 5.
In an embodiment the pixel structure further comprises a second shared discharge rod 7, the second shared discharge rod 7 being located on the second pixel 2. The second shared discharging rod 7 is used for adjusting the voltage difference between the second sub-pixel area 22 and the second main pixel area 21 to adjust the overall brightness of the second pixel 2. In a preferred embodiment, the second shared discharging rod 7 may be located on the center line or the symmetry axis of the second pixel 2, so that the layout of the pixel structure may be more regular.
The pixel structure of the present embodiment may be provided with a plurality of pixels on the display panel, wherein the first pixel 1 and the second pixel 2 may be regarded as one cyclic pixel unit, and are regularly arranged on the display panel, but may possibly bring about a defect of reduced resolution of the display panel. Therefore, in this embodiment, two sharing discharging rod wires may be separately led out and connected to the first sharing discharging rod 6 and the second sharing discharging rod 7, so that the voltage signals of the first sharing discharging rod 6 and the second sharing discharging rod 7 may be adjusted separately to adjust the display signals of the first pixel 1 and the second pixel 2, so as to overcome the above-mentioned drawbacks. Meanwhile, since the first data line 4 and the second data line 5 may cause a shading problem in the opening area, resulting in inconsistent brightness of the adjacent pixels, the brightness of the adjacent pixels may be optimized by individually adjusting the voltage signals of the first common discharging bar 6 or/and the second common discharging bar 7.
The pixel structure of the embodiment is improved on the basis of a 1G1D3Tpulse architecture. The circuit diagram of the 1G1D3Tpulse architecture is shown in fig. 4, and includes a main pixel area thin film transistor tft_m, a main pixel area liquid crystal capacitor clc_m, a main pixel area storage capacitor cst_m, a sub pixel area thin film transistor tft_s, a sub pixel area liquid crystal capacitor clc_s, a sub pixel area storage capacitor cst_s, and a shared thin film transistor tft_share, wherein a scan line 3Gate is respectively provided corresponding to each row of pixels, and a Data line Data is respectively provided corresponding to each column of pixels; the Gate electrode of the main pixel region thin film transistor tft_m is connected to the scan line 3Gate, the source/drain electrode thereof is connected to the Data line Data, and the main pixel region liquid crystal capacitor clc_m and the main pixel region storage capacitor cst_m are connected in parallel between the drain/source electrode thereof and the common electrode a_com (or c_com); the grid electrode of the sub-pixel area thin film transistor TFT_s is connected with a scanning line 3Gate, the source electrode/drain electrode of the sub-pixel area thin film transistor TFT_s is connected with a Data line Data, and a sub-pixel area liquid crystal capacitor Clc_s and a sub-pixel area storage capacitor cst_s are connected in parallel between the drain electrode/source electrode and a common electrode A_com (or C_com); the Gate electrode of the sharing thin film transistor tft_share is connected to the scan line 3Gate, and the source electrode and the drain electrode thereof are connected to the drain electrode/source electrode of the sub-pixel region thin film transistor tft_s and the common electrode a_com, respectively.
It will be understood by those skilled in the art that although the common electrodes a_com and c_com are different in name, in an actual liquid crystal panel, both are generally the same in potential, and may be represented by only the common electrode a_com; since the thin film transistor has the same characteristics as the source and drain, the source and drain are not particularly limited in the circuit; in the stereoscopic structure of the liquid crystal display panel, the two electrodes of the liquid crystal capacitor and the storage capacitor generally correspond to a pixel electrode (or a storage electrode having the same potential as the pixel electrode) and a common electrode, respectively.
In this embodiment, the pixel structure includes a substrate, a first metal layer, an insulating layer, and a second metal layer. Wherein the first metal layer is formed with the scan lines 3 and the second metal layer is formed with the first data lines 4 and the second data lines 5. The second gold layer is positioned on the substrate, the insulating layer is positioned on the second metal layer, and the first metal layer is positioned on the insulating layer.
In one embodiment, the substrate may be a glass substrate, and the materials of the first metal layer and the second metal layer include one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). The material of the insulating layer includes at least one of silicon oxide and silicon nitride.
The pixel structure of the embodiment can offset or better relieve the crosstalk phenomenon between the first pixel 1 and the second pixel 2, and simultaneously improve the aperture opening ratio of the first pixel 1 and the second pixel 2, improve the light transmittance of the first pixel 1 and the second pixel 2, and enhance the display effect.
The embodiment of the invention provides a display panel, which comprises a substrate and the pixel structures provided by the embodiment, wherein the pixel structures are arranged on the substrate and are distributed in an array mode. The display panel of the present embodiment includes a liquid crystal display panel.
Specifically, the pixel structure of the display panel of the present embodiment includes a first pixel 1, a second pixel 2, a scan line 3, a first data line 4 and a second data line 5. Wherein the first pixel 1 includes a first main pixel region 11 and a first sub pixel region 12; the second pixel 2 is disposed adjacent to the first pixel 1, and the second pixel 2 includes a second main pixel region 21 and a second sub pixel region 22; the scanning line 3 is located between the first main pixel area 11 and the first sub pixel area 12 and is located between the second main pixel area 21 and the second sub pixel area 22 at the same time; the first data line 4 includes a first data line main area portion 41 and a first data line sub area portion 42, the first data line main area portion 41 being located on the first main pixel area 11, the first data line sub area portion 42 being located on the first sub pixel area 12; the second data line 5 includes a second data line main area portion 51 and a second data line sub area portion 52, the second data line main area portion 51 being located on the second main pixel area 21, the second data line sub area portion 52 being located on the first sub pixel area 12; the signal electrical property of the first data line 4 is opposite to the signal electrical property of the second data line 5.
In the display panel of the present embodiment, the first data line sub-area portion 42 and the second data line sub-area portion 52 are located on the first sub-pixel area 12 at the same time, and the signals of the two signals are opposite, so that the coupling effect of the first data line 4 and the second data line 5 on the first pixel 1 can be counteracted or reduced. In addition, compared with the prior art, the adjacent two data lines are all located in the corresponding pixel regions, and the distance between the first data line sub-region 42 and the second data line sub-region 52 is closer, so that the effect of counteracting the coupling is stronger.
In one embodiment, the first data line 4 and the second data line 5 are parallel to each other, and the scan line 3 is perpendicular to both the first data line 4 and the second data line 5. This structure facilitates the layout of the traces within the pixel structure.
In an embodiment the pixel structure further comprises a first shared discharge rod 6. The first common discharging rod 6 is used for adjusting the voltage difference in the first sub-pixel area 12 and the first main pixel area 11 to adjust the overall brightness of the first pixel 1. The first shared discharge bar 6 is located on the first pixel 1, and the first data line sub-area portion 42 and the second data line sub-area portion 52 are symmetrical with respect to the first shared discharge bar 6.
In the above structure, the first data line sub-area portion 42 and the second data line sub-area portion 52 are symmetrically arranged on the first sub-pixel area 12, and the distances between the first data line sub-area portion and the first common discharging rod 6 are equal, so that the effect of counteracting the coupling effect can be further enhanced.
In one embodiment, the first shared discharging rod 6 may be located on the center line or the symmetry axis of the first pixel 1, so that the routing of the first data line sub-area portion 42 and the second data line sub-area portion 52 may be more regular, and the effect of counteracting the coupling effect may be further enhanced.
In one embodiment, the first data line sub-area portion 42 and the second data line sub-area portion 52 are both located on the opening area of the first sub-pixel area 12. Compared with the prior art, the data lines are located in the non-opening area, occupy the area of the opening area, and the first data line sub-area portion 42 and the second data line sub-area portion 52 of the present embodiment are both located in the opening area, so that the corresponding areas of the two data line sub-area portions can be combined into the opening area, the area occupation ratio of the opening area of the first sub-pixel area 12 is enlarged, the opening ratio of the first sub-pixel area 12 is improved, and the light transmittance is increased.
In one embodiment, the first data line main area portion 41 is located in the opening area of the first main pixel area 11. In this way, the area corresponding to the first data line main area portion 41 can be integrated into the opening area of the first main pixel area 11, the opening area ratio of the first main pixel area 11 can be enlarged, and the opening ratio of the first main pixel area 11 can be improved.
In one embodiment, the second data line main area portion 51 is located in the opening area of the second main pixel area 21. In this way, the area corresponding to the second data line main area portion 51 can be incorporated into the opening area of the second main pixel area 21, the opening area ratio of the second main pixel area 21 can be enlarged, and the opening ratio of the second main pixel area 21 can be improved.
In one embodiment, the short circuit detection module further includes a metal layer where the first data line sub-area portion 42 and the second data line sub-area portion 52 are located, and is electrically connected to the short circuit detection module. The first data line sub-area portion 42 and the second data line sub-area portion 52 are located on the first sub-pixel area 12 at the same time, and the first data line sub-area portion 42 is separated from the second data line sub-area portion 52 by a relatively short distance, so that there is a possibility that the metal layers where the first data line sub-area portion 42 and the second data line sub-area portion 52 are located are in contact to cause a short circuit. According to the embodiment, the short circuit detection module can be arranged in the frame area of the display panel so as to monitor the short circuit condition of the metal layer, and when the short circuit occurs, the short circuit detection module can be used for timely processing.
In one embodiment, the length of the first data line sub-section 42 is greater than the length of the first data line main section 41. Correspondingly, the area of the first sub-pixel region 12 is larger than the area of the first main pixel region 11. Therefore, the duty ratio of the first data line sub-area part 42 in the first data line 4 can be improved, the wiring length of the first data line sub-area part 42 is longer, and the effect of counteracting the coupling effect is better.
In one embodiment, the length of the second data line secondary section 52 is greater than the length of the second data line primary section 51. Correspondingly, the area of the second sub-pixel area 22 is larger than the area of the second main pixel area 21. This can increase the duty ratio of the second data line sub-area portion 52 in the second data line 5, so that the trace length of the second data line sub-area portion 52 is longer and the effect of counteracting the coupling effect is better.
In an embodiment the pixel structure further comprises a second shared discharge rod 7, the second shared discharge rod 7 being located on the second pixel 2. The second shared discharging rod 7 is used for adjusting the voltage difference between the second sub-pixel area 22 and the second main pixel area 21 to adjust the overall brightness of the second pixel 2. In a preferred embodiment, the second shared discharging rod 7 may be located on the center line or the symmetry axis of the second pixel 2, so that the layout of the pixel structure may be more regular.
The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (9)
1. A pixel structure, comprising:
a first pixel including a first main pixel region and a first sub pixel region;
the second pixel is arranged adjacent to the first pixel and comprises a second main pixel area and a second sub pixel area;
the scanning line is positioned between the first main pixel area and the first sub pixel area and is simultaneously positioned between the second main pixel area and the second sub pixel area;
the first data line comprises a first data line main area part and a first data line sub-area part, the first data line main area part is positioned on the first main pixel area, and the first data line sub-area part is positioned on the first sub-pixel area;
a second data line including a second data line main region portion and a second data line sub-region portion, the second data line main region portion being located on the second main pixel region, the second data line sub-region portion being located on the first sub-pixel region;
the first shared discharging rod is positioned on the first pixel, and the first data line sub-area part and the second data line sub-area part are symmetrical relative to the first shared discharging rod;
the signal electrical property of the first data line is opposite to the signal electrical property of the second data line.
2. The pixel structure of claim 1, wherein the first data line sub-region portion and the second data line sub-region portion are both located on an opening region of the first sub-pixel region.
3. The pixel structure of claim 1, wherein the first data line main region portion is located on an opening region of the first main pixel region.
4. The pixel structure of claim 1, wherein the second data line main region portion is located on an opening region of the second main pixel region.
5. The pixel structure of claim 1, further comprising a short circuit detection module, wherein the metal layer where the first data line sub-area portion and the second data line sub-area portion are located is electrically connected to the short circuit detection module.
6. The pixel structure of claim 1, wherein the length of the first data line sub-region portion is greater than the length of the first data line main region portion.
7. The pixel structure of claim 1, wherein the length of the second data line secondary section is greater than the length of the second data line primary section.
8. The pixel structure of claim 1, further comprising a second shared discharge bar, the second shared discharge bar being located on the second pixel.
9. A display panel comprising a substrate and the pixel structure of any one of claims 1 to 8, the pixel structure being provided on the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210146175.8A CN114387936B (en) | 2022-02-17 | 2022-02-17 | Pixel structure and display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210146175.8A CN114387936B (en) | 2022-02-17 | 2022-02-17 | Pixel structure and display panel |
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| CN114387936A CN114387936A (en) | 2022-04-22 |
| CN114387936B true CN114387936B (en) | 2023-05-02 |
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