CN114384969B - High-speed true random number generation system - Google Patents
High-speed true random number generation system Download PDFInfo
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- CN114384969B CN114384969B CN202111630135.2A CN202111630135A CN114384969B CN 114384969 B CN114384969 B CN 114384969B CN 202111630135 A CN202111630135 A CN 202111630135A CN 114384969 B CN114384969 B CN 114384969B
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- 238000005070 sampling Methods 0.000 claims description 4
- 230000010355 oscillation Effects 0.000 claims description 3
- 238000004364 calculation method Methods 0.000 claims description 2
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- 238000004891 communication Methods 0.000 description 3
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
Abstract
The invention discloses a high-speed true random number generation system, which comprises a true random number generation module and a processor; the true random number generation module is configured to generate N paths of true random number sequences; the processor is configured to control a rate of the N-way true random number module sequence; the process of the processor controlling the sequence rate of the plurality of sets of true random number modules is as follows: the processor outputs an I/O port, the enabling pin of the physical noise chip is controlled by outputting high and low levels, the random number output is controlled by chip selection, so that the true random number module sequence reaches the true random number sequence rate required by the system, the true random number sequence is shifted, and the high-rate random bit stream is serially output. The invention generates the true random number sequence through the true random number generation module, controls the speed of the true random number sequence through the FPGA processor to enable the true random number sequence to serially output high-speed random bit stream, improves the safety of the secret key in the transmission process, and simultaneously improves the distribution speed of the secret key of the QKD system.
Description
Technical Field
The invention relates to the field of quantum random numbers, in particular to a high-speed true random number generation system.
Background
True random number generators are widely used in various fields of today's information flow society, especially where privacy is important. True random number generators are not only an important component of modern communications, but also the generation of random numbers is a building security foundation.
In modern communications, people encrypt, decrypt, authenticate, etc. information primarily through random numbers. The upper limit of the rate of the random numbers generated by the true random number generator depends on the characteristic decision of the entropy source, and although in recent years, the random number generating chip achieves a certain achievement, the rate has not yet reached the needs of the random system. The random number is mainly generated by a true random number generator and a pseudo random number generator. The former is to generate a true random number through a physical chip, which has unpredictable and independent property and achieves true random, but the main problem is that the rate of random sequence generation cannot meet the requirements of modern communication. The latter is by means of encryption algorithms such as: symmetric encryption, asymmetric encryption, hash algorithm, etc., and realizing 'true random' through software operation. However, since the algorithm and the seed are fixed and are regularly circulated, the random number is predictable and reproducible, and is called a pseudo random number, and a high-performance encryption system cannot be satisfied. Such as: a quantum key distribution system. Therefore, there is a need to improve the prior art to provide random numbers with better accuracy.
The existing random number generator is mainly realized by a method of generating a pseudo random number through an algorithm, and has the defect that once the algorithm is deciphered, the algorithm is not random. Another method is that the noise source random number generates true random, and the disadvantage is that the speed is too low to meet the encryption service requirement of the system.
Therefore, the existing random number generator needs to be further improved, and the scheme of the system is used for generating the high-speed high-quality random number generator, so that the circuit is simple and reliable, easy to realize and low in cost, and can be embedded into other application occasions.
Disclosure of Invention
In order to solve the technical problems, an embeddable random number system with better precision and ensured system safety is provided.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows: the high-speed true random number generation system is characterized by comprising a true random number generation module and a processor;
the true random number generation module is configured to generate N paths of parallel true random number sequences;
the processor is configured to control the rate at which the N-way parallel true random number sequences are generated;
the process of the processor controlling the rate of generating the N paths of parallel true random number sequences is as follows:
step 1: the processor outputs high and low level control physical noise chip enable pins through an output I/O port, and controls random number output through chip selection;
step 2: the processor controls the N paths of parallel true random number sequences to reach the rate of the true random number sequences, then shifts the N paths of parallel true random number sequences, and serially outputs high-rate random bit streams;
the high rate refers to a random data stream with the rate of more than 50 MHz;
the calculation formula of the shift frequency F of the N-path parallel true random number sequence shift processing by the processor is as follows:
f=f×x, where F is the transmission rate of the random sequence and X is the shift bit width.
Preferably, the true random number generation module includes a physical noise chip for generating a sequence of true random number modules.
Preferably, the physical noise chip is a digital physical noise source chip, and the digital physical noise source chip is provided with N groups, namely a first noise source chip, a second noise source chip, a third noise source chip and a … … Nth noise source chip.
Preferably, the N digital physical noise source chips convert randomly generated dither noise into random numbers by an internal oscillation sampling method, and multiple groups of random numbers form a random number sequence.
Preferably, the processor is an FPGA processor.
Preferably, the digital physical noise source chip outputs signals to the FPGA processor, internal delay is performed on the output signals through the FPGA processor, and delay generated in circuit transmission of data and clock data is eliminated.
Preferably, the delay value and the delay amount are determined according to an input data period T;
the T is divided into 64 taps, the delay step length of each tap is T/64, and the maximum delay step length is 32 taps.
Preferably, the processor includes a shift trigger clock that outputs the high frequency clock signal through the PLL frequency doubling circuit by an internal or external clock generating circuit.
Preferably, the shift trigger clock uses the generated high-frequency clock signal to sample and shift the N-path parallel true random number sequences, and outputs serial random sequences from the multi-path low-speed parallel random sequences through shift.
Preferably, the shift process is performed by a shift register with a shift number of X bits.
The beneficial technical effects of the invention are as follows: the invention generates the true random number sequence through the true random number generation module, controls the speed of the true random number sequence through the FPGA processor to enable the true random number sequence to serially output high-speed random bit stream, improves the safety of the secret key in the transmission process, and simultaneously improves the distribution speed of the secret key of the QKD system.
Drawings
FIG. 1 is a block diagram of the overall structure of the present invention;
fig. 2 is a block diagram of the overall structure of the trigger signal synchronizing circuit according to the present invention.
Detailed Description
The present invention will be further described in detail with reference to the following examples, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent, but the scope of the present invention is not limited to the following specific examples.
1-2, a high-speed true random number generation system comprises a true random number generation module and a processor, wherein the processor adopts an FPGA processor;
the true random number generation module is configured to generate N paths of parallel true random number sequences;
the FPGA processor is configured to control the rate of generating the N paths of parallel true random number sequences;
the FPGA processor controls the process of generating the N paths of parallel true random number sequence rate as follows:
the FPGA processor outputs an I/O port, controls the output of the random number through the chip selection by outputting the enable pin of the high-low level control physical noise chip, enables the true random number sequence to reach the true random number sequence rate required by the system, shifts the true random number sequence and serially outputs a high-rate random bit stream.
The true random number generation module comprises a WNG series physical noise chip, and the true random number generation module generates a true random number module sequence through the physical noise chip.
Specifically, the physical noise chip adopts a digital physical noise source chip, the digital physical noise source chip has N pieces, namely a first noise source chip #1, a second noise source chip #2, a third noise source chip #3, a … …, an N-th noise source chip #N and the like, and the N pieces of digital physical noise source chips generate physical noise and output N paths of parallel true random number sequences.
Specifically, the output N paths of parallel true random number sequences are that the physical noise chip converts the generated dithering noise into random numbers by adopting an oscillation sampling method, the dithering noise is random in the process, namely the generated random sequences also meet the random characteristic, and the random sequences meet the true random characteristic, but the rate of the random numbers is not high at the moment, so that the FPGA processor is required to process the random numbers at an increased rate.
The main control chip of the FPGA processor adopts Intel EP4CGX series chips, and the main control chip processes the random sequence output by each path so as to improve the speed of the random number.
The processing process and method of the FPGA processor are as follows: n digital physical noise source chips output random number signals to the FPGA processor, and the processor is used for controlling the delay of Idelay in the chip, eliminating the delay generated by data and clock data in circuit transmission and ensuring the strict synchronization of the data.
The Idelay delay processing can be realized through manual debugging setting or through an automatic algorithm, and the delay value and the delay amount are determined according to the input data period T. And dividing T into 64 taps, wherein the delay step length of each tap is T/64, the maximum delay step length is 32 taps, and the delay amount is set according to the transmission performance of the circuit, so that the synchronization effect is achieved. And meanwhile, sampling and shifting N paths of low-input random numbers by using an internal high-speed clock and an N-bit shift register, and finally outputting a serial random sequence (the shifting is to output a serial random sequence by shifting a plurality of paths of low-speed parallel random sequences).
The shift rate is determined based on an internally configured clock trigger signal. The frequency configuration requirement meets the following conditions: f=f×x. Where f is the transmission rate of the random sequence and X is the shift bit width. The shift trigger clock can output a high-frequency clock signal through an internal or external clock generating circuit and a PLL frequency doubling circuit. The random number rate generated after the shift processing reaches the level of the high-frequency clock signal rate, so that the high-speed random number bit stream is output in series, and the practical problem of low true random number rate is solved.
Variations and modifications to the above would be obvious to persons skilled in the art to which the invention pertains from the foregoing description and teachings. Therefore, the invention is not limited to the specific embodiments disclosed and described above, but some modifications and changes of the invention should be also included in the scope of the claims of the invention. In addition, although specific terms are used in the present specification, these terms are for convenience of description only and do not constitute any limitation on the invention.
Claims (10)
1. The high-speed true random number generation system is characterized by comprising a true random number generation module and a processor;
the true random number generation module is configured to generate N paths of parallel true random number sequences;
the processor is configured to control the rate at which the N-way parallel true random number sequences are generated;
the process of the processor controlling the rate of generating the N paths of parallel true random number sequences is as follows:
step 1: the processor outputs high and low level control physical noise chip enable pins through an output I/O port, and controls random number output through chip selection;
step 2: the processor controls the N paths of parallel true random number sequences to reach the rate of the true random number sequences, then shifts the N paths of parallel true random number sequences, and serially outputs high-rate random bit streams;
the high rate refers to a random data stream with the rate of more than 50 MHz;
the calculation formula of the shift frequency F of the N-path parallel true random number sequence shift processing by the processor is as follows:
f=f×x, where F is the transmission rate of the random sequence and X is the shift bit width.
2. The high-speed true random number generating system of claim 1 wherein said true random number generating module comprises a physical noise chip for generating a sequence of true random number modules.
3. The system of claim 2, wherein the physical noise chip is a digital physical noise source chip, and the digital physical noise source chip is provided with N groups of noise source chips, which are a first noise source chip, a second noise source chip, a third noise source chip, and a … … nth noise source chip, respectively.
4. A high-speed true random number generating system as recited in claim 3 wherein N sets of said digital physical noise source chips convert randomly generated dither noise into random numbers by means of internal oscillation sampling, the sets of random numbers forming a random number sequence.
5. A high-speed true random number generating system according to claim 3, wherein said processor is an FPGA processor.
6. The system of claim 5, wherein the digital physical noise source chip outputs signals to the FPGA processor, and the FPGA processor delays the output signals internally to eliminate delays in the circuit transmission of the data and clock data.
7. The system for generating high-speed true random numbers according to claim 6, wherein a delay value and a delay amount of the internal delay are determined according to an input data period T;
the period T is divided into 64 taps, the delay step length of each tap is T/64, and the maximum delay step length is 32 taps.
8. The system of claim 7, wherein the processor includes a shift trigger clock, the shift trigger clock outputting the high frequency clock signal via the PLL frequency multiplier circuit through an internal or external clock generating circuit.
9. The system for generating high-speed true random numbers according to claim 8, wherein the shift trigger clock uses the generated high-frequency clock signal to sample and shift the N parallel true random number sequences, and outputs the serial random sequences from the multiple low-speed parallel random sequences through shifting.
10. The system of claim 8, wherein the shift process is performed by a shift register with X bits.
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| KR19990076323A (en) * | 1998-03-31 | 1999-10-15 | 윤종용 | Boundary scan standard interface circuit for microprocessor emulation mode |
| CN103019648A (en) * | 2012-11-27 | 2013-04-03 | 天津大学 | True random number generator with digital post-processing circuit |
| CN103188075A (en) * | 2013-02-01 | 2013-07-03 | 广州大学 | Secret key and true random number generator and method for generating secret key and true random number |
| CN104516715A (en) * | 2014-12-29 | 2015-04-15 | 太原理工大学 | Tbps all-optical parallel true random number generator with extra-strong scalability |
| CN105955707A (en) * | 2016-04-27 | 2016-09-21 | 太原理工大学 | Oversampling high-speed real-time optical true random number generator |
| CN107608657A (en) * | 2017-08-17 | 2018-01-19 | 华南师范大学 | It is a kind of based on when width conversion adjustable true random number generation system |
| CN109271136A (en) * | 2018-08-06 | 2019-01-25 | 上海交通大学 | Real random number generator and method for generation based on FPGA |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10708043B2 (en) * | 2013-03-07 | 2020-07-07 | David Mayer Hutchinson | One pad communications |
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- 2021-12-28 CN CN202111630135.2A patent/CN114384969B/en active Active
Patent Citations (8)
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|---|---|---|---|---|
| JPH0736673A (en) * | 1993-07-20 | 1995-02-07 | Canon Inc | Random-number generator, communication system using the same and device therefor |
| KR19990076323A (en) * | 1998-03-31 | 1999-10-15 | 윤종용 | Boundary scan standard interface circuit for microprocessor emulation mode |
| CN103019648A (en) * | 2012-11-27 | 2013-04-03 | 天津大学 | True random number generator with digital post-processing circuit |
| CN103188075A (en) * | 2013-02-01 | 2013-07-03 | 广州大学 | Secret key and true random number generator and method for generating secret key and true random number |
| CN104516715A (en) * | 2014-12-29 | 2015-04-15 | 太原理工大学 | Tbps all-optical parallel true random number generator with extra-strong scalability |
| CN105955707A (en) * | 2016-04-27 | 2016-09-21 | 太原理工大学 | Oversampling high-speed real-time optical true random number generator |
| CN107608657A (en) * | 2017-08-17 | 2018-01-19 | 华南师范大学 | It is a kind of based on when width conversion adjustable true random number generation system |
| CN109271136A (en) * | 2018-08-06 | 2019-01-25 | 上海交通大学 | Real random number generator and method for generation based on FPGA |
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