CN114373803B - Semiconductor element and preparation method thereof - Google Patents
Semiconductor element and preparation method thereof Download PDFInfo
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- CN114373803B CN114373803B CN202210013765.3A CN202210013765A CN114373803B CN 114373803 B CN114373803 B CN 114373803B CN 202210013765 A CN202210013765 A CN 202210013765A CN 114373803 B CN114373803 B CN 114373803B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 200
- 239000000758 substrate Substances 0.000 claims abstract description 113
- 210000000746 body region Anatomy 0.000 claims abstract description 56
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- 229910052751 metal Inorganic materials 0.000 claims description 24
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- 150000002500 ions Chemical class 0.000 claims description 15
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
Abstract
The invention discloses a semiconductor element and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate, and forming an epitaxial layer on the substrate; one side of the epitaxial layer far away from the substrate comprises a groove; forming a first insulating layer on the side wall and the bottom of the groove, and forming a first polycrystalline silicon layer and a second polycrystalline silicon layer in a space surrounded by the first insulating layer; the second polycrystalline silicon layer is used as grid polycrystalline silicon, and the first insulating layer between the second polycrystalline silicon layer and the groove is used as a grid insulating layer; forming a body region and a source region in the epitaxial layer; forming a compensation charge area in the first insulating layer at the bottom of the groove; the electric field generated by the charges in the compensation charge area is used for weakening the electric field intensity of the position with weaker voltage resistance in the epitaxial layer so as to improve the voltage resistance value of the semiconductor element to the target voltage resistance value. The technical scheme provided by the embodiment of the invention effectively improves the voltage resistance of the device, does not need to accurately control different thicknesses of the first insulating layer at different depths of the groove, and simplifies the mode of improving the voltage resistance of the device.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a semiconductor element and a preparation method thereof.
Background
Deep trench MOSFETs have a better figure of merit (FOM) than conventional Metal-Oxide-Semiconductor Field-Effect transistors (MOSFETs). The split-gate MOSFET adopts a coupling balance design, so that low on-resistance and low reverse transmission capacitance can be realized simultaneously, the conduction loss and the switching loss of a system are reduced, and the service efficiency of an electronic product is improved.
The split gate type MOSFET has the problem of poor voltage resistance of a device, the current scheme couples an electric field provided by a double-gate structure and charges in an epitaxial layer to realize higher voltage resistance, but in the method, because the processing difficulty of the double-gate structure is higher, a groove needs to be dug in the epitaxial layer, then an oxide layer and a polycrystalline silicon double-gate structure are formed in the groove, the thickness of the oxide layer between the double-gate structure and the epitaxial layer is uniform, different thicknesses are difficult to accurately control at different depths of the groove, the problem of poor voltage resistance of the device is improved, and the problem of poor voltage resistance of the device cannot be well improved.
Disclosure of Invention
The embodiment of the invention provides a semiconductor element and a preparation method thereof, which aim to effectively improve the voltage resistance of a device.
In a first aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:
providing a substrate, and forming an epitaxial layer on the substrate; one side of the epitaxial layer, which is far away from the substrate, comprises a groove;
forming a first insulating layer on the side wall and the bottom of the groove, and forming a first polycrystalline silicon layer and a second polycrystalline silicon layer in a space surrounded by the first insulating layer; the second polycrystalline silicon layer is used as grid polycrystalline silicon, and the first insulating layer between the second polycrystalline silicon layer and the groove is used as a grid insulating layer; the first polycrystalline silicon layer is used as source polycrystalline silicon, and a first insulating layer between the first polycrystalline silicon layer and the groove is used as a shielding gate insulating layer;
forming a body region and a source region in the epitaxial layer; the body region and the source region are positioned on the left side and the right side of the second polycrystalline silicon layer; the body region is positioned on one side close to the substrate relative to the source region;
forming a compensation charge area in the first insulating layer at the bottom of the groove; the electric field generated by the charges in the compensation charge area is used for weakening the electric field intensity of the position with weaker voltage resistance in the epitaxial layer so as to improve the voltage resistance value of the semiconductor element to a target voltage resistance value.
Optionally, the forming a compensation charge region in the first insulating layer at the bottom of the trench includes:
inputting a voltage larger than the initial withstand voltage value of the semiconductor element between the source region and the drain region, and forming a compensation charge region in the insulating layer at the bottom of the trench through the generated avalanche current; wherein the drain region is a heavily doped substrate.
Optionally, forming a first insulating layer on the sidewall and the bottom of the trench, and forming a first polysilicon layer and a second polysilicon layer in a space surrounded by the first insulating layer includes:
forming a second insulating layer on the side wall of the groove, the bottom of the groove and the surface of one side of the epitaxial layer far away from the substrate;
depositing a first polysilicon layer in the groove by a chemical vapor deposition method;
etching the first polysilicon layer by dry etching, so that the height of the etched first polysilicon layer in the groove is smaller than the depth of the groove;
removing the second insulating layer which is positioned on one side of the epitaxial layer far away from the substrate and positioned in the groove and not covered by the first polycrystalline silicon layer through wet etching;
forming a third insulating layer on one side of the first polycrystalline silicon layer far away from the substrate and the side wall which is not covered by the first polycrystalline silicon layer in the groove;
depositing the second polysilicon layer in the trench by chemical vapor deposition; and a third insulating layer on one side of the first polycrystalline silicon layer, which is far away from the substrate, is used as the intermediate insulating layer, and a second insulating layer between the first polycrystalline silicon layer and the groove and a third insulating layer between the second polycrystalline silicon layer and the groove are used as the first insulating layer.
Optionally, the first insulating layer is further formed on a side of the epitaxial layer away from the substrate;
when a third insulating layer is formed on one side of the first polycrystalline silicon layer, which is far away from the substrate, and on the side wall, which is not covered by the first polycrystalline silicon layer, in the groove, the third insulating layer is also formed on one side of the epitaxial layer, which is far away from the substrate; and the third insulating layer at one side of the epitaxial layer, which is far away from the substrate, is used as the first insulating layer at one side of the epitaxial layer, which is far away from the substrate.
Optionally, the forming a body region and a source region in the epitaxial layer includes:
forming the body region and the source region in the epitaxial layer by means of ion implantation;
wherein the ions implanted into the source region are the same as the ion type doped in the epitaxial layer.
Optionally, the source region and the epitaxial layer are both doped in an N-type manner, and the body region is doped in a P-type manner; or, the source region and the epitaxial layer are both doped in a P type, and the body region is doped in an N type.
Optionally, after forming the body region and the source region in the epitaxial layer, the method further includes:
forming a passivation layer and a metal layer on one side of the epitaxial layer far away from the substrate and one side of the second polycrystalline silicon layer far away from the substrate; the metal layer contacts the body and source regions through the passivation layer and the first opening of the body region and contacts the second polysilicon layer through the second opening of the passivation layer.
Optionally, forming a passivation layer and a metal layer on the side of the epitaxial layer away from the substrate and the side of the second polysilicon layer away from the substrate includes:
forming the passivation layer on one side of the epitaxial layer far away from the substrate and one side of the second polycrystalline silicon layer far away from the substrate;
etching the passivation layer and the source region of the epitaxial layer to form the first opening and the second opening, wherein the first opening exposes part of the body region; the second opening exposes a part of the second polysilicon layer;
forming a metal layer on one side of the passivation layer away from the substrate, wherein the metal layer is in contact with the source region and the body region through the first opening; through the second opening, in contact with the second polysilicon layer.
Optionally, the metal layer in contact with the source region serves as a source electrode led out; the metal layer in contact with the second polycrystalline silicon layer is used as a gate electrode led out;
and forming an externally-led drain electrode on one side of the substrate far away from the epitaxial layer.
In a second aspect, an embodiment of the present invention provides a semiconductor element formed by the method for manufacturing a semiconductor according to any one of the first aspects, including:
a substrate;
the epitaxial layer is positioned on one side of the substrate; one side of the epitaxial layer, which is far away from the substrate, comprises a groove;
the first insulating layer is positioned on the side wall and the bottom of the groove;
a first polysilicon layer and a second polysilicon layer located in a space surrounded by the first insulating layer; the second polycrystalline silicon layer is used as grid polycrystalline silicon, and the first insulating layer between the second polycrystalline silicon layer and the groove is used as a grid insulating layer; the first polycrystalline silicon layer is used as source polycrystalline silicon, and a first insulating layer between the first polycrystalline silicon layer and the groove is used as a shielding gate insulating layer;
a body region and a source region; the body region and the source region are formed in the epitaxial layer; the body region and the source region are positioned at the left side and the right side of the second polycrystalline silicon layer, and relative to the source region, the body region is positioned at one side close to the substrate;
the compensation charge area is positioned in the first insulating layer at the bottom of the groove; the electric field generated by the charges in the compensation charge area is used for weakening the electric field intensity of the position with weaker voltage resistance in the epitaxial layer so as to improve the voltage resistance value of the semiconductor element to a target voltage resistance value.
The embodiment of the invention provides a semiconductor element and a preparation method thereof, wherein the preparation method of the semiconductor element comprises the following steps: providing a substrate, and forming an epitaxial layer on the substrate; one side of the epitaxial layer, which is far away from the substrate, comprises a groove; forming a first insulating layer on the side wall and the bottom of the groove, and forming a first polycrystalline silicon layer and a second polycrystalline silicon layer in a space surrounded by the first insulating layer; the second polycrystalline silicon layer is used as grid polycrystalline silicon, and a first insulating layer between the second polycrystalline silicon layer and the groove is used as a grid insulating layer; the first polycrystalline silicon layer is used as source polycrystalline silicon, and a first insulating layer between the first polycrystalline silicon layer and the groove is used as a shielding gate insulating layer; forming a body region and a source region in the epitaxial layer; the body region and the source region are positioned on the left side and the right side of the second polycrystalline silicon layer; the body region is positioned at one side close to the substrate relative to the source region; forming a compensation charge area in the first insulating layer at the bottom of the groove; the electric field generated by the charges in the compensation charge area is used for weakening the electric field intensity of the position with weaker voltage resistance in the epitaxial layer so as to improve the voltage resistance value of the semiconductor element to the target voltage resistance value. According to the technical scheme provided by the embodiment of the invention, the compensation charge area is formed in the insulating layer at the bottom of the groove, and an electric field generated by charges in the compensation charge area is used for weakening the electric field strength of a position with weaker withstand voltage in the epitaxial layer, so that the withstand voltage value of the semiconductor element is increased to a target withstand voltage value, and different thicknesses of the first insulating layer are not required to be accurately controlled at different depths of the groove.
Drawings
Fig. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2 is a cross-sectional view of a structure corresponding to step S110 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3 is a cross-sectional view of a structure corresponding to step S120 in a method for manufacturing a semiconductor device according to an embodiment of the invention;
fig. 4 is a cross-sectional view of a structure corresponding to step S130 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 5 is a cross-sectional view of a structure corresponding to step S140 in a method for manufacturing a semiconductor device according to an embodiment of the invention;
fig. 6 is a cross-sectional view of another semiconductor device manufacturing method according to another embodiment of the present invention, wherein the cross-sectional view corresponds to step S140;
fig. 7 is a cross-sectional view of another semiconductor device manufacturing method according to another embodiment of the present invention, wherein the cross-sectional view corresponds to step S140;
FIG. 8 is a flow chart of another method for fabricating a semiconductor device according to an embodiment of the present invention;
fig. 9 is a cross-sectional view of a structure corresponding to step S220 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 10-11 are cross-sectional views of structures corresponding to step S230 in a method for fabricating a semiconductor device according to an embodiment of the present invention;
fig. 12-13 are cross-sectional views of structures corresponding to step S240 in a method for fabricating a semiconductor device according to an embodiment of the invention;
fig. 14 is a cross-sectional view of a structure corresponding to step S250 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 15 is a cross-sectional view of a structure corresponding to step S270 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 16 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 17 is a cross-sectional view of a structure corresponding to step S340 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 18 is a cross-sectional view of a structure corresponding to step S350 in a method for manufacturing a semiconductor device according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, fig. 1 is a flowchart of the method for manufacturing the semiconductor device according to the embodiment of the present invention, and referring to fig. 1, the method for manufacturing the semiconductor device includes:
s110, providing a substrate, and forming an epitaxial layer on the substrate; the side of the epitaxial layer remote from the substrate comprises a trench.
Specifically, fig. 2 is a structural cross-sectional view corresponding to step S110 in the method for manufacturing a semiconductor element according to the embodiment of the present invention, and referring to fig. 2, a material of the substrate 20 may include silicon, an epitaxial layer 30 is grown on a surface of the substrate 20 using a silicon material, a thickness of the epitaxial layer 30 is determined according to a source-drain withstand voltage required by a device, and a range of the epitaxial layer 30 may be from 5 micrometers to 20 micrometers; the epitaxial layer 30 includes an N-type epitaxial layer or a P-type epitaxial layer. The epitaxial layer 30 is formed with a plurality of trenches 40 on a side thereof away from the substrate 20. The trench reticle may be used for a photolithography process, requiring exposure at the trench 40 locations without photoresist masking, with the remainder masked with photoresist. And etching the position without the photoresist masking to form a deep groove 40 by dry etching, and removing the photoresist.
S120, forming a first insulating layer on the side wall and the bottom of the groove, and forming a first polycrystalline silicon layer and a second polycrystalline silicon layer in a space surrounded by the first insulating layer; the second polycrystalline silicon layer is used as grid polycrystalline silicon, and the first insulating layer between the second polycrystalline silicon layer and the groove is used as a grid insulating layer; the first polycrystalline silicon layer is used as source polycrystalline silicon, and the first insulating layer between the first polycrystalline silicon layer and the groove is used as a shielding gate insulating layer.
Specifically, fig. 3 is a cross-sectional view of a structure corresponding to step S120 in the method for manufacturing a semiconductor device according to an embodiment of the present invention, and referring to fig. 3, a material of the first insulating layer 50 includes silicon oxide, which may be formed on the sidewall and the bottom of the trench 40 by a wet oxygen oxidation growth method, or may be formed on the sidewall of the trench 40 and the bottom of the trench 40 by a chemical vapor deposition method. Wherein the silicon oxide formed on the sidewall and bottom of the trench 40 by wet oxygen oxidation growth has better compactness. The higher the density of the silicon oxide, the better the isolation of the polysilicon material in the trench 40 from the epitaxial layer 30 forming the trench 40, and the better the operating performance of the fabricated semiconductor device. However, the higher the density of the silicon oxide, the greater the stress between the insulating layer and the film layer, and thus the first insulating layer 50 may be formed by a combination of a chemical vapor deposition method and a wet oxygen oxidation growth method. The material of the intermediate insulating layer 70 also includes silicon oxide, and may be formed in the manner described above, and will not be described herein.
Two polysilicon portions are also provided within the trench 40 structure: the second polysilicon layer 80 located in the upper half is the control gate (gate polysilicon) and the first polysilicon layer 60 located in the lower half is the shield gate (source polysilicon). The first insulating layer 50 between the second polysilicon layer 80 and the trench 40 serves as a gate insulating layer 510. The first insulating layer 50 located between the first polysilicon layer 60 and the trench 40 serves as a shield gate insulating layer 520. The first and second polysilicon layers 60 and 80 may be formed by a chemical vapor deposition method. It should be noted that fig. 3 schematically shows a cross-sectional structure of the first polysilicon 60 and the second polysilicon 80 after forming the first polysilicon 60 and the second polysilicon 80, wherein the first polysilicon 60 and the second polysilicon 80 are in an upper-lower structure and the deep trench of the inter-block insulating layer 70 between the first polysilicon 60 and the second polysilicon 80 is electrically coupled with a balanced mosfet. The embodiment of the present invention may also include a deep trench electrically coupled balanced type mosfet with other structures, for example, a mosfet with an upper and lower structure without the intermediate insulating layer 70; or a deep trench MOSFET of a left-right configuration in which the gate polysilicon (80) is disposed around the source polysilicon (60).
S130, forming a body region and a source region in the epitaxial layer; wherein, the body region and the source region are both located at the left and right sides of the second polysilicon layer 80; the body region is located on a side close to the substrate opposite the source region.
Specifically, fig. 4 is a cross-sectional view of a structure corresponding to step S130 in the method for manufacturing a semiconductor device according to the embodiment of the present invention, and referring to fig. 4, taking the first polysilicon 60 and the second polysilicon 80 as an upper-lower structure, and taking the deep trench electrically coupled balanced type mosfet between the first polysilicon 60 and the second polysilicon 80, which includes the inter-layer insulating layer 70, as an example, the body region 90 and the source region 110 may be formed in the epitaxial layer 30 by ion implantation. The ion is enabled to have certain kinetic energy through the cyclotron, and the kinetic energy of the ion is positively correlated with the injection depth of the ion. Wherein the ions implanted in the body region 90 are of the opposite type to the ions doped in the epitaxial layer 30, and the ions implanted in the source region 110 are of the same type as the ions doped in the epitaxial layer 30. For example, the doping ions of epitaxial layer 30 are pentavalent elements (phosphorus or arsenic), N-type epitaxial layer 30 can be formed, the implanted ions in body region 90 are trivalent elements (boron or boron fluoride), and the implanted ions in source region 110 are of the same type as the doping ions in epitaxial layer 30, and can also be pentavalent phosphorus or arsenic.
The substrate 20 is heavily doped to serve as a drain region, for example, N-type doping, and the epitaxial layer 30 on the upper surface of the substrate 20 is an N-type semiconductor drift region. In the trench 40, the shield gate is located below the control gate, and when the device is turned on, the drain current flows along the longitudinal sidewall of the trench 40, forming an inversion layer channel on the surface of the body region 90. When the source is forward biased, electrons travel along the inversion layer channel from the source region 110 to the drain region 10. Electrons from the source region 110 pass through the channel and enter the drift region at the bottom of the trench gate, and the current spreads out over the entire cell cross-sectional width.
S140, forming a compensation charge area in the first insulating layer at the bottom of the groove; the electric field generated by the charges in the compensation charge area is used for weakening the electric field intensity of the position with weaker voltage resistance in the epitaxial layer so as to improve the voltage resistance value of the semiconductor element to the target voltage resistance value.
Specifically, the semiconductor devices (MOSFETs) having different specifications of voltage resistance include, for example, a device having a 60V voltage resistance value, a device having an 80V voltage resistance value, a device having a 100V voltage resistance value, a device having a 120V voltage resistance value, a device having a 150V voltage resistance value, a device having a 200V voltage resistance value, and the like. For a device with a withstand voltage of 100V which cannot be installed in a circuit with a withstand voltage of 120V, a device with a withstand voltage of 100V may be turned on by applying a voltage of 120V to the device with a withstand voltage of 100V, and the effect of a MOSFET as a switch-off circuit is not obtained. The higher the voltage resistance of the device, the wider the voltage range of the applicable circuit of the device. In addition, when the device is used as a switch to turn on a circuit, the resistance of the device affects the energy loss of the circuit. The greater the resistance of the device, the greater the thermal energy it generates and the greater the energy it loses. The higher the voltage resistance of a MOSFET, the higher the energy consumed at turn-on, i.e., the higher its resistance at turn-on. For example, the resistance of a device with a withstand voltage of 100V when it is turned on is R1, the resistance of a device with a withstand voltage of 120V when it is turned on is R2, and R2 is larger than R1.
Fig. 5 is a cross-sectional view of a structure corresponding to step S150 in the method for manufacturing a semiconductor device according to the embodiment of the invention, referring to fig. 5, taking a deep trench electrically coupled balanced MOSTET in which the first polysilicon 60 and the second polysilicon 80 are in an upper-lower structure and the middle insulating layer 70 is enclosed between the first polysilicon 60 and the second polysilicon 80 as an example, a compensation charge region 2 is formed in the first insulating layer 50 at the bottom of the trench 40, and an electric field generated by charges in the compensation charge region 2 weakens an electric field strength at a position with weak voltage resistance in the epitaxial layer 30, thereby improving a voltage resistance of the semiconductor device. Wherein the target voltage resistance value is a voltage value which can be borne after the voltage resistance is improved. Wherein the charge compensation region 2 can be formed by partial chemical bond breaking in the insulating layer at the bottom of the trench 40, and the chemical bond breaking generates corresponding positive and negative charges to compensate the charges required for the avalanche voltage increase. The voltage resistance of the MOSFET can be improved under the condition of not changing the physical structure of the MOSFET and ensuring that the resistance of the MOSFET is not changed. Namely, the voltage resistance of the MOSFET is improved, and the increase of the loss of the MOSFET during conduction is avoided. As described above, the embodiments of the present invention may further include other deep trench electrically coupled balanced mosfets. Fig. 6 is a cross-sectional view of another semiconductor device manufacturing method according to another embodiment of the present invention, wherein the cross-sectional view corresponds to step S150, and referring to fig. 6, the structure is a deep trench mosfet having an upper and lower structure without an intermediate insulating layer 70, and the compensated charge region 2 can be formed at the bottom of the trench to improve the voltage resistance. Fig. 7 is a cross-sectional view of another semiconductor device manufacturing method according to another embodiment of the present invention, wherein the cross-sectional view corresponds to step S150, and referring to fig. 7, the structure is a deep trench MOSFET with left and right structures, wherein gate polysilicon is disposed around source polysilicon, and a compensation charge region 2 can be formed at the bottom of the trench to improve the voltage resistance. The deep trench mosfet with other structures falls into the scope of the present invention, and will not be described herein.
According to the preparation method of the semiconductor element, the compensation charge area is formed in the insulating layer at the bottom of the groove in the manufacturing process, the electric field intensity of the position with weaker voltage resistance in the epitaxial layer is weakened through the electric field generated by the charges in the compensation charge area, so that the voltage resistance value of the semiconductor element is improved to the target voltage resistance value, and different thicknesses of the first insulating layer are not required to be accurately controlled at different depths of the groove. In addition, the voltage resistance of the MOSFET can be improved under the condition of not changing the physical structure of the MOSFET and ensuring that the resistance of the MOSFET is not changed.
Fig. 8 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present invention, which is used to refine the method for manufacturing a deep trench electrically coupled balanced mosfet in which the first polysilicon and the second polysilicon are in an upper-lower structure and the inter-block insulating layer is disposed between the first polysilicon and the second polysilicon in the above embodiment, and referring to fig. 8, the method for manufacturing a semiconductor device includes:
s210, providing a substrate, and forming an epitaxial layer on the substrate; the side of the epitaxial layer remote from the substrate comprises a trench.
And S220, forming a second insulating layer on the side wall of the groove, the bottom of the groove and the surface of one side of the epitaxial layer far away from the substrate by a chemical vapor deposition method.
Specifically, fig. 9 is a cross-sectional view of the structure corresponding to step S220 in the method for manufacturing a semiconductor device according to the embodiment of the present invention, and referring to fig. 9, the chemical vapor deposition technique is a process of introducing vapor containing a gaseous reactant or a liquid reactant constituting a film element and other gases required for reaction into a reaction chamber, performing a chemical reaction on a surface to be formed, and depositing a solid product on the surface to form a film. Before forming the second insulating layer 51 on the sidewall of the trench 40, the bottom of the trench 40, and the surface of the epitaxial layer 30 on the side away from the substrate 20 by using a chemical vapor deposition method, the sidewall of the trench 40, the bottom of the trench 40, and the surface of the epitaxial layer 30 on the side away from the substrate 20 may be oxidized, so that an oxide layer with a relatively high density is grown on the sidewall of the trench 40, the bottom of the trench 40, and the surface of the epitaxial layer 30 on the side away from the substrate 20 as the second insulating layer 51 with a partial thickness. And then a second insulating layer 51 with the remaining thickness is formed on the surface thereof by a chemical vapor deposition method. The second insulating layer 51 is formed by combining a chemical vapor deposition method and a wet oxygen oxidation growth method, so that the compactness of silicon oxide can be ensured, and the second insulating layer 51 can be prevented from being too large in stress. In addition, the process duration for forming the second insulating layer 51 can also be increased by forming part of the second insulating layer 51 by combining with the chemical vapor deposition method.
S230, depositing a first polycrystalline silicon layer in the groove by a chemical vapor deposition method; and etching the first polysilicon layer by dry etching, so that the height of the etched first polysilicon layer in the groove is less than the depth of the groove.
Specifically, fig. 10-11 are cross-sectional views of the structure corresponding to step S230 in the method for manufacturing a semiconductor device according to the embodiment of the present invention, and referring to fig. 10-11, a first polysilicon material layer 61 is deposited in the trench 40 by a chemical vapor deposition method; the first polysilicon material layer 61 is etched by dry etching so that the height of the first polysilicon layer 60 formed after etching in the trench 40 is smaller than the depth of the trench 40.
S240, removing the second insulating layer which is positioned on one side of the epitaxial layer, far away from the substrate, and positioned in the groove and not covered by the first polycrystalline silicon layer through wet etching; and forming a third insulating layer on one side of the first polysilicon layer far away from the substrate and the side wall in the groove which is not covered by the first polysilicon layer by a chemical vapor deposition method.
Specifically, referring to fig. 12 to fig. 13, after depositing the first polysilicon layer 60 in the trench 40, the second insulating layer 51 located on the side of the epitaxial layer 30 away from the substrate 20 and in the trench 40, which is not covered by the first polysilicon layer 60, is removed by wet etching after depositing the first polysilicon layer 60 in the trench 40 according to the cross-sectional structure view corresponding to step S240 in the method for manufacturing a semiconductor device according to the embodiment of the present invention. Removing the second insulating layer 51 on the side of the epitaxial layer 30 away from the substrate 20, the distance from the upper surface of the first polysilicon layer 60 to the opening of the trench 40 can be prevented from increasing due to the presence of the second insulating layer 51 therein; removing the second insulating layer 51 which is located in the trench 40 and not covered by the first polysilicon layer 60, the width reduction of the trench 40 due to the existence of the second insulating layer 51 therein can be avoided; thereby facilitating the deposition of the material of the intermediate insulating layer 70 on the side of the first polysilicon layer 60 away from the substrate 20 and reducing the difficulty of forming the intermediate insulating layer 70. The trench 40 may be filled with an oxide material by a High Density Plasma Chemical Vapor Deposition (HDP CVD) process, a portion of the oxide material may be removed by wet etching, and the third insulating layer 52 may be formed by leaving an oxide material on a side of the first polysilicon layer 60 away from the substrate 20 and on a sidewall of the trench 40 not covered by the first polysilicon layer 60. In order to improve the compactness of the third insulating layer 52 on the sidewall of the trench 40 not covered by the first polysilicon layer 60, the third insulating layer 52 on the sidewall of the trench 40 not covered by the first polysilicon layer 60 may also be formed by etching to leave an oxide material only on the side of the first polysilicon layer 60 away from the substrate 20 after the HDP CVD process, and then forming silicon oxide on the sidewall of the trench 40 not covered by the first polysilicon layer 60 by thermal oxidation. Wherein the second insulating layer 51 between the first polysilicon layer 60 and the trench 40 and the third insulating layer 52 between the second polysilicon layer 80 and the trench 40 serve as the first insulating layer 50.
In addition, the first insulating layer 50 may also be formed on a side of the epitaxial layer 30 away from the substrate 20; when the third insulating layer 52 is formed on the side of the first polysilicon layer 60 away from the substrate 20 and the side wall of the trench 40 not covered by the first polysilicon layer 60 by the HDP CVD process, the third insulating layer 52 is also formed on the side of the epitaxial layer 30 away from the substrate 20; the third insulating layer 52 on the side of the epitaxial layer 30 remote from the substrate 20 serves as the first insulating layer 50. The first insulating layer 50 on the side of the epitaxial layer 30 remote from the substrate 20 is used for isolation protection of the upper surface of the epitaxial layer 30 in subsequent processes.
And S250, depositing a second polysilicon layer in the groove by a chemical vapor deposition method.
Specifically, fig. 14 is a cross-sectional view of the structure corresponding to step S250 in the method for manufacturing a semiconductor device according to the embodiment of the invention, and referring to fig. 14, a second polysilicon layer 80 is deposited in the trench 40 by a chemical vapor deposition method. The third insulating layer 52 serves as an intermediate insulating layer 70 on the side of the first polysilicon layer 60 remote from the substrate 20. Since the first insulating layer 50 on the trench sidewall 40 includes the second insulating layer 51 formed between the first polysilicon layer 60 and the trench 40 and the third insulating layer 52 formed between the second polysilicon layer 80 and the trench 40, the third insulating layer 52 between the second polysilicon layer 80 and the trench 40 is used as the gate insulating layer 510; the first insulating layer 51 between the first polysilicon layer 60 and the trench 40 is used as a shield gate insulating layer 520.
S260, forming a body region and a source region in the epitaxial layer; the body region and the source region are positioned on the left side and the right side of the second polycrystalline silicon layer; the body region is located on a side close to the substrate opposite the source region.
S270, inputting a voltage which is larger than the initial withstand voltage value of the semiconductor element between the source region and the drain region, and forming a compensation charge region in the first insulating layer at the bottom of the groove through the generated avalanche current; the electric field generated by the charges in the compensation charge area is used for weakening the electric field intensity of the position with weaker voltage resistance in the epitaxial layer so as to improve the voltage resistance value of the semiconductor element to the target voltage resistance value.
Specifically, as the source and drain regions increase in voltage, the electric field in the epitaxial layer 30 increases accordingly. Thus, electrons or holes in the epitaxial layer 30 gain energy under the action of the electric field. However, the distribution of the electric field in the semiconductor is not uniform, and the position where the electric power is most concentrated, i.e., the position where the electric field strength is strongest in the epitaxial layer 30, and the position where the endurance is the weakest. The electrons or holes at this position will move under the influence of the electric field. Electrons and holes moving in epitaxial layer 30 will continuously collide with crystal atoms again, and when the energy of the electrons and holes is large enough, the electrons in the covalent bonds can be excited by such collisions to form free electron-hole pairs. The newly generated electrons and holes also move in opposite directions to recover energy, and electron-hole pairs can be generated again through collision, which is the multiplication effect of carriers. When the reverse voltage is increased to a certain value, the multiplication of the carriers is as same as that of avalanche, the carriers are increased much and quickly, and thus, the reverse current is increased sharply, and avalanche breakdown occurs in the PN junction.
Normally, the avalanche of the MOS transistor is that the drain-source voltage of the MOS transistor exceeds the withstand voltage value. When the drain-source voltage exceeds the withstand voltage value, the MOS tube can be broken down, but the MOS tube is not necessarily broken down after being broken down. When the MOS tube is broken down by the impulse high voltage, the avalanche state occurs, but the voltage between the drain and the source is not zero due to the breakdown, but is maintained at a voltage higher than the nominal withstand voltage, and the current flowing through the drain is the avalanche current. Whether the avalanche is repeated pulse avalanche or single pulse avalanche, if the energy is too large, or the MOS heat dissipation is poor, and the MOS tube is damaged due to overheating after a long time, certain limits are needed to the width and the repetition frequency of the pulse.
Fig. 15 is a cross-sectional view of a structure corresponding to step S270 in the method for manufacturing a semiconductor device according to an embodiment of the present invention, referring to fig. 15, a voltage greater than the initial breakdown voltage of the semiconductor device is inputted between the source region and the drain region (the heavily doped substrate 20), carriers forming an avalanche current 1 (for example, an NMOS electron current, a PMOS hole current, and the directions are opposite) enter the insulating layer at the bottom of the trench 40, and covalent bonds of silicon oxide are opened by collision, so as to generate charges, and further, a compensation charge region 2 is formed. The electric field generated by the charges in the compensation charge region 2 can reduce the electric field strength at the position with weak voltage resistance in the epitaxial layer 30. After the double-gate MOSFET is impacted by avalanche current repeatedly for many times, due to compensation effect brought by electric field and charge coupling, the extreme electric field can generate corresponding positive and negative charges in the corresponding oxide layer area of the bottom gate to compensate charges required by continuously rising of avalanche voltage. These charges are permanently embedded in the oxide layer of the bottom gate and do not disappear even after long-term aging, so that the withstand voltage of the double-gate MOSFET can be permanently improved. Note that when the avalanche voltage increases to a certain degree, the amount of charges in the compensation charge region 2 does not increase due to repulsion between charges, so that the withstand voltage value does not increase after stabilizing to a certain value.
Fig. 16 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present invention, which is used for further refining and supplementing the method for manufacturing a deep trench electrically coupled balanced MOSTET in which the first polysilicon 60 and the second polysilicon 80 are in an upper-lower structure and the inter-insulating layer 70 is sandwiched between the first polysilicon 60 and the second polysilicon 80, and referring to fig. 16, the method for manufacturing a semiconductor device includes:
s310, providing a substrate, and forming an epitaxial layer on the substrate; the side of the epitaxial layer remote from the substrate comprises a trench.
S320, forming a first insulating layer on the side wall and the bottom of the groove, and forming a first polycrystalline silicon layer and a second polycrystalline silicon layer in a space surrounded by the first insulating layer; the second polycrystalline silicon layer is used as grid polycrystalline silicon, and the first insulating layer between the second polycrystalline silicon layer and the groove is used as a grid insulating layer; the first polycrystalline silicon layer is used as source polycrystalline silicon, and the first insulating layer between the first polycrystalline silicon layer and the groove is used as a shielding gate insulating layer.
S330, forming a body region and a source region in the epitaxial layer; the body region and the source region are positioned on the left side and the right side of the second polycrystalline silicon layer; the body region is located on a side close to the substrate opposite the source region.
S340, forming a passivation layer and a metal layer on one side of the epitaxial layer far away from the substrate and one side of the second polycrystalline silicon layer far away from the substrate; the metal layer contacts the body region and the source region through the passivation layer and the first opening of the body region and contacts the second polysilicon layer through the second opening of the passivation layer.
Specifically, fig. 17 is a cross-sectional view of a structure corresponding to step S340 in the method for manufacturing a semiconductor device according to the embodiment of the present invention, and referring to fig. 17, the passivation layer 120 is located on a side close to the substrate 20 with respect to the metal layer. The passivation layer 120 may be formed of an inorganic layer of silicon oxide, silicon nitride, or the like, or an organic layer. Passivation of device surfaces is one of the key technologies in semiconductor device manufacturing. Passivation of the surface of the semiconductor element protects the interconnects within the semiconductor element and the electrical properties of the surface of the semiconductor element, preventing mechanical and chemical damage to the semiconductor element. The metal layer contacts the body region 90 and the source region through the passivation layer 120 and the first opening of the body region 90, and contacts the second polysilicon layer 80 through the second opening of the passivation layer 120; the metal layer in contact with the source region is used as a source electrode S led out; the metal layer in contact with the second polysilicon layer 80 serves as the gate electrode G of the external lead. If the first insulating layer 50 can also be formed on the side of the epitaxial layer 30 away from the substrate 20, the passivation layer 120 is located on the side of the first insulating layer 50 away from the substrate 20 and on the side of the second polysilicon layer 80 away from the substrate 20.
Optionally, a passivation layer 120 and a metal layer are formed on the side of the epitaxial layer 30 away from the substrate 20 and the side of the second polysilicon layer 80 away from the substrate 20, including: forming a passivation layer 120 on the side of the epitaxial layer 30 away from the substrate 20 and the side of the second polysilicon layer 80 away from the substrate 20; etching the passivation layer 120 and the source region of the epitaxial layer 30 to form the first opening and the second opening, wherein the first opening exposes a part of the body region 90; the second opening exposes a portion of the second polysilicon layer 80; a metal layer is formed on the side of the passivation layer 120 remote from the substrate 20, the metal layer contacting the source and body regions 90 through the first opening and contacting the second polysilicon layer 80 through the second opening.
And S350, forming an externally-led drain electrode on one side of the substrate far away from the epitaxial layer.
Specifically, fig. 18 is a cross-sectional view of a structure corresponding to step S350 in the method for manufacturing a semiconductor device according to the embodiment of the present invention, and referring to fig. 18, an external drain electrode 10 is formed on a side of the substrate 20 away from the epitaxial layer 30. The drain electrode 10 may be an entire metal film layer.
S360, forming a compensation charge area in the insulating layer at the bottom of the groove; the electric field generated by the charges in the compensation charge area is used for weakening the electric field intensity of the position with weaker voltage resistance in the epitaxial layer so as to improve the voltage resistance value of the semiconductor element to the target voltage resistance value.
An embodiment of the present invention also provides a semiconductor element formed by the method for manufacturing a semiconductor according to any of the above embodiments, and referring to fig. 5, the semiconductor element includes:
a substrate 20;
an epitaxial layer 30, the epitaxial layer 30 being located on one side of the substrate 20; the side of epitaxial layer 30 remote from substrate 20 includes trenches 40;
a first insulating layer 50 on the sidewalls and bottom of the trench 40;
a first polysilicon layer 60 and a second polysilicon layer 80 located in a space surrounded by the first insulating layer 50; wherein, the second polysilicon layer 80 is used as gate polysilicon, and the first insulating layer 50 between the second polysilicon layer 80 and the trench 40 is used as gate insulating layer;
a drain region 10 located on a side of the substrate 20 away from the epitaxial layer 30;
a compensation charge region 2 in the first insulating layer 50 at the bottom of the trench 40; the electric field generated by the charges in the compensation charge region 2 is used to weaken the electric field strength at the position with weaker voltage resistance in the epitaxial layer 30, so as to increase the voltage resistance value of the semiconductor element to the target voltage resistance value.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (9)
1. A method for manufacturing a semiconductor device, comprising:
providing a substrate, and forming an epitaxial layer on the substrate; one side of the epitaxial layer far away from the substrate comprises a groove;
forming a first insulating layer on the side wall and the bottom of the groove, and forming a first polycrystalline silicon layer and a second polycrystalline silicon layer in a space surrounded by the first insulating layer; the second polycrystalline silicon layer is used as grid polycrystalline silicon, and the first insulating layer between the second polycrystalline silicon layer and the groove is used as a grid insulating layer; the first polycrystalline silicon layer is used as source polycrystalline silicon, and a first insulating layer between the first polycrystalline silicon layer and the groove is used as a shielding gate insulating layer;
forming a body region and a source region in the epitaxial layer; the body region and the source region are positioned on the left side and the right side of the second polycrystalline silicon layer; the body region is positioned at one side close to the substrate relative to the source region;
forming a compensation charge area in the first insulating layer at the bottom of the groove; the electric field generated by the charges in the compensation charge area is used for weakening the electric field intensity of a position with weak withstand voltage in the epitaxial layer so as to improve the withstand voltage value of the semiconductor element to a target withstand voltage value;
the forming of the compensation charge region in the first insulating layer at the bottom of the trench includes:
inputting a voltage which is larger than the initial withstand voltage value of the semiconductor element between the source region and the drain region, and forming a compensation charge region in the first insulating layer at the bottom of the trench through the generated avalanche current; wherein the drain region is a heavily doped substrate.
2. The method according to claim 1, wherein the second polysilicon layer is located on a side of the first polysilicon layer away from the substrate; the first polycrystalline silicon layer and the second polycrystalline silicon layer are separated by an intermediate insulating layer;
forming a first insulating layer on the side wall and the bottom of the trench, and forming a first polysilicon layer and a second polysilicon layer in a space surrounded by the first insulating layer, including:
forming a second insulating layer on the side wall of the groove, the bottom of the groove and the surface of one side of the epitaxial layer far away from the substrate;
depositing a first polysilicon layer in the groove by a chemical vapor deposition method;
etching the first polysilicon layer by dry etching, so that the height of the etched first polysilicon layer in the groove is smaller than the depth of the groove;
removing the second insulating layer which is positioned on one side of the epitaxial layer far away from the substrate and is positioned in the groove and not covered by the first polycrystalline silicon layer through wet etching;
forming a third insulating layer on one side of the first polycrystalline silicon layer far away from the substrate and the side wall which is not covered by the first polycrystalline silicon layer in the groove;
depositing the second polysilicon layer in the trench by a chemical vapor deposition method; and a third insulating layer on one side of the first polycrystalline silicon layer, which is far away from the substrate, is used as the intermediate insulating layer, and a second insulating layer between the first polycrystalline silicon layer and the groove and a third insulating layer between the second polycrystalline silicon layer and the groove are used as the first insulating layer.
3. The method for manufacturing a semiconductor element according to claim 2, wherein the first insulating layer is further formed on a side of the epitaxial layer away from the substrate;
when a third insulating layer is formed on one side of the first polycrystalline silicon layer, which is far away from the substrate, and on the side wall, which is not covered by the first polycrystalline silicon layer, in the groove, the third insulating layer is also formed on one side of the epitaxial layer, which is far away from the substrate; and the third insulating layer at one side of the epitaxial layer, which is far away from the substrate, is used as the first insulating layer at one side of the epitaxial layer, which is far away from the substrate.
4. The method of claim 1, wherein the forming body and source regions in the epitaxial layer comprises:
forming the body region and the source region in the epitaxial layer by means of ion implantation;
wherein the ions implanted into the source region are the same as the ion type doped in the epitaxial layer.
5. The method according to claim 3, wherein the source region and the epitaxial layer are both N-type doped, and the body region is P-type doped; or the source region and the epitaxial layer are both doped in a P-type manner, and the body region is doped in an N-type manner.
6. The method of manufacturing a semiconductor element according to claim 1, further comprising, after forming the body region and the source region in the epitaxial layer:
forming a passivation layer and a metal layer on one side of the epitaxial layer far away from the substrate and one side of the second polycrystalline silicon layer far away from the substrate; the metal layer contacts the body and source regions through the passivation layer and the first opening of the body region and contacts the second polysilicon layer through the second opening of the passivation layer.
7. The method of claim 6, wherein forming a passivation layer and a metal layer on the side of the epitaxial layer away from the substrate and the side of the second polysilicon layer away from the substrate comprises:
forming the passivation layer on one side of the epitaxial layer far away from the substrate and one side of the second polycrystalline silicon layer far away from the substrate;
etching the passivation layer and the source region of the epitaxial layer to form the first opening and the second opening, wherein the first opening exposes part of the body region; the second opening exposes a part of the second polysilicon layer;
forming a metal layer on one side of the passivation layer away from the substrate, wherein the metal layer is in contact with the source region and the body region through the first opening; through the second opening, in contact with the second polysilicon layer.
8. The method according to claim 7, wherein a metal layer in contact with the source region serves as a source electrode for external lead; the metal layer in contact with the second polycrystalline silicon layer is used as a gate electrode led out;
and forming an externally-led drain electrode on one side of the substrate far away from the epitaxial layer.
9. A semiconductor element formed by the method for manufacturing a semiconductor element according to any one of claims 1 to 8, comprising:
a substrate;
the epitaxial layer is positioned on one side of the substrate; one side of the epitaxial layer, which is far away from the substrate, comprises a groove;
the first insulating layer is positioned on the side wall and the bottom of the groove;
a first polysilicon layer and a second polysilicon layer located in a space surrounded by the first insulating layer; the second polycrystalline silicon layer is used as grid polycrystalline silicon, and the first insulating layer between the second polycrystalline silicon layer and the groove is used as a grid insulating layer; the first polycrystalline silicon layer is used as source polycrystalline silicon, and a first insulating layer between the first polycrystalline silicon layer and the groove is used as a shielding gate insulating layer;
a body region and a source region; the body region and the source region are formed in the epitaxial layer; the body region and the source region are positioned at the left side and the right side of the second polycrystalline silicon layer, and relative to the source region, the body region is positioned at one side close to the substrate;
the compensation charge area is positioned in the first insulating layer at the bottom of the groove; the electric field generated by the charges in the compensation charge area is used for weakening the electric field intensity of the position with weaker voltage resistance in the epitaxial layer so as to improve the voltage resistance value of the semiconductor element to a target voltage resistance value.
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