JP5037103B2 - Silicon carbide semiconductor device - Google Patents

Description

The present invention relates to a silicon carbide semiconductor equipment, and more particularly to a silicon carbide semiconductor power device.

  In order to overcome the physical property limits of power devices using silicon, power device DMOSFETs using silicon carbide have been developed. In particular, in the MOS channel section for controlling the on / off of the device, development relating to improvement of channel mobility and reduction of channel length has been vigorously performed in order to reduce the channel resistance of the element.

  The power MOSFET shown in Patent Document 1 is called a UMOSFET, and is a well-known device useful in high voltage and high power applications. The UMOSFET is a MOSFET in which a trench gate electrode portion is formed in a U-shaped groove, and includes an oxide layer formed on the groove sidewall of the U-shaped groove and a gate electrode formed in contact with the oxide layer. . The UMOSFET includes a source electrode and a drain electrode. When a positive voltage is not applied to the gate electrode, the p-type silicon carbide base layer electrically isolates the n-type silicon carbide source layer from the n-type silicon carbide drift layer (off state). When a positive voltage is applied to the gate electrode, an electron inversion layer, that is, a channel is formed in the p-type silicon carbide base layer along the sidewall of the U-shaped groove. As a result, a current flows from the drain electrode through the n-type silicon carbide substrate, the n-type silicon carbide drift layer, the p-type silicon carbide base layer, and the n-type silicon carbide source layer toward the source electrode. (On state).

US Pat. No. 5,506,421

  Silicon carbide has a dielectric breakdown electric field 10 times larger than that of silicon, and when it is used as a material for a vertical power MOSFET, a unipolar element with high breakdown voltage and low resistance and low switching loss can be obtained. However, when a gate insulating thermal oxide film is used on the silicon carbide in the trench gate electrode portion for controlling on / off of the vertical MOSFET, the MOS channel mobility is formed at the interface between the silicon carbide and the thermal oxide film. It becomes lower due to the interface state, and the on-resistance as the whole element increases.

  In order to reduce the channel resistance, it is effective to increase the channel mobility by reducing the channel length or decreasing the acceptor impurity concentration of the p-type silicon carbide base layer.

  However, in the UMOSFET having the structure described in Patent Document 1, the p-type silicon carbide base layer forms a channel. Therefore, when the channel length is shortened, the p-type silicon carbide base layer for off breakdown voltage must be thinned, and the breakdown voltage characteristics cannot be maintained. Further, when the acceptor impurity concentration of the p-type silicon carbide base layer is lowered, the p-type acceptor impurity concentration of the channel forming portion must be lowered, and the breakdown voltage characteristic cannot be maintained. As described above, there is a problem that the on-resistance of the channel cannot be lowered while maintaining the breakdown voltage characteristics.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to reduce the on-resistance of the channel while maintaining the withstand voltage characteristics.

ｄ＞ｄ _１ ＋ｄ _２ ・・・（３）
ただし、
ε _ｒ ：炭化珪素の比誘電率
ε _０ ：真空誘電率（Ｆ／ｍ）
ｅ：電子の電荷量（Ｃ）
Ｎ _ｄ１ ：前記第１導電型炭化珪素ドリフト層の不純物濃度（ｃｍ ^−３ ）
Ｎ _ｄ２ ：前記第１導電型炭化珪素ソース層の不純物濃度（ｃｍ ^−３ ）
Ｎ _ａ ：前記第２導電型炭化珪素チャネル層の不純物濃度（ｃｍ ^−３ ）
Ｖ _ｄ ：前記第１導電型炭化珪素ドリフト層と前記第２導電型炭化珪素チャネル層が形成するｐｎ接合間における炭化珪素の拡散電位（ｅＶ）
Ｖ：前記第１導電型炭化珪素ドリフト層と前記第２導電型炭化珪素チャネル層が形成するｐｎ接合に対して逆方向に印加される電圧の電位ポテンシャル（ｅＶ） A silicon carbide semiconductor device according to claim 1 of the present invention is formed on a first conductivity type silicon carbide drift layer formed on a surface of a first conductivity type silicon carbide semiconductor substrate, and on the first conductivity type silicon carbide drift layer. A second conductivity type silicon carbide channel layer, a second conductivity type silicon carbide base layer provided in the first conductivity type silicon carbide drift layer in contact with a lower surface of the second conductivity type silicon carbide channel layer, Electrically connected to the first conductivity type silicon carbide source layer formed on the two conductivity type silicon carbide channel layer, the first conductivity type silicon carbide source layer, and the second conductivity type silicon carbide base layer; A source electrode provided; a drain electrode provided on the back surface of the first conductivity type silicon carbide semiconductor substrate; and a surface of the first conductivity type silicon carbide source layer, penetrating through the second conductivity type silicon carbide channel layer, First guide Mold inner wall of the trench reaching the silicon carbide drift layer and a gate electrode formed through an insulating film, the thickness of the second conductivity type silicon carbide channel layer d ([mu] m) is the following formula (1) - (3 ), The lower end of the second conductivity type silicon carbide base layer is located below the lower end of the trench, and the second conductivity type silicon carbide base layer is formed by the second conductivity type silicon carbide base layer. The depletion layer is provided apart from the trench so that the depletion layer extends below the trench .

d> d ₁ + d ₂ (3)
However,
ε _r : relative dielectric constant of silicon carbide
ε ₀ : Vacuum dielectric constant (F / m)
e: Charge amount of electrons (C)
N _d1 : Impurity concentration (cm ⁻³ ) of the first conductivity type silicon carbide drift layer
N _d2 : Impurity concentration (cm ⁻³ ) of the first conductivity type silicon carbide source layer
N _a : Impurity concentration (cm ⁻³ ) of the second conductivity type silicon carbide channel layer
V _d : Diffusion potential (eV) of silicon carbide between pn junctions formed by the first conductivity type silicon carbide drift layer and the second conductivity type silicon carbide channel layer
V: potential potential (eV) of voltage applied in the opposite direction to the pn junction formed by the first conductivity type silicon carbide drift layer and the second conductivity type silicon carbide channel layer

  According to the silicon carbide semiconductor device of the present invention, the on-resistance of the second conductivity type silicon carbide channel layer can be lowered while maintaining the breakdown voltage characteristics.

<Embodiment 1>
FIG. 1 is a cross-sectional view of a silicon carbide MOSFET which is a silicon carbide semiconductor device according to the present embodiment. The silicon carbide MOSFET includes an n-type silicon carbide substrate 1, an n-type silicon carbide drift layer 2, a p-type silicon carbide base layer 3, a p-type silicon carbide channel layer 4, an n-type silicon carbide source layer 5, and p A silicon carbide contact layer 6, a gate insulating film 7, a gate electrode 8, a source electrode 9, a drain electrode 10, and a trench gate electrode portion 11 are provided.

The structure of the silicon carbide semiconductor device according to the present embodiment will be described together with the manufacturing method thereof with reference to FIGS. In FIG. 2, first, n-type silicon carbide drift layer 2 that is a first conductivity type silicon carbide drift layer is formed on the surface of n-type silicon carbide substrate 1 that is a first conductivity type silicon carbide semiconductor substrate. N-type silicon carbide drift layer 2 is formed by an epitaxial method comprising thermal CVD (Chemical Vapor Deposition). The n-type silicon carbide drift layer 2 has, for example, a temperature of 1500 to 1600 ° C., an atmospheric pressure of 250 mbar, a carrier gas flow rate: H ₂ = 50 l / min, a generated gas flow rate: SiH ₄ / C ₃ H ₈ / N ₂ = 9 ccm / 4. The film thickness is 7 to 15 μm under the conditions of 5 ccm / 1.5 ccm and n-type dopant concentration of 5e15 to 1.5e16 cm ⁻³ .

Next, p-type silicon carbide channel layer 4 which is the second conductivity type silicon carbide channel layer is formed on n-type silicon carbide drift layer 2. The p-type silicon carbide channel layer 4 is formed by an epitaxial method after the n-type silicon carbide drift layer 2 is formed and N ₂ in the generated gas is switched to TMA (trimethylaluminum). In the present embodiment, p-type silicon carbide channel layer 4 is formed by an epitaxial method, but may be formed by ion implantation of Al ions. The film thickness and acceptor impurity concentration of p-type silicon carbide channel layer 4 will be described later.

Next, n-type silicon carbide source layer 5 which is a first conductivity type silicon carbide source layer is formed on p-type silicon carbide channel layer 4. The n-type silicon carbide source layer 5 is formed by an epitaxial method after the p-type silicon carbide channel layer 4 is formed and the TMA of the generated gas is switched to N ₂ again. N-type silicon carbide source layer 5 is formed, for example, so as to have a film thickness of 0.1 to 1.0 μm under conditions of a dopant concentration of 1e19 to 3e19 cm ⁻³ . In the present embodiment, n-type silicon carbide source layer 5 is formed by an epitaxial method. N-type silicon carbide source layer 5 having the same depth and impurity concentration is formed by ion implantation of N ions. Also good.

  The thickness and acceptor impurity concentration of p-type silicon carbide channel layer 4 described above are such that punch-through due to the short channel effect does not occur between n-type silicon carbide drift layer 2 and n-type silicon carbide source layer 5. Must be set to

The width d ₁ (μm) of the depletion layer formed on the p-type silicon carbide channel layer 4 side from the interface between n-type silicon carbide drift layer 2 and p-type silicon carbide channel layer 4 is expressed by the following equation. Here, ε _r is the relative dielectric constant of silicon carbide, ε ₀ is the vacuum dielectric constant (F / m), e is the charge amount of electrons (C), and N _d1 is the donor impurity concentration of the n-type silicon carbide drift layer 2 ( cm ⁻³ ), N _a is the acceptor impurity concentration (cm ⁻³ ) of the p-type silicon carbide channel layer 4, and V _d is between the pn junction formed by the n-type silicon carbide drift layer 2 and the p-type silicon carbide channel layer 4. It is the diffusion potential (eV) of silicon carbide. V is a potential potential (eV) of a voltage applied in the opposite direction to the pn junction formed by n-type silicon carbide drift layer 2 and p-type silicon carbide channel layer 4.

Similarly, the width d ₂ (μm) of the depletion layer formed on the p-type silicon carbide channel layer 4 side from the interface between the n-type silicon carbide source layer 5 and the p-type silicon carbide channel layer 4 is expressed by the following equation. Is done. Here, N _d2 is the donor impurity concentration (cm ⁻³ ) of the n-type silicon carbide source layer 5.

In order to prevent punch-through due to the short channel effect between n-type silicon carbide drift layer 2 and n-type silicon carbide source layer 5, film thickness d of p-type silicon carbide channel layer 4 is as follows: It is necessary to satisfy.
d> d ₁ + d ₂ (3)

The channel resistance is determined by the channel length d and the channel mobility. In general, since channel mobility depends on acceptor impurity concentration Na of p-type silicon carbide channel layer 4, in other words, channel resistance depends on channel length d and acceptor impurity concentration Na. Therefore, the optimum in order to obtain the channel resistance, the channel resistance, the channel length d, expressed in the acceptor impurity concentration Na, d> d 1 ₊ d satisfies _two of the minimum channel length d value and the value of the acceptor impurity concentration Na It is desirable to set in combination.

  2 formed as described above, p-type silicon carbide base layer 3 which is the second conductivity type silicon carbide base layer is in contact with the lower surface of p-type silicon carbide channel layer 4 as shown in FIG. Provided in n-type silicon carbide drift layer 2.

Specifically, a pattern mask is formed on n-type silicon carbide source layer 5, and the concentration is 5 × e ¹⁷ to 2 × in the region of 0.7 to 1.0 μm from the deepest part of p-type silicon carbide channel layer 4. A p-type silicon carbide base layer 3 is formed by selectively implanting Al ions of e ¹⁸ cm ⁻³ . Here, the N concentration of n-type silicon carbide source layer 5 is set sufficiently higher than the Al concentration of p-type silicon carbide base layer 3. Therefore, even if Al ion implantation is performed in order to form p-type silicon carbide base layer 3, n-type silicon carbide source layer 5 near the crystal surface above p-type silicon carbide base layer 3 is sufficiently effectively n Functions as a type dopant. In the present embodiment, the acceptor impurity concentration of p-type silicon carbide base layer 3 is set higher than the acceptor impurity concentration of p-type silicon carbide channel layer 4. In other words, the acceptor impurity concentration of p-type silicon carbide channel layer 4 is set lower than the acceptor impurity concentration of p-type silicon carbide base layer 3. Moreover, the adjacent p-type silicon carbide base layers 3 are arranged 2 to 4 μm apart, for example.

Next, as shown in FIG. 4, a part of n-type silicon carbide source layer 5 is made p-type, and p-type silicon carbide contact layer 6 connecting source electrode 9 and p-type silicon carbide base layer 3 described later is formed. . Specifically, p-type after the pattern mask is removed to form a silicon carbide base layer 3, newly forming a pattern mask on the n-type silicon carbide source layer 5, the concentration 1.5e ²⁰ to 5 high Al ions. It is formed by injecting at a depth of 0e ²⁰ cm ⁻³ to the depth reaching the p-type silicon carbide base layer 3. Thus, by providing p-type silicon carbide connector layer 6 having a higher concentration than p-type silicon carbide base layer 3 between source electrode 9 and p-type silicon carbide base layer 3, source electrode 9 and p-type silicon carbide are provided. It is possible to prevent a Schottky barrier from occurring with the base layer 3. After removing the mask, the element substrate is annealed at 1400 to 1900 ° C. by an annealing apparatus to electrically activate the implanted ion region.

  Next, the n-type silicon carbide source layer 5 is formed on the inner wall of the trench 12 through the p-type silicon carbide channel layer 4 and reaching the n-type silicon carbide drift layer 2 through a gate insulating film as an insulating film from the surface. A gate electrode 8 to be formed is formed. The trench gate electrode portion 11 includes a gate insulating film 7 and a gate electrode 8.

  Specifically, as shown in FIG. 5, the width is 0.2 to 2.0 μm at the center between a pair of adjacent p-type silicon carbide base layers 3 by sacrificial oxidation or RIE (Reactive Ion Etching). Then, trench 12 is formed that reaches n-type silicon carbide drift layer 2 in contact with the deepest portion of p-type silicon carbide channel layer 4. Therefore, as shown in FIG. 5, p-type silicon carbide base layer 3 is provided apart from trench 12. Further, the lower end of trench 12 is formed to be located above the lower end of p-type silicon carbide base layer 3. In other words, the lower end of p-type silicon carbide base layer 3 is formed so as to be located below the lower end of trench 12.

  Next, as shown in FIG. 6, the gate insulating film 7 is formed on the element surface including the inner wall of the trench 12. After that, the gate electrode 8 that at least contacts the gate insulating film 7 formed on the inner wall of the trench 12 is selectively formed. The gate electrode 8 is formed by, for example, an electrode formation technique, a lithography technique, and an etching technique.

  Next, as shown in FIG. 7, source electrode 9 is provided in electrical connection with n-type silicon carbide source layer 5 and p-type silicon carbide base layer 3. In the present embodiment, source electrode 9 is electrically connected to p-type silicon carbide base layer 3 by p-type silicon carbide connector layer 6. Drain electrode 10 is provided on the back surface of n-type silicon carbide substrate 1. These electrodes are formed by, for example, a lithography technique, an etching technique, and an electrode forming technique.

  Finally, in order to alloy the source electrode 9 and the drain electrode 10 with the silicon carbide in contact with the n-type silicon carbide substrate 1, for example, the substrate 950 to 1000 ° C., the processing time 20 to 60 seconds, RTA (Rapid Thermal Anneal) treatment is performed at a temperature rising rate of 10 to 25 ° C./second. Thereby, the main part of the element structure as shown in FIG. 7 is completed.

  In the silicon carbide MOSFET configured as described above, when a positive voltage is applied to the gate electrode 8, electron inversion occurs in the vicinity of the interface of the p-type silicon carbide channel layer 4 in contact with the gate insulating film 7 on the side wall of the trench 12. A layer is formed and the MOSFET is turned on. On the other hand, when no voltage is applied to gate electrode 8, the voltage applied to drain electrode 10 is applied to a depletion layer extending between p-type silicon carbide base layer 3 and n-type silicon carbide drift layer 2, and MOSFET is Turn off.

  In the silicon carbide MOSFET that operates as described above, the p-type silicon carbide base layer 3 and the p-type silicon carbide channel layer 4 for off breakdown voltage can be formed independently. Therefore, p-type silicon carbide base layer 3 that maintains the off breakdown voltage of the device is formed sufficiently thick to obtain a sufficient off breakdown voltage, while p-type silicon carbide channel layer 4 that determines the channel length is replaced with p-type silicon carbide base. Regardless of the thickness of the layer 3, it can be formed sufficiently thin. If the thickness of p-type silicon carbide channel layer 4 is reduced, defect-induced levels at the gate oxide film / silicon carbide interface can be reduced, and the channel mobility can be increased. As a result, the on-resistance of the channel can be lowered. In this way, it is possible to maintain the breakdown voltage characteristics and reduce the on-resistance of the channel without any trade-off.

  Further, when the p-type silicon carbide channel layer 4 is thinned, the required trench 12 can be made shallower, which is extremely advantageous for increasing the density of the trench gate electrode portion 11 as compared with the conventional UMOSFET. is there.

  Further, the thickness d of the p-type silicon carbide channel layer 4 is set so that the width of the depletion layer formed between the n-type silicon carbide drift layer 2 and the p-type silicon carbide channel layer 4, and the n-type silicon carbide source layer 5 It is larger than the sum of the widths of the depletion layers formed between the p-type silicon carbide channel layers 4. Therefore, punch-through due to the short channel effect can be prevented between n-type silicon carbide drift layer 2 and n-type silicon carbide source layer 5.

  Further, the acceptor impurity concentration of p-type silicon carbide channel layer 4 is lower than the acceptor impurity concentration of p-type silicon carbide base layer 3. As a result, the on-resistance of the channel can be further lowered while maintaining the off-breakdown voltage.

  Further, since the lower end of p-type silicon carbide base layer 3 is located below the lower end of trench 12, a depletion layer due to p-type silicon carbide base layer 3 spreads also under trench 12. Therefore, the lower part of the trench 12 is shielded by the depletion layer, and electric field concentration at the bottom of the trench 12 can be avoided. In this way, the voltage tolerance of the trench gate electrode part 11 at the time of on / off control can be improved.

  Further, in the case of a MOSFET having a general lateral channel, in order to reduce the channel width to 0.5 μm or less, the lithography technique requires accuracy within at least ± 0.2 μm and is difficult to produce. However, in this embodiment, it is a MOSFET having a vertical channel, and p-type silicon carbide channel layer 4 is formed by an epitaxial method. In such a film formation process, the film thickness can be controlled with relatively high accuracy even in the order, so that a short channel can be easily formed.

1 is a cross sectional view showing a silicon carbide semiconductor device according to a first embodiment. 5 is a cross sectional view showing a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a cross sectional view showing a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a cross sectional view showing a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a cross sectional view showing a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a cross sectional view showing a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a cross sectional view showing a method for manufacturing the silicon carbide semiconductor device according to the first embodiment . FIG .

Explanation of symbols

  1 n-type silicon carbide substrate, 2 n-type silicon carbide drift layer, 3 p-type silicon carbide base layer, 4 p-type silicon carbide channel layer, 5 n-type silicon carbide source layer, 6 p-type silicon carbide contact layer, 7 gate insulation Film, 8 gate electrode, 9 source electrode, 10 drain electrode, 11 trench gate electrode part, 12 trench.

Claims (2)

A first conductivity type silicon carbide drift layer formed on the surface of the first conductivity type silicon carbide semiconductor substrate;
A second conductivity type silicon carbide channel layer formed on the first conductivity type silicon carbide drift layer;
A second conductivity type silicon carbide base layer provided in the first conductivity type silicon carbide drift layer in contact with the lower surface of the second conductivity type silicon carbide channel layer;
A first conductivity type silicon carbide source layer formed on the second conductivity type silicon carbide channel layer;
A source electrode provided in electrical connection with the first conductivity type silicon carbide source layer and the second conductivity type silicon carbide base layer;
A drain electrode provided on the back surface of the first conductivity type silicon carbide semiconductor substrate;
A gate electrode formed on the inner wall of the trench reaching the first conductivity type silicon carbide drift layer through the second conductivity type silicon carbide channel layer from the surface of the first conductivity type silicon carbide source layer via an insulating film And
The thickness d (μm) of the second conductivity type silicon carbide channel layer satisfies the following formulas (1) to (3):
The lower end of the second conductivity type silicon carbide base layer is located below the lower end of the trench,
The second conductivity type silicon carbide base layer is provided apart from the trench to such an extent that a depletion layer formed by the second conductivity type silicon carbide base layer extends below the trench.
Silicon carbide semiconductor device.

d> d ₁ + d ₂ (3)
However,
ε _r : relative dielectric constant of silicon carbide
ε ₀ : Vacuum dielectric constant (F / m)
e: Charge amount of electrons (C)
N _d1 : Impurity concentration (cm ⁻³ ) of the first conductivity type silicon carbide drift layer
N _d2 : Impurity concentration (cm ⁻³ ) of the first conductivity type silicon carbide source layer
N _a : Impurity concentration (cm ⁻³ ) of the second conductivity type silicon carbide channel layer
V _d : Diffusion potential (eV) of silicon carbide between pn junctions formed by the first conductivity type silicon carbide drift layer and the second conductivity type silicon carbide channel layer
V: potential potential (eV) of voltage applied in the opposite direction to the pn junction formed by the first conductivity type silicon carbide drift layer and the second conductivity type silicon carbide channel layer The impurity concentration of the second conductivity type silicon carbide channel layer is lower than the impurity concentration of the second conductivity type silicon carbide base layer,
The silicon carbide semiconductor device according to claim 1.

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