CN114266264A

CN114266264A - Signal demodulation method, apparatus, receiver and computer readable storage medium

Info

Publication number: CN114266264A
Application number: CN202111528708.0A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shenzhen Xhorse Electronics Co Ltd
Current assignee: Shenzhen Xhorse Electronics Co Ltd
Priority date: 2021-12-14
Filing date: 2021-12-14
Publication date: 2022-04-01

Abstract

A signal demodulation method, apparatus, receiver and computer readable storage medium are provided, the method comprising obtaining a first baseband envelope signal within a first symbol period; the logic level of the first baseband envelope signal is a normal bit level; acquiring a second baseband envelope signal in a second symbol period; the second symbol period is a backward period of the first symbol period; determining a level mean value of the first baseband envelope signal to obtain a first mean value; performing direct current removal processing on the second baseband envelope signal according to the first average value to obtain a reference second signal; determining a logic level of the second baseband envelope signal from the reference second signal. By adopting the method, the abnormal bit level can be judged, and the accuracy of logic level judgment is improved.

Description

Signal demodulation method, apparatus, receiver and computer readable storage medium

Technical Field

The present invention relates to the field of signal processing technologies, and in particular, to a signal demodulation method, an apparatus, a receiver, and a computer-readable storage medium.

Background

The principle of Radio Frequency Identification (RFID) is that a reader and a tag perform non-contact data communication to achieve the purpose of identifying a target. Thus, NFC (Near Field Communication) technology has been developed, and devices using NFC can exchange data in close proximity to each other, which is an evolution of integration of contactless radio frequency identification and interconnection technology.

In the determination of the logic level of the signal, the threshold value is conventionally determined by a moving average method, in which 3 groups of 64 consecutive data shift registers are used, and the average values of three groups of data are respectively determined, so as to determine the logic level of the signal. The conventional demodulation method cannot accurately detect an abnormal logic level of a signal.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a signal demodulation method, apparatus, receiver and computer readable storage medium for solving the above technical problems.

A method of signal demodulation, the method comprising:

acquiring a first baseband envelope signal in a first code element period; the logic level of the first baseband envelope signal is a normal bit level;

acquiring a second baseband envelope signal in a second symbol period; the second symbol period is a backward period of the first symbol period;

determining a level mean value of the first baseband envelope signal to obtain a first mean value;

performing direct current removal processing on the second baseband envelope signal according to the first average value to obtain a reference second signal;

determining a logic level of the second baseband envelope signal from the reference second signal.

A signal demodulation apparatus, the apparatus comprising:

the baseband envelope signal monitoring module is used for acquiring a first baseband envelope signal in a first code element period; the logic level of the first baseband envelope signal is a normal bit level;

the baseband envelope signal monitoring module is further configured to acquire a second baseband envelope signal in a second symbol period; the second symbol period is a backward period of the first symbol period;

the direct current removing module is used for determining the level mean value of the first baseband envelope signal to obtain a first mean value;

the dc removing module is further configured to perform dc removing processing on the second baseband envelope signal according to the first average value to obtain a reference second signal;

a symbol decision module for determining a logic level of the second baseband envelope signal from the reference second signal.

In one embodiment, the signal demodulation device further comprises a digital rectification module and a digital channel filtering module; the digital rectification module is used for acquiring a modulation signal in a first code element period; rectifying the modulation signal in the first code element period to obtain a double-frequency modulation carrier signal; the digital channel filtering module is configured to filter the double frequency modulated carrier signal to obtain a first baseband envelope signal in a first symbol period.

In one embodiment, the digital channel filtering module is configured to filter the double frequency modulated carrier signal through a cascaded integrator-comb filter to obtain a first baseband envelope signal in a first symbol period.

In one embodiment, the digital channel filtering module is configured to filter the double frequency modulated carrier signal through a cascaded integrator-comb filter to obtain a filtered double frequency modulated carrier signal;

and when the communication protocol adopted by the modulation signal is a preset communication protocol, down-sampling the filtered double-frequency modulation carrier signal through a down-sampling filter to obtain a first baseband envelope signal in a first code element period.

A receiver comprising a memory storing a computer program and a processor implementing the steps of the method of embodiments of the application when executing the computer program.

A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method of embodiments of the application.

In the signal demodulation method, the signal demodulation device, the signal demodulation receiver, and the computer-readable storage medium in this embodiment, because of the existence of the dc component, the decision threshold according to which the logic level is determined is particularly important, and because the logic level of the first baseband envelope signal is the normal bit level, the logic level of the second baseband envelope signal can be determined, and the logic level decision accuracy is improved by determining the level mean value of the first baseband envelope signal, obtaining the first mean value, performing dc removal processing on the second baseband envelope signal according to the first mean value, obtaining the reference second signal, that is, performing dc removal processing on the mean value of the signal based on the normal bit level.

Drawings

FIG. 1 is a block diagram of a front-end analog circuit of a signal demodulation method according to an embodiment;

FIG. 2 is a demodulation waveform of a front-end analog circuit in one embodiment;

FIG. 3 is a diagram of ADC conversion waveforms in one embodiment;

FIG. 4 is a timing diagram illustrating the synchronization of the I and Q ASK modulated signals according to one embodiment;

FIG. 5 is a waveform illustrating bit types in one embodiment;

FIG. 6 is a timing diagram illustrating the removal of DC component signals according to one embodiment;

FIG. 7 is a timing diagram illustrating the removal of DC component signals according to another embodiment;

FIG. 8 is a flow diagram illustrating a method for demodulating a signal according to one embodiment;

FIG. 9 is a waveform illustrating sampling of subcarriers in one embodiment;

FIG. 10 is a timing diagram of an embodiment of the end bit signal with the DC component removed;

FIG. 11 is a timing diagram of an embodiment of a collision bit signal with a DC component removed;

FIG. 12 is a schematic block diagram of an in-phase quadrature integration type bit synchronization circuit in one embodiment;

FIG. 13 is a timing diagram of the decision output of the IQ integration type bit synchronization circuit in one embodiment;

FIG. 14 is a waveform diagram illustrating modulation signal rectification in one embodiment;

FIG. 15 is a waveform diagram of low pass filtering in one embodiment;

FIG. 16 is a block diagram of a second order CIC filter in accordance with one embodiment;

FIG. 17 is a waveform diagram of a baseband envelope signal in one embodiment;

fig. 18 is a block diagram showing the structure of a signal demodulating apparatus according to an embodiment;

fig. 19 is a block diagram showing the construction of a signal demodulating apparatus according to another embodiment;

FIG. 20 is a flowchart illustrating a signal demodulation method according to another embodiment;

fig. 21 is a waveform diagram illustrating demodulation of a digital signal according to an embodiment.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.

It should be noted that all directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly, and the connection may be a direct connection or an indirect connection.

In addition, the descriptions related to "first", "second", etc. in the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. For ease of understanding, the "first" in the various embodiments may be considered to relate to a first baseband envelope signal and the "second" may be considered to relate to a second baseband envelope signal.

In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.

In one embodiment, as shown in fig. 1, a block diagram of a front-end analog circuit of a signal demodulation method in one embodiment is shown. Including a contactless tag 110 and a receiver 120. The communication protocols supported by the contactless tag 110 include, but are not limited to, ISO1443A and ISO 15693. Receiver 120 in fig. 1 is a block circuit diagram of an analog front end of the receiver. The Digital-to-analog converter comprises an integrator, a band-pass filter, a gain amplifier and an ADC (analog-to-Digital converter) which are connected in sequence. The subcarrier with the frequency of 13.56MHz is multiplied by two paths of orthogonal sampling clocks of an I path and a Q path of 13.56MHz respectively, the sampled signals are transmitted to a band-pass filter, subcarrier components and out-of-band noise are filtered, and the signals are amplified by a gain amplifier to obtain two paths of ASK modulation carrier signals of the I path and the Q path of 848KHz (Kilo Hertz). As shown in fig. 2, the demodulation waveforms of the front-end analog circuit in one embodiment include (a) subcarrier waveforms, (b) I sampling waveforms, and (c) Q sampling waveforms.

The two paths of ASK modulated carrier signals of the I path and the Q path of 848KHz are converted by the ADC and quantized into 4bit data. FIG. 3 is a diagram illustrating ADC conversion waveforms in one embodiment. Fig. 3(b) shows the I-channel sampling waveform in fig. 2 (b). Fig. 3(c) shows the Q-path sampling waveform in fig. 2 (c). Also included in fig. 3 is the ADC sampling clock. Fig. 3(d) shows I-channel ADC data. In fig. 3(e), Q ADC data is shown.

Fig. 4 is a schematic diagram of the synchronous timing of the I-path ASK modulation signal and the Q-path ASK modulation signal in one embodiment. The ADC sampling clocks of the I path and the Q path are inverted 6.78MHz clocks, and 4-bit data of the I path and the Q path are synchronized to a 27.12MHz digital clock domain before digital signal processing. The following embodiments are all described by taking the case where the I path and the Q path are synchronized.

In one embodiment, the ASK baseband envelope signal contains a dc component signal. The dc component in the digital circuit is the mean of the baseband envelope signal. Removing the dc component means subtracting the average value from the level value of the baseband envelope signal, so that the high level of the baseband envelope signal is in the positive integer domain and the low level is in the negative integer domain. Therefore, the baseband envelope signal from which the dc component signal is removed can determine baseband data.

And within one symbol period, three bit types are to be identified: a valid data bit, an end bit (held low for one symbol period), and a collision bit (high for one symbol period). FIG. 5 is a diagram illustrating a waveform of a bit pattern in one embodiment. Fig. 5(a) shows waveforms of valid data bits. Fig. 5(b) shows a waveform of the end bit. Fig. 5(c) shows waveforms of collision bits.

Fig. 6 is a timing diagram illustrating the removal of the dc component signal according to an embodiment. Fig. 6(a) shows a baseband envelope signal, and the 1bit represents the baseband envelope signal of the first period, and so on. Fig. 6(b) shows the baseband envelope signal delayed by one symbol period. Fig. 6(c) is a level average of the baseband envelope signal. Fig. 6(d) shows the signal after removal of the dc component.

The working principle is as follows:

since the average value of the bits needs to be calculated in advance, the baseband envelope signal needs to be delayed by one symbol period (i.e. 16 sampling periods), and meanwhile, the baseband signal listening does not destroy the integrity of the baseband envelope signal.

When in the signal listening phase, the 1bit mean value (fig. 6(c)) can be calculated from the baseband envelope signal (fig. 6(a)) by a 16-point sliding filter. Wherein, the mean value of the 1bit is the direct current component of the 1 bit. When the 1bit direct current component is removed, the 1bit signal of the baseband envelope signal delayed by one code element period is subtracted by the 1bit signal of the 1bit signal, and the 1bit signal without the direct current component signal can be obtained. While removing the dc component of the 1bit signal, the 2bit dc component is calculated in advance from the baseband envelope signal (fig. 6(a)), and so on for the other bits.

If the end bit and the collision bit are subjected to the de-direct current processing by adopting the method, the de-direct current end bit and the collision bit fluctuate around zero. Fig. 7 is a timing diagram illustrating the removal of the dc component signal in another embodiment. As can be seen from fig. 7, if the end bit and the collision bit are dc-processed in the manner shown in fig. 6, both the dc-processed end bit and the collision bit fluctuate around 0. Therefore, the receiver cannot recognize the end bit and the collision bit. Therefore, the technical scheme in each embodiment of the application is provided.

In an embodiment, as shown in fig. 8, a schematic flowchart of a signal demodulation method in an embodiment is shown, where the method is applied to a receiver as an example, the method includes:

step 802, obtaining a first baseband envelope signal in a first symbol period; the logic level of the first baseband envelope signal is a normal bit level.

Wherein the first symbol period may refer to a period currently processed by the receiver. For example, the first symbol period includes, but is not limited to, the first period, the second period, and so on.

The first baseband envelope signal may be a first ASK baseband envelope signal. The first ASK baseband envelope signal may specifically be obtained after the first ASK modulation signal is rectified and filtered. The first baseband envelope signal may be obtained from a signal received via an ISO1443A or ISO15693 communication protocol. The first baseband envelope signal may be the signal of the first envelope protrusion or the ASK baseband envelope signal after the first envelope protrusion. The first baseband envelope signal may be a digital signal. Specifically, a receiver acquires an I path ASK modulation signal and a Q path ASK modulation signal which have synchronized time sequence; determining the signal intensity of the ASK modulation signal of the I path and the signal intensity of the ASK modulation signal of the Q path; determining an ASK modulation signal with stronger signal intensity from the signal intensity of the ASK modulation signal of the I path and the signal intensity of the ASK modulation signal of the Q path; and obtaining a first baseband envelope signal in a first code element period according to the ASK modulation signal with stronger signal strength.

In this embodiment, as shown in fig. 9, a waveform diagram of sampling a subcarrier in one embodiment is shown. The white dots in fig. 9 indicate the sampling timing of the I-path, and the black dots indicate the sampling timing of the Q-path. The analog front end samples the subcarriers, and because the sampling points are random, the sampling result has four possibilities.

As shown in fig. 9(a), the I-path samples the 848KHz modulated carrier, and the Q-path non-modulated carrier. Then the signal with stronger signal strength is the I-path modulated signal. Accordingly, the first baseband signal in the first symbol period is obtained from the I-path modulated signal.

As shown in fig. 9(b), the I path has no modulated carrier, and the Q path samples the 848KHz modulated carrier. Then the stronger signal is the Q-path modulated signal. Accordingly, the first baseband signal in the first symbol period is obtained from the Q-path modulated signal.

As shown in fig. 9(c), both the I and Q paths have 848KHz modulated carriers, and the signal strength of the I path modulated signal > the signal strength of the Q path modulated signal. Accordingly, the first baseband signal in the first symbol period is obtained from the I-path modulated signal.

As shown in fig. 9(d), both the I and Q paths have 848KHz modulated carriers, and the signal strength of the I path modulated signal is less than that of the Q path modulated signal. Accordingly, the first baseband signal in the first symbol period is obtained from the Q-path modulated signal.

Step 804, acquiring a second baseband envelope signal in a second symbol period; the second symbol period is a backward period of the first symbol period.

Specifically, the second symbol period is a backward period of the first symbol period. Specifically, the second symbol period may be the next period of the first symbol period. The second baseband envelope signal may be a second ASK baseband envelope signal. The second ASK baseband envelope signal may specifically be obtained after rectification and filtering of the second ASK modulated signal. The second baseband envelope signal may be obtained from a signal received via an ISO1443A or ISO15693 communication protocol.

Similarly, the receiver derives a second baseband envelope signal in a second symbol period from the ASK modulated signal having the stronger signal strength. The second baseband envelope signal within the second symbol period may be a digital signal.

Step 806, determining a level average of the first baseband envelope signal to obtain a first average.

Specifically, the receiver integrates and averages the first baseband envelope signal to obtain a first average value.

And 808, performing direct current removal processing on the second baseband envelope signal according to the first average value to obtain a reference second signal.

Wherein, the DC removal processing is to remove the DC component signal. The reference second signal is specifically a second baseband envelope signal after dc removal by the first average value. The baseband envelope signal contains a direct current component, the direct current component is an average value of the baseband envelope signal, and the removal of the direct current component means that the average value is subtracted from the baseband envelope signal, so that the high level of the baseband signal is in a positive integer domain, and the low level of the baseband signal is in a negative integer domain. Therefore, the baseband envelope signal from which the dc component is removed can determine baseband data.

Specifically, the receiver subtracts the first mean value from the signal level values in the second baseband signal to obtain the reference second signal.

In one embodiment, as shown in FIG. 10, a timing diagram of the end bit signal with the DC component removed in one embodiment is shown. Fig. 10(a) shows the acquired baseband envelope signal. Fig. 10(b) shows the baseband envelope signal delayed by one symbol period. Fig. 10(c) is a bit average value of the baseband envelope signal of fig. 10 (a). The bit average is the average of the levels in one symbol period. Fig. 10(d) is a bit average value of the baseband envelope signal after a processing delay of one symbol period. Fig. 10(e) shows the baseband envelope signal delayed by one symbol period after the dc component signal is removed. That is, fig. 10(e) is a result of subtracting the signal of fig. 10(d) from the signal of fig. 10 (b). For example, the nth bit signal in FIG. 10(e) is the nth bit signal in FIG. 10(b) minus the bit average of the (n-1) th bit in FIG. 10 (d). The other signals are analogized. The nth signal can be regarded as a second baseband envelope signal, the (n-1) th signal is a first baseband envelope signal, and the (n-1) th average value is a first average value. Then, at the end bit, the average value of the nth bit is adopted to perform the dc removal processing, and then the logic level is judged, so that the end bit can be judged.

In one embodiment, as shown in FIG. 11, a timing diagram of the collision bit signal with the DC component removed in one embodiment is shown. Fig. 11(a) shows the acquired baseband envelope signal. Fig. 11(b) shows a baseband envelope signal delayed by one symbol period in processing. Fig. 11(c) is a bit average of the baseband envelope signal of fig. 11 (a). The bit average is the average of the levels in one symbol period. Fig. 11(d) is a bit average value of the baseband envelope signal after a processing delay of one symbol period. Fig. 11(e) shows the baseband envelope signal delayed by one symbol period after the dc component signal is removed. That is, fig. 11(e) is a result of subtracting the signal of fig. 11(d) from the signal of fig. 11 (b). For example, the (n-a +1) th bit signal in FIG. 11(e) is the (n-a +1) th bit signal in FIG. 11(b) minus the bit average of the (n-a) th bit in FIG. 11 (d). The other signals are analogized. The (n-a +1) th bit signal can be regarded as a second baseband envelope signal, the (n-a) th bit is a first baseband envelope signal, and the (n-a) th bit average value is a first average value. Then, when the bits collide, the mean value of the (n-a +1) th bit is adopted to perform the dc removal processing, and then the logic level is determined, so that the colliding bits can be determined.

Step 810 determines a logic level of the second baseband envelope signal based on the reference second signal.

Wherein the logic level is 0 or 1. Alternatively, the logic level is high or low. The logic levels within a symbol period include a normal bit level and an abnormal bit level. Both 0 and 1 are included in the normal bit level. The abnormal bit level includes a collision bit level and an end bit level. The collision bit level includes only 1 or only high. Only 0 or only low levels are included in the end bit level.

Specifically, the receiver integrates every half symbol period in the reference second signal, obtaining every half integrated value; the logic level of the second envelope signal is determined based on the positive and negative of each half-integral value. For example, when the half-integrated value is positive, it is determined that 1 is included in the logic level of the second baseband envelope signal; when the half-integrated value is negative, it is determined that 0 is included in the logic level of the second baseband envelope signal. Alternatively, the receiver may determine the logic level of the second envelope signal based on the magnitude of each half of the integrated value. When an abnormal bit logic level is detected, demodulation is ended.

In the signal demodulation method in this embodiment, because of the existence of the direct current component, the decision threshold according to which the logic level is determined is particularly important, and because the logic level of the first baseband envelope signal is the normal bit level, the first average value is obtained by determining the average value of the level of the first baseband envelope signal, and the dc removal processing is performed on the second baseband envelope signal according to the first average value, so as to obtain the reference second signal, that is, the dc removal processing is performed on the average value of the signal based on the normal bit level, so that the logic level of the second baseband envelope signal can be determined, the abnormal bit level is determined, and the accuracy of logic level determination is improved.

In one embodiment, determining the logic level of the second baseband envelope signal from the reference second signal comprises: integrating the reference second signal to obtain a second integral value; when the second integrated value satisfies the abnormal bit determination condition, the logic level of the second baseband envelope signal is determined to be an abnormal bit level.

Wherein the exception bits include a collision bit and an end bit. The abnormal bit determination condition is used for indicating that the logic levels in the symbol period are both 1 or both 0. The collision bits, i.e. the logic levels in the symbol period are all 1, as shown in fig. 5 (c). The end bits are all 0 logic levels in the symbol period, as shown in fig. 5 (b).

Specifically, the receiver integrates the reference second signal to obtain a second integrated value; determining a logic level of the second baseband envelope signal as an abnormal bit level when the second integrated value satisfies an abnormal bit determination condition; wherein the abnormal bit determination condition includes that the second integration value is not within a preset integration range. For example, the preset integration value range refers to a range corresponding to a normal bit level. When an abnormal bit level is detected, demodulation is ended.

In this embodiment, the receiver integrates every half symbol period in the reference second signal to obtain two second integral values; when the two second integrated values satisfy an abnormal bit determination condition, determining the logic level of the second baseband envelope signal as an abnormal bit level; wherein the abnormal bit determination condition includes both of the two integrated values being positive values or both of the two integrated values being negative values, or the like.

In this embodiment, the reference second signal is integrated to obtain a second integral value; when the second integrated value satisfies the abnormal bit determination condition, the logic level of the second baseband inclusion signal is determined to be the abnormal bit level, the abnormal bit level can be determined without increasing the cost, and the accuracy of logic level determination is improved.

In one embodiment, determining the logic level of the second baseband envelope signal from the reference second signal further comprises: determining a level average value of a second baseband envelope signal to obtain a second average value; when the second integral value does not meet the abnormal bit determination condition, performing direct current removal processing on the second baseband envelope signal according to a second average value to obtain a target second signal; the normal bit level of the second baseband envelope signal is determined from the target second signal.

The second average value is a level average value obtained by integrating and averaging the second baseband envelope signal.

Specifically, the receiver integrates and averages the second baseband envelope signal, determines a level average of the second baseband envelope signal, and obtains a second average. And when the second integral value does not meet the abnormal bit determination condition, indicating that the second baseband envelope signal is not an abnormal bit, performing direct current removal processing on the second baseband envelope signal according to a second average value to obtain a target second signal. The receiver may integrate the target second signal for each half symbol period and determine the normal bit level of the second baseband envelope signal based on the positive and negative of the integration result.

In this embodiment, the second average value of the second baseband envelope signal itself is used to perform dc removal processing, and the normal bit level is determined, so that the accuracy of logic level determination can be improved.

In one embodiment, determining a level average of the second baseband envelope signal, obtaining the second average, comprises: performing direct current removing processing on the first baseband envelope signal according to the first average value to obtain a direct current removed first baseband envelope signal; carrying out bit synchronization on the first baseband envelope signal without direct current to obtain a first bit synchronization signal; and determining the level average value of the second baseband envelope signal according to the first bit synchronous signal to obtain a second average value.

The bit synchronization is a process of digital signal code element time alignment, and in the digital transmission, a first bit synchronization signal is extracted from an information code stream, and a timing extraction process of the information code element is identified by means of the first bit synchronization signal. Bit synchronization is the basis for a correct sampling decision.

Specifically, the receiver performs dc removal processing on the first baseband envelope signal according to the first average value to obtain a dc-removed first baseband envelope signal. The receiver may perform bit synchronization on the first baseband envelope signal without direct current through a filter circuit or an in-phase quadrature integration type bit synchronization circuit, and the like, to obtain a first bit synchronization signal. And the receiver integrates the second baseband envelope signal according to the first bit synchronization signal and calculates a level average value to obtain a second average value.

In this embodiment, the dc removal processing is performed on the first baseband envelope signal according to the first average value, so as to obtain a dc-removed first baseband envelope signal, obtain a first bit synchronization signal corresponding to the first baseband envelope signal, and correct the second baseband envelope signal through the first bit synchronization signal, so that the obtained second average value is more accurate.

In one embodiment, as shown in fig. 12, a schematic block diagram of an in-phase quadrature integration type bit synchronization circuit in one embodiment is shown. In order to enhance the anti-interference performance of the bit synchronization circuit and the decision output, the embodiment of the application adopts an in-phase quadrature integration type bit synchronization circuit. The integral bit synchronization circuit applies the principle of matched filtering to optimally detect the baseband envelope signal without the direct current component, the influence of interference is greatly weakened, and the extracted bit synchronization signal has better anti-interference performance. The integral bit synchronization circuit also meets the design requirement of judging the baseband envelope at the moment of the maximum signal-to-noise ratio, ensures that each bit of data is judged once, and improves the judgment accuracy.

The clock conversion circuit generates two paths of mutually orthogonal bidirectional clock signals, namely clk _ d1 and clk _ d2, wherein the duty ratios of the two paths of signals are 1: and 3, the high-level pulse width is 1 crystal oscillator clock period.

The in-phase integration and sampling holding circuit is used for accumulating the envelope signals with the DC components removed in the half-symbol period and outputting an accumulated value at the end of the half-symbol period. And when the accumulated value is greater than 0, judging the half code element to be at a high level, otherwise, judging the half code element to be at a low level.

The phase detector consists of a transition edge detection circuit, an exclusive-or gate circuit and an and gate (pd _ bef and pd _ aft) circuit. Pd _ bef outputs a high pulse when the bit sync signal is advanced, otherwise pd _ aft outputs a high pulse.

The controller is composed of flip-flops (pd _ before and pd _ after) and gates (gate _ open and gate _ close), so as to complete the function of 'adding and deducting' pulse, and further realize the purpose of adjusting the bit synchronization signal output by the frequency divider.

Fig. 13 is a timing chart of a determination output of the in-phase quadrature integration type bit synchronizing circuit in one embodiment. Fig. 13(a) shows a baseband envelope signal from which a dc component signal is removed. Fig. 13(b) shows a bit synchronization signal. Fig. 13(c) is half symbol period integration. Fig. 13(d) shows a baseband signal obtained by demodulation. And when the integral value in the half code element period is greater than 0, judging the half code element to be at a high level, otherwise, judging the half code element to be at a low level. Since the signal is a return-to-zero code, one decoded sample pulse is generated at three-quarters of the symbol period. And sampling the baseband signal at the decoding sampling pulse, if the baseband signal is at a low level, decoding the bit of the baseband data to be 0, otherwise, decoding the bit of the baseband data to be 1.

In one embodiment, obtaining a first baseband envelope signal in a first symbol period comprises: acquiring a modulation signal in a first code element period; rectifying the modulation signal in the first code element period to obtain a double frequency modulation carrier signal; the double frequency modulated carrier signal is filtered to obtain a first baseband envelope signal within a first symbol period.

The modulation signal in the first symbol period is a digital signal, so that the double-frequency modulation carrier signal and the first baseband envelope signal in the first period are both digital signals.

Specifically, the receiver acquires the modulated signal in the first symbol period from the modulated signal in which the signal is strong. The receiver inverts the negative half cycle of the modulated signal of the first symbol period to the positive half cycle to obtain a double frequency modulated carrier signal. Fig. 14 is a schematic diagram of waveforms for rectifying a modulation signal in one embodiment. Fig. 14 includes (a) a modulated signal and (b) a double frequency modulated carrier signal. The negative half cycle of the ASK modulation signal corresponds to 0-7 of the ADC, and the positive half cycle corresponds to 8-15 of the ADC. The ADC values are converted to values corresponding to the positive and negative half cycles of the ASK modulated signal, as shown in table 1. And rectifying the ASK modulation carrier by taking the highest value of the ADC as a sign bit.

The receiver obtains a first baseband envelope signal in a first symbol period by low pass filtering a double frequency modulated carrier signal. Fig. 15 is a waveform diagram of low-pass filtering in one embodiment. Fig. 15 includes (a) a double frequency modulated carrier signal and (b) a baseband envelope signal.

In this embodiment, the modulation signal in the first symbol period is obtained, and the modulation signal in the first symbol is rectified and then filtered to obtain the first baseband envelope signal in the first symbol period, so that the operation of the circuit can be reduced and the operation load of the circuit can be reduced without changing the sample rate of the signal.

In one embodiment, filtering a double frequency modulated carrier signal to obtain a first baseband envelope signal in a first symbol period comprises: filtering the double frequency modulation carrier signal through a cascade integral comb filter to obtain a first baseband envelope signal in a first code element period.

The Cascaded integrator-comb (CIC) filter does not need a multiplier and a storage unit, and occupies less resources when processing high-frequency signals. The digital channel filter structure of the 2-order CIC filter is adopted in the embodiment of the application.

In particular, the cascaded integrator-comb filter comprises one or more pairs of integrator-comb filters, wherein the pairs of integrator-comb filters are separated by a decimator having a decimation factor M. Fig. 16 is a schematic structural diagram of a second-order CIC filter in one embodiment. Wherein Z^-1Is a comb filterAnd M is an extractor.

Common communication protocols for receivers include ISO14443A and ISO 15693. It will be appreciated that common general protocols may also include other communication protocols.

Since ISO14443A and ISO15693 have different modulation carrier frequencies and code rates, the frequency to be filtered by CIC for different communication protocols is also different. The ASK modulated carrier frequency and code rate of ISO14443A card and ISO15693 card are shown in Table 2.

TABLE 2ASK (amplitude Shift keying) modulation Carrier frequency and code Rate

When demodulating the ASK modulated signal of the ISO14443A card, the CIC digital low-pass filter needs to satisfy the following condition:

the 1.69MHz modulated carrier signal is filtered, leaving a 106KHz baseband signal.

When demodulating the ASK modulated signal of the ISO15693 card, the CIC digital low-pass filter needs to satisfy the following conditions:

the 847.5KHz modulated carrier signal is filtered, and signals with frequencies below 53KHz are reserved.

By analyzing the amplitude-frequency characteristic of the CIC filter extracted by 2-order and 4-time, the signals with the frequency near 1.69MHz are greatly attenuated, so that the effect of filtering the 1.69MHz signals can be achieved; and the signal at 106KHz is extremely attenuated, so as to achieve the purpose of retaining the signal at 106 KHz. Therefore, when demodulating the ASK modulation signal of the ISO14443A card, a2 nd order 4-time decimation CIC filter is suitable.

By analyzing the amplitude-frequency characteristic of the CIC filter extracted by 2-order and 8-time, the signals with the frequency near 847.5KHz are greatly attenuated, so that the effect of filtering 847.5KHz signals can be achieved; and the signal below 53KHz is attenuated very little, so that the aim of retaining the signal below 53KHz is fulfilled. Therefore, when demodulating ASK modulation signals of ISO15693 cards, a 2-order 8-time decimation CIC low-pass filter is suitable.

The main effect of the cascaded integrator-comb filter is as follows:

1. the out-of-band quantization noise is filtered out. After digital rectification, a double frequency modulation carrier signal is obtained. The channel filter is required to filter the double frequency modulated carrier signal and to filter out-of-band noise signals.

2. The sampling frequency is reduced. After digital rectification, the signal retains the sampling frequency of 6.78MHz, redundant data exists, and therefore the signal needs to be subjected to down-sampling processing.

3. Anti-aliasing. In the process of extracting the rectified signal, the quantization noise in the frequency band is also extracted, so that a cascaded integrator-comb filter is needed to perform anti-aliasing processing on the signal.

In this embodiment, the first baseband envelope signal in the first symbol period is obtained by filtering the double-frequency modulated carrier signal through the cascaded integrator-comb filter, so that out-of-band quantization noise can be filtered, the sampling frequency can be reduced, anti-aliasing processing can be performed on the signal, and the accuracy of the obtained first baseband envelope signal can be improved.

In one embodiment, filtering a double frequency modulated carrier signal through a cascaded integrator-comb filter to obtain a first baseband envelope signal in a first symbol period, comprises: filtering the double-frequency modulation carrier signal through a cascade integral comb filter to obtain a filtered double-frequency modulation carrier signal; and when the communication protocol adopted by the modulation signal is a preset communication protocol, down-sampling the filtered double-frequency modulation carrier signal through a down-sampling filter to obtain a first baseband envelope signal in a first code element period.

The preset communication protocol comprises a communication protocol of which the number of samples exceeds the preset number of samples after filtering. Advantageously, the preset number of samples may be 8. As can be seen from the analysis of table 3, the number of samples after filtering in ISO14443A is 8, and no further down-sampling is required. ISO15693 filtered signals need to be down-sampled. And the 1-order and 8-time decimation CIC filter is adopted to down-sample the signal with the code rate of ISO15693 card 6.62, and the 1-order and 2-time decimation CIC filter is adopted to down-sample the signal with the code rate of ISO15693 card 26.48.

TABLE 3 number of samples for half symbol period after digital low-pass filtering

In the digital signal processing process of the DC removal circuit and the integral bit synchronization circuit, only 8 sampling numbers are needed in a half code element period, and in order to reduce the overhead and power consumption of a chip, the filtered signal is subjected to down-sampling, so that the effect of corresponding to 8 sampling numbers in the half code element period is achieved.

In this embodiment, because the sampling frequency of some filtered double frequency modulated carrier signals is higher, it is necessary to determine whether downsampling is needed through a communication protocol used by the modulated signals, and when the communication protocol used by the modulated signals is a preset communication protocol, downsampling is performed through a downsampling filter, so that overhead and power consumption of a chip can be reduced.

In one embodiment, obtaining a first baseband envelope signal in a first symbol period comprises: monitoring a baseband envelope signal; when a first envelope protrusion is detected, a first baseband envelope signal within a first symbol period is obtained.

Wherein the first baseband envelope signal in the first symbol period may be the baseband envelope signal of the first symbol period in the signal.

Specifically, when the tag does not transmit valid data, the signal is in a low-level state. Monitoring a baseband envelope signal by a receiver; when the first envelope protrusion is detected, processing of the signal is started, obtaining a first baseband envelope signal in a first symbol period.

Fig. 17 is a schematic diagram of a waveform of a baseband envelope signal in one embodiment. The signal comprises a constant carrier signal and a signal enveloping the protrusions. The constant carrier signal has no envelope protrusion. Thus, by detecting the first envelope protrusion, the first baseband envelope signal in the first symbol period can be located.

In this embodiment, by detecting the baseband envelope signal, when the first envelope protrusion is detected, the signal processing is started, and the signal can be correctly processed.

In one embodiment, a demodulation method includes:

step (a1), a modulated signal in a first symbol period is acquired.

And (a2) rectifying the modulation signal in the first code element period to obtain a double frequency modulation carrier signal.

And (a3) filtering the double frequency modulation carrier signal through a cascade integrator comb filter to obtain a filtered double frequency modulation carrier signal.

And (a4), when the communication protocol adopted by the modulation signal is a preset communication protocol, down-sampling the filtered double-frequency modulation carrier signal through a down-sampling filter to obtain a first baseband envelope signal in a first symbol period.

Step (a5) of acquiring a first baseband envelope signal in a first symbol period.

And (a6) acquiring a second baseband envelope signal in a second symbol period. The second symbol period is a backward period of the first symbol period.

And (a7) determining a level average value of the first baseband envelope signal to obtain a first average value.

And (a8) performing dc removal processing on the second baseband envelope signal according to the first average value to obtain a reference second signal.

And (a9) integrating the reference second signal to obtain a second integrated value.

And a step (a10) of determining the logic level of the second baseband envelope signal as an abnormal bit level when the second integrated value satisfies the abnormal bit determination condition.

And (a11), performing direct current removing processing on the first baseband envelope signal according to the first average value to obtain a direct current removed first baseband envelope signal.

And (a12) performing bit synchronization on the first baseband envelope signal subjected to the direct current removal to obtain a first bit synchronization signal.

And (a13) determining a level mean value of the second baseband envelope signal according to the first bit synchronization signal to obtain a second mean value.

And (a14) when the second integral value does not meet the abnormal bit determination condition, performing dc removal processing on the second baseband envelope signal according to the second average value to obtain a target second signal.

And (a15) determining a normal bit level of the second baseband envelope signal based on the target second signal.

In the embodiment, the filtering is performed by the cascade integration comb filter, so that subcarrier signals can be filtered, the down-sampling and the anti-aliasing can be performed, the average value is calculated after the down-sampling, and the consumption of resources can be reduced; the abnormal bit level and the normal bit level can be judged by averaging according to the code element period, and the judgment accuracy of the logic level is improved.

The steps (a1) to (a15) may be implemented by hardware, by an FPGA (Field Programmable Gate Array), or by circuit simulation performed by a computer.

It should be understood that, although the steps in the flowchart of fig. 8 described above are sequentially displayed as indicated by arrows and the steps of the step (a1) to the step (a15) are sequentially displayed as indicated by reference numerals, the steps are not necessarily sequentially performed in the order indicated by the arrows or numerals. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 8 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or in alternation with other steps or at least a portion of the other steps or stages.

In one embodiment, as shown in fig. 18, a block diagram of a signal demodulation apparatus in one embodiment is shown. Fig. 18 provides a signal demodulation apparatus, which may be a part of a computer device using a software module or a hardware module, or a combination of the two, and specifically includes a baseband envelope signal monitoring module 1802, a dc removal module 1804, and a symbol determination module 1806 connected in sequence, where:

a baseband envelope signal monitoring module 1802, configured to obtain a first baseband envelope signal in a first symbol period;

a baseband envelope signal monitoring module 1802, further configured to obtain a second baseband envelope signal in a second symbol period; the second symbol period is a backward period of the first symbol period;

a dc removal module 1804, configured to determine a level mean value of the first baseband envelope signal, to obtain a first mean value;

the dc removal module 1804 is further configured to perform dc removal processing on the second baseband envelope signal according to the first average value to obtain a reference second signal;

a symbol decision module 1806, configured to determine a logic level of the second baseband envelope signal according to the reference second signal.

In this embodiment, because the presence of the dc component, the decision threshold according to when determining the logic level is particularly important, and because the logic level of the first baseband envelope signal is the normal bit level, the reference second signal is obtained by determining the level average value of the first baseband envelope signal to obtain the first average value, and performing dc removal processing on the second baseband envelope signal according to the first average value to obtain the reference second signal, that is, performing dc removal processing on the average value of the signal based on the normal bit level, so that the logic level of the second baseband envelope signal can be determined, the abnormal bit level is determined, and the decision accuracy of the logic level is improved.

In one embodiment, the signal demodulation apparatus further includes an integration bit synchronization module. The integration bit synchronization module is used for integrating the reference second signal to obtain an integration value; a symbol decision module 1806, configured to determine that the logic level of the second baseband envelope signal is an abnormal bit level when the integrated value satisfies the abnormal bit determination condition.

In one embodiment, the dc removal module 1804 is further configured to determine a level average of the second baseband envelope signal, to obtain a second average;

when the integral value does not meet the abnormal bit determination condition, performing direct current removal processing on the second baseband envelope signal according to a second average value to obtain a target second signal;

the symbol determining module 1806 is further configured to determine a normal bit level of the second baseband envelope signal according to the signal level value of the target second signal.

In one embodiment, the dc removal module 1804 is further configured to perform dc removal processing on the first baseband envelope signal according to the first average value to obtain a dc-removed first baseband envelope signal;

the integral bit synchronization module is also used for carrying out bit synchronization on the first baseband envelope signal without direct current to obtain a first bit synchronization signal;

the dc removing module 1804 is further configured to determine a level mean of the second baseband envelope signal according to the first bit synchronization signal, so as to obtain a second mean.

In one embodiment, the signal demodulation device further comprises a digital rectification module and a digital channel filtering module; the digital rectification module is used for acquiring a modulation signal in a first code element period; rectifying the modulation signal in the first code element period to obtain a double frequency modulation carrier signal; and the digital channel filtering module is used for filtering the double frequency modulation carrier signal to obtain a first baseband envelope signal in a first code element period.

In one embodiment, the baseband envelope signal listening module 1802 is further configured to monitor the baseband envelope signal; when a first envelope protrusion is detected, a first baseband envelope signal within a first symbol period is obtained.

In one embodiment, the signal demodulation apparatus may further include a signal synchronization module, a digital rectification module, and a digital notification filtering module, which are connected in sequence, wherein the digital channel filtering module is connected to the baseband envelope signal monitoring module. Fig. 19 is a block diagram showing a structure of a signal demodulating apparatus according to another embodiment. Fig. 19 may be connected with the block diagram of fig. 1. Fig. 19 includes an I/Q two-path signal synchronization module, a digital rectification module, a digital channel filtering module, a baseband envelope signal monitoring module, a dc removal module, an integral bit synchronization module, and a symbol determination module. The digital signals processed by the ASK digital demodulation algorithm of the non-contact I C card receiver comprise an I-path ASK modulation signal and a Q-path ASK modulation signal, wherein the I-path ASK modulation signal and the Q-path ASK modulation signal are ASK digital modulation signals with 4 bits and different signal intensities. The signal demodulation device comprises the following processing procedures:

and the signal synchronization module is used for synchronizing the I path modulation signal and the Q path modulation signal to a digital clock domain.

And the channel selection module is used for selecting one path from the I path modulation signal and the Q path modulation signal for demodulation. The signal with stronger signal strength in the I-path modulation signal and the Q-path modulation signal can be selected through a configuration register or selected.

And the digital rectification module is used for rectifying the selected modulation signal to obtain a double-frequency modulation carrier signal.

And the digital channel filtering module is used for filtering and down-sampling the double frequency modulation carrier signal to obtain a baseband envelope signal.

And the baseband envelope signal monitoring module is used for monitoring the baseband signal and detecting the position of the first envelope protrusion of the baseband. Therefore, if the envelope protrusion is detected, it is determined that the baseband signal is detected, and the first envelope protrusion is used as a start bit of the bit synchronization. If no envelope protrusion is detected, the envelope protrusion continues to be detected.

Fig. 20 is a flowchart illustrating a signal demodulation method according to another embodiment. The following description is made with reference to fig. 19 and 20.

A dc removal module, configured to determine a first mean value of the first baseband envelope signal when receiving the first baseband envelope signal in the first symbol period; and performing direct current removal processing on the first baseband envelope signal according to the first average value to obtain a target first signal.

And the integration bit synchronization module is used for integrating each half code element in the target first signal to obtain a first integration value.

And the code element judging module is used for judging whether the logic level is 0 or 1 according to the first integral value so as to obtain a baseband signal. When the first integral value is a positive number, the half code element is at a high level; when the first integrated value is negative, the half symbol is low.

And the integral bit synchronization module is used for determining a first bit synchronization signal of the target first signal.

And the direct current removing module is further used for performing direct current removing processing on the second baseband envelope signal according to the first average value when the second baseband envelope signal in the second symbol period is received, so as to obtain a reference second signal.

And the integration bit synchronization module is also used for integrating each half code element in the reference second signal to obtain a second integration value.

And the code element judging module is also used for judging the abnormal bit level according to the second integral value.

The direct current removing module is further used for determining a second average value of the second baseband envelope signal according to the first bit synchronization signal; and performing direct current removal processing on the second baseband envelope signal according to the second average value to obtain a target second signal.

And the integration bit synchronization module is used for integrating each half code element in the target second signal when the second baseband envelope signal is not at an abnormal bit level, namely the second integration value does not meet the abnormal bit determination condition.

And the code element judging module is used for judging whether the normal bit level is 0 or 1 according to the integration result obtained by integrating each half code element in the target second signal so as to obtain the baseband signal.

The integral bit synchronization module is also used for inputting a target second signal into the in-phase quadrature integral bit synchronization circuit to obtain a second bit synchronization signal; the second bit synchronization signal is used for processing a third baseband envelope signal in a third symbol period.

In one embodiment, as shown in fig. 21, a waveform diagram of digital signal demodulation in one embodiment is shown. The figure includes (a) ASK modulated signal, (b) double frequency modulated carrier signal, (c) low pass filtered signal, (d) down sampled signal, (e) dc removed baseband envelope signal, (f) bit sync signal and finally decoded (g) baseband signal.

In this embodiment, whether the current baseband envelope signal is a collision bit level is determined by the mean value of the previous baseband envelope signal, and when the abnormal bit determination condition is not satisfied, that is, when the current baseband envelope signal is not the abnormal bit level, the normal bit level is determined again, so that it can be ensured that the previous baseband envelope signal is the normal bit level, the signal is circularly determined until the collision bit is finally determined and then output, demodulation is finished, the resource occupation can be reduced, and the determination accuracy of the logic level can be improved.

For the specific limitations of the receiver, reference may be made to the above limitations of the signal demodulation method, which are not described herein again. The various modules in the receiver described above may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, a receiver is provided that includes the structures of the apparatus embodiments described above. In conjunction with the structure of fig. 1, the receiver may further include an integrator, a band-pass filter, a gain amplifier, and an ADC, which are connected in sequence. The receiver may specifically comprise a card reader or the like.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.

In one embodiment, a computer program product or computer program is provided that includes computer instructions stored in a computer-readable storage medium. The computer instructions are read by a processor of the computer device from the computer-readable storage medium, and the computer instructions are executed by the processor to cause the computer device to perform the steps in the above-mentioned method embodiments.

It will be understood by those skilled in the art that all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a non-volatile computer-readable storage medium, and which, when executed, may include the processes of the above embodiments of the methods. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. A method for demodulating a signal, the method comprising:

2. The method of claim 1, wherein said determining a logic level of the second baseband envelope signal from the reference second signal comprises:

integrating the reference second signal to obtain a second integral value;

determining that the logic level of the second baseband envelope signal is an abnormal bit level when the second integrated value satisfies an abnormal bit determination condition.

3. The method of claim 2, wherein determining the logic level of the second baseband envelope signal from the reference second signal further comprises:

determining a level mean value of the second baseband envelope signal to obtain a second mean value;

when the second integral value does not meet the abnormal bit determination condition, performing direct current removal processing on the second baseband envelope signal according to the second average value to obtain a target second signal;

determining a normal bit level of the second baseband envelope signal from the target second signal.

4. The method of claim 3, wherein determining the level average of the second baseband envelope signal and obtaining the second average comprises:

performing direct current removing processing on the first baseband envelope signal according to the first average value to obtain a direct current removed first baseband envelope signal;

carrying out bit synchronization on the first baseband envelope signal without the direct current to obtain a first bit synchronization signal;

and determining the level average value of the second baseband envelope signal according to the first bit synchronization signal to obtain a second average value.

5. The method of claim 1, wherein said obtaining the first baseband envelope signal in the first symbol period comprises:

acquiring a modulation signal in a first code element period;

rectifying the modulation signal in the first code element period to obtain a double frequency modulation carrier signal;

and filtering the double frequency modulation carrier signal to obtain a first baseband envelope signal in a first code element period.

6. The method of claim 5, wherein filtering the double frequency modulated carrier signal to obtain a first baseband envelope signal in a first symbol period comprises:

and filtering the double-frequency modulation carrier signal through a cascade integral comb filter to obtain a first baseband envelope signal in a first code element period.

7. The method of claim 6, wherein filtering the double frequency modulated carrier signal with a cascaded integrator-comb filter to obtain a first baseband envelope signal in a first symbol period comprises:

filtering the double-frequency modulation carrier signal through a cascade integral comb filter to obtain a filtered double-frequency modulation carrier signal;

8. A signal demodulation apparatus, characterized in that the apparatus comprises:

9. The apparatus of claim 8, wherein the signal demodulation apparatus further comprises an integration bit synchronization module;

the integration bit synchronization module is used for integrating the reference second signal to obtain an integration value;

and the code element judging module is used for determining that the logic level of the second baseband envelope signal is an abnormal bit level when the integrated value meets an abnormal bit determination condition.

10. The apparatus of claim 9, wherein the dc removal module is further configured to determine a level mean of the second baseband envelope signal, and obtain a second mean;

when the integral value does not meet the abnormal bit determination condition, performing direct current removal processing on the second baseband envelope signal according to the second average value to obtain a target second signal;

the symbol decision module is further configured to determine a normal bit level of the second baseband envelope signal according to the signal level value of the target second signal.

11. The apparatus according to claim 10, wherein the dc removal module is further configured to perform dc removal processing on the first baseband envelope signal according to the first average value to obtain a dc-removed first baseband envelope signal;

the integral bit synchronization module is further configured to perform bit synchronization on the first baseband envelope signal without direct current to obtain a first bit synchronization signal;

the dc removing module is further configured to determine a level mean value of the second baseband envelope signal according to the first bit synchronization signal, and obtain a second mean value.

12. A receiver, characterized in that it comprises a signal demodulation arrangement according to any one of claims 8 to 11.

13. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 7.