CN114123372A

CN114123372A - Charge and discharge switch circuit, charge and discharge control device, chip and battery management system

Info

Publication number: CN114123372A
Application number: CN202111007662.8A
Authority: CN
Inventors: 不公告发明人
Original assignee: Zhuhai Maiju Microelectronics Co Ltd
Current assignee: Zhuhai Maiju Microelectronics Co Ltd
Priority date: 2020-09-01
Filing date: 2021-08-30
Publication date: 2022-03-01
Also published as: CN219980445U; CN112398192A

Abstract

The present disclosure provides a charge and discharge switching circuit for controlling a charge current and/or a discharge current of a battery/cell, comprising: the MOS transistor comprises a first MOS transistor, a second MOS transistor and a switch, wherein the grid electrode of the first MOS transistor receives a first control signal so as to be conducted and cut off, the first MOS transistor is a low voltage-resistant MOS transistor, the second MOS transistor is a grid electrode of the second MOS transistor receives a second control signal so as to be conducted and cut off, the second MOS transistor is a high voltage-resistant MOS transistor, one end of the switch is connected with the grid electrode of the second MOS transistor, and the other end of the switch is connected with the source electrode of the second MOS transistor, so that when the first MOS transistor is cut off, the switch is conducted to enable the second MOS transistor to be cut off before the first MOS transistor is cut off or to be cut off while the first MOS transistor is cut off. A charging and discharging control device, a chip and a battery management system are also provided.

Description

Charge and discharge switch circuit, charge and discharge control device, chip and battery management system

Technical Field

The disclosure relates to a charge and discharge switch circuit, a charge and discharge control device, a chip and a battery management system.

Background

In the battery system, overcharge and overdischarge of the battery not only reduce the lifespan of the battery, but also cause safety accidents of explosion and fire when serious. The battery is, for example, a lithium battery pack or the like.

Fig. 1 shows a conventional overcurrent detection manner according to the prior art.

When the battery is normally discharged, the voltage of the control signal OD and OC port of the output of the driving unit is usually VDD, 5V or 15V, the control signals OD and OC are respectively connected to the gates (G) of the protection switch MOSFETs M1 and M2, when M1 and M2 operate in the linear region, the drains (D) and sources (S) of M1 and M2 are equivalently an on-resistance, and the on-resistance is R_on。

Discharge current I_dsgThe voltage of the P-terminal is higher when the voltage difference (I) between the P-terminal and the B-terminal is detected_dsg*R_on) When a certain limit value is reached, the voltage of the control signal OD is changed from VDD to VB- (voltage at terminal B), thereby turning off M1 and turning off the discharge path. Control signal OC may still remain at a potential such as VDD and M2 may still be in an on state.

Similarly, when the battery is normally charged, the gate voltages of M1 and M2 are VDD. The current flows from the B-terminal to the P-terminal, the voltage of the P-terminal is lower when the voltage difference (I) between the B-terminal and the P-terminal_chg*R_on) When a certain limit value is reached, the voltage of the control signal OC changes from, for example, VDD to VB-, turning off M2, cutting off the charging path. The control signal OD may still be held at a potential such as VDD and M1 may still be in an on state.

In the circuit configuration shown in fig. 1, the on-resistances R of M1 and M2 are set during normal charging_onIn the circuit of the battery and the external charger, when the system is charged, the power loss P caused by the on-resistance of M1 and M2_Loss＝I_chg*[2*R_on]²This power loss translates directly into heating of the system. Thus, the temperature rise Δ T — P due to heat loss of M2 of M1 during system charging is_Lossand/(C x m), wherein C is the specific heat coefficient of the system, and m is the mass of the system.

The safe operating temperature of a lithium battery system is usually around 45 ℃, so in order to control the system temperature rise due to the heat dissipation of the on-resistance of M1 and M2, the maximum value I of the charging current must be controlled_chg(max)＝P_Loss(max)/([2*R_on]²) Thus, the charging current is reduced, and the charging time of the system is inevitably prolonged.

Similarly, during discharge, the on-resistances R of M1 and M2_onIn series with the battery and the load (R)_Load) In the loop of (3), the heat loss P caused by the on-resistances of M1 and M2_Loss＝I_dsg*[2*R_on]². This power loss reduces the efficiency of battery energy utilization and also limits the maximum discharge current. P-T caused by heat loss of M1 and M2 when the system is discharged_Lossand/(C x m), wherein C is the specific heat coefficient of the system, and m is the mass of the system. The safe operating temperature of a lithium battery system is usually around 45 ℃, so in order to control the system temperature rise due to the heat dissipation of the on-resistance of M1 and M2, the maximum value I of the charging current must be controlled_dsg(max)＝P_Loss(max)/([2*R_on]²). This limits the maximum current that the battery system can output.

Disclosure of Invention

In order to solve one of the above technical problems, the present disclosure provides a charge and discharge switch circuit, a charge and discharge control device, a chip and a battery management system.

According to one aspect, a charge and discharge switching circuit for controlling a charging current and/or a discharging current of a battery/cell, comprises:

the grid electrode of the first MOS transistor receives a first control signal so as to conduct and cut off, the first MOS transistor is a low voltage-resistant MOS transistor, and the source electrode or the drain electrode of the first MOS transistor is connected with the battery side;

a gate of the second MOS transistor receives a second control signal to be turned on and off, the second MOS transistor is a high voltage-tolerant MOS transistor, a source or a drain of the second MOS transistor is connected to an external load or an external charger side, and a drain or a source of the second MOS transistor is connected to a drain or a source of the first MOS transistor; and

and one end of the switch is connected with the grid electrode of the second MOS transistor, and the other end of the switch is connected with the source electrode of the second MOS transistor, so that when the first MOS transistor is turned off, the switch is turned on to enable the second MOS transistor to be turned off before the first MOS transistor is turned off or to be turned off at the same time when the first MOS transistor is turned off.

According to at least one embodiment of the present disclosure, the first MOS transistor is a discharging MOS transistor and the first control signal is a discharging control signal, the second MOS transistor is a charging MOS transistor and the second control signal is a charging control signal, a source of the first MOS transistor is connected to a battery side, a source of the second MOS transistor is connected to an external load or an external charger side, and a drain of the second MOS transistor is connected to a drain of the second MOS transistor.

According to at least one embodiment of the present disclosure, the first MOS transistor is a charging MOS transistor and the first control signal is a discharging control signal, the second MOS transistor is a discharging MOS transistor and the second control signal is a discharging control signal, a drain of the first MOS transistor is connected to a battery side, a drain of the second MOS transistor is connected to an external load or an external charger side, and a source of the second MOS transistor is connected to a source of the second MOS transistor.

According to at least one embodiment of the present disclosure, the battery side is a low voltage side of a battery, the external load or external charger side is a low voltage side of the external load or a low voltage side of the external charger, or the battery side is a high voltage side of a battery, and the external load or external charger side is a high voltage side of the external load or a high voltage side of the external charger.

According to at least one embodiment of the present disclosure, a high voltage protection diode is connected between the source and the drain of the first MOS transistor.

According to at least one embodiment of the present disclosure, an on-resistance of the first MOS transistor is smaller than an on-resistance of the second MOS transistor.

According to at least one embodiment of the present disclosure, the first MOS transistor and the second MOS transistor are NMOS transistors.

According to at least one embodiment of the present disclosure, the switch further includes a second resistor, the switch is a switch NMOS transistor, one end of the second resistor is connected to a gate of the switch NMOS transistor and the other end of the second resistor is connected to a source of the switch NMOS transistor, the gate of the switch NMOS transistor is connected to a current signal, a drain of the switch NMOS transistor is connected to a gate of the second MOS transistor, and the source of the switch NMOS transistor is connected to the source of the second MOS transistor.

According to at least one embodiment of the present disclosure, when it is required to turn off the second MOS transistor, the current signal is provided, and the second MOS transistor is rapidly turned off by a voltage formed on the second resistor.

According to at least one embodiment of the present disclosure, the semiconductor device further includes a first resistor, one end of the first resistor is connected to the gate of the second MOS transistor and the other end of the first resistor is connected to the source of the second MOS transistor.

According to at least one embodiment of the present disclosure, the switch further includes a second high voltage protection diode, the switch is a switch NMOS transistor, a positive terminal of the second high voltage protection diode is connected to a gate of the switch NMOS transistor and a negative terminal of the second high voltage protection diode is connected to a source of the switch NMOS transistor, the gate of the switch NMOS transistor is connected to a current signal, a drain of the switch NMOS transistor is connected to a gate of a second MOS transistor, and the source of the switch NMOS transistor is connected to the source of the second MOS transistor.

According to at least one embodiment of the present disclosure, when it is required to turn off the second MOS transistor, the current signal is provided, and the second MOS transistor is rapidly turned off by a voltage formed on the second high voltage protection diode.

According to at least one embodiment of the present disclosure, the semiconductor device further comprises a first high voltage protection diode, wherein the positive end of the first high voltage protection diode is connected with the gate of the second MOS transistor, and the negative end of the first high voltage protection diode is connected with the source of the second MOS transistor.

According to at least one embodiment of the present disclosure, the switch is an N-channel junction field effect transistor, a gate of the N-channel junction field effect transistor is connected to a source of the second MOS transistor, a drain of the N-channel junction field effect transistor is connected to a gate of the second MOS transistor, and a source of the N-channel junction field effect transistor is connected to a source of the second MOS transistor.

According to at least one embodiment of the present disclosure, when it is required to turn off the second MOS transistor, the N-channel junction field effect transistor is rapidly turned off so that the second MOS transistor is rapidly turned off.

According to another aspect, a charge and discharge control device for controlling a charging current and/or a discharging current of a battery/battery pack, comprising:

the charge and discharge switching circuit as described above; and

a drive circuit to provide the first and second control signals.

the charge and discharge switching circuit as described above; and

a drive circuit to provide the first control signal, the second control signal, and a current signal.

According to at least one embodiment of the present disclosure, further comprising:

the device comprises a voltage acquisition unit and/or a detection circuit, wherein the voltage acquisition unit is used for acquiring the voltage of a battery/battery pack, and the detection circuit is used for detecting the charging current and/or the discharging current; and

a control logic circuit to provide control signals to the drive circuit based on signals from the voltage acquisition unit and/or detection circuit.

According to still another aspect, a chip is integrated with the charge and discharge switching circuit as described above, or integrated with the charge and discharge control device as described above.

According to still another aspect, a battery management system is characterized by comprising the charge and discharge switching circuit as described above, or comprising the charge and discharge control device as described above, or comprising the chip as described above.

According to yet another aspect, an electrical device comprises:

a battery/pack for powering other components in the electrical device; and

the charging and discharging switching circuit as described above, or the charging and discharging control device as described above, or the chip as described above, or the battery management system as described above.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 shows a prior art battery management schematic.

Fig. 2 shows a schematic structural diagram of a high withstand voltage transistor.

Fig. 3 shows a battery management schematic.

Fig. 4 shows a battery management schematic.

Fig. 5 shows a battery management schematic.

Fig. 6 shows a battery management schematic.

Fig. 7 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

Fig. 8 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

Fig. 9 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

Fig. 10 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

Fig. 11 shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

FIG. 12 shows a schematic diagram of an electrical device according to an embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.

The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.

When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "below … …," below … …, "" below … …, "" below, "" above … …, "" above, "" … …, "" higher, "and" side (e.g., as in "side wall") to describe one component's relationship to another (other) component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of "above" and "below". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.

In the battery management application environment, in the circuit structure shown in fig. 1, both transistors M1 and M2 must adopt MOSFETs with high voltage withstanding MOSFETs, the basic structure of which is shown in fig. 2, and the corresponding on-resistance R of the high voltage withstanding MOSFET_DS,onThe total of six parts is that the composition, namely,

R_DS,on＝R_s,metal+R_source+R_channel+R_drift+R_drain+R_d,metal。

wherein R is_s,metalIs source contact resistance, R_sourceIs a source neutral region drift resistance, R_channelAs channel resistance, R_driftIs a drift resistor of lightly doped voltage-withstanding region, R_drainIs the drain neutral region drift resistance, R_d,metalIs the drain contact resistance.

V_GSIs a gate-source voltage, V_ThThreshold turn-on voltage for NMOSFET, C_oxIs unit capacitance of gate oxide layer, mu_n，chElectron mobility, μ for NMOSFET channel_n，driftElectron mobility of the withstand voltage drift region, N_driftN-type impurity mobility of a withstand voltage drift region, d_driftDepth in the vertical direction of the channel of the withstand voltage drift region, L_driftLength in the direction of channel of withstand voltage drift region, W_driftBV is a Drain-Source (Drain-Source) breakdown voltage of an NMOSFET, and V is a volt unit of voltage (for normalizing BV, where BV/V is a dimensionless physical quantity), which is a width of the withstand voltage drift region perpendicular to the channel direction.

High durabilityThe voltage NMOSFET (for example, the Source-Drain voltage resistance is more than 10V) is equivalent to the low voltage NMOSFET (for example, the Source-Drain voltage resistance is less than 5V), a long lightly doped voltage-resistant drift region (drift area) is required to be adopted in the device structure, and the higher the Drain-Source voltage resistance is, the higher the doping concentration N of the drift region is_driftThe lower the length L of the drift region_driftThe longer.

According to the formula of the resistance of the voltage-resistant drift region, the drift resistance R of the lightly doped voltage-resistant region can be known to be higher in voltage resistance_driftThe larger the increase, and the more the NMOSFET on-resistance. In general, for high voltage tolerant NMOSFETs, the drift region resistance dominates.

In conventional protection switch circuit designs, 2 high voltage MOSFETs in series must be employed.

In order to solve the problems in the prior art, such as the performance of the battery system, which is affected by the power loss caused by the charging switch and the discharging switch, the series on-resistance of the MOSFET in the current path needs to be reduced. Therefore, only the MOSFETs M1 or M2 shown in fig. 1 may be used in series with the current path, with one of the MOSFETs being used as a charge switch and a discharge switch. Obviously, when one MOSFET is used, the on-resistance can be reduced by half, and the power consumption can be reduced by half. However, if a high voltage MOSFET is used, the following problems occur.

The following description will be made with respect to a case where one MOSFET is employed as the charge switch and the discharge switch.

Fig. 3 shows the case of battery discharge. In the case where only M1 is used for the charge/discharge switch and M2 is omitted, the source S of the MOS transistor M1 is connected to the B-terminal of the battery, the drain D of the MOS transistor M1 is connected to the P-terminal of the external load, and the MOS transistor M1 has a parasitic diode D1, as shown in fig. 3. The gate G of the MOS transistor M1 receives a control signal from the driving unit to be turned on and off. Wherein the source S of the MOS transistor M1 is shorted to the substrate (Bulk, terminal B) of the MOS transistor M1. By using a MOS transistor M1, it is obvious that the on-resistance R of the charge and discharge switch will be enabled_onReduced to half.

When the battery discharges to the external load, the flowing direction of the current in the loop is as follows: discharge current I_dsgFlowing from the P-terminal to the B-terminal, the voltage at the B-terminal is higher than that at the P-terminal, when the voltage difference (I) between the P-terminal and the B-terminal is detected_dsg*R_on) When a certain threshold is reached, the voltage of the control signal at the gate of the MOS transistor M1 changes from high level (e.g., VDD, the supply voltage of the driving unit) to VP- (voltage at the P-terminal), thereby turning off M1 and turning off the discharge path.

Fig. 4 shows the case of battery charging. In the case where only M1 is used for the charge/discharge switch and M2 is omitted, for example, as shown in fig. 4, the source S of the MOS transistor M1 is connected to the B-terminal of the battery, the drain D of the MOS transistor M1 is connected to the P-terminal of the external load, and the MOS transistor M1 has a parasitic diode D1. The gate G of the MOS transistor M1 receives a control signal from the driving unit to be turned on and off. Wherein the source S of the MOS transistor M1 is shorted to the substrate (Bulk, terminal B) of the MOS transistor M1. By using a MOS transistor M1, it is obvious that the on-resistance R of the charge and discharge switch will be enabled_onReduced to half.

When the battery is charged through the external charger, the flowing direction of the current in the loop is as follows: charging current I_chgFlowing from the B-terminal to the P-terminal, the voltage of the P-terminal is higher than that of the B-terminal, when the voltage difference (I) between the B-terminal and the P-terminal is detected_chg*R_on) When a certain threshold is reached, in order to turn off M1, the control signal voltage at the gate of MOS transistor M1 changes from high (VDD, driver circuit supply voltage) to VB-, that is, gate G and source S are shorted, and VG ═ VS ═ VB-.

D1 is the natural parasitic body diode of MOSFET M1, the positive terminal (anode, P-type doped) of parasitic diode D1 is the P-well (Bulk) of MOSFET M1, and the negative terminal (cathode, N-type doped) of parasitic diode D1 is the drain D of MOSFET M1. Therefore, even though the voltage of the control signal at the gate G of the MOSFET M1 is VB ", the MOSFET M1 is turned off (the conduction channel is not formed), but the charging current continues to flow through the parasitic diode D1, continuing to charge the battery.

Therefore, the MOSFET M1 still cannot completely turn off the charging current in case of charging overcurrent due to the parasitic diode D1.

The following description will be made of a case where only M2 is used for the charge/discharge switch and M1 is omitted.

Fig. 5 shows an example in the case of discharging, as shown in fig. 5, the drain D of the MOS transistor M2 is connected to the B-terminal of the battery and the source S of the MOS transistor M2 is connected to the P-terminal of the external load, the MOS transistor M2 having a parasitic diode D1. The gate G of the MOS transistor M2 receives a control signal from the driving unit to be turned on and off. Wherein the source S of the MOS transistor M2 is shorted to the substrate (Bulk, terminal B) of the MOS transistor M2. By using a MOS transistor M2, it is obvious that the on-resistance R of the charge and discharge switch will be enabled_onReduced to half.

When the battery discharges to the load, the flowing direction of the current in the loop is as follows: discharge current I_dsgFlowing from P-terminal to B-terminal, the voltage at B-terminal is higher, when the voltage difference (I) between P-terminal and B-terminal is detected_dsg*R_on) When a certain threshold is reached, the voltage of the gate control signal of the MOS transistor M2 changes from high (VDD, drive circuit supply voltage) to VP-, the gate G and the source S are shorted, and VG ═ VS ═ VP-, in order to turn off the discharge path. Although VG-VS is 0, the conduction channel of M2 disappears. However, since the positive terminal of the parasitic diode D1 is the P-type substrate region (bulk) of the MOS transistor M2 and is connected to the source S, i.e., the P-terminal, and the negative terminal of D1 is connected to the drain D of the MOS transistor M2, the battery can still continue to discharge to the load through the parasitic diode D1 of the MOS transistor M2, and the discharge path cannot be completely cut off.

Fig. 6 shows an example in the case of charging, as shown in fig. 5, the drain D of the MOS transistor M2 is connected to the B-terminal of the battery and the source S of the MOS transistor M2 is connected to the P-terminal of the external load, the MOS transistor M2 having a parasitic diode D1. The gate G of the MOS transistor M2 receives a control signal from the driving unit to be turned on and off. Wherein the source S of the MOS transistor M2 is shorted to the substrate (Bulk, terminal B) of the MOS transistor M2. By using a MOS transistor M2, it is obvious that the on-resistance R of the charge and discharge switch will be enabled_onReduced to half.

When the battery is charged by an external charger, the current flow direction in the loop is: charging deviceElectric current I_chgThe voltage flowing from the B-terminal to the P-terminal is higher, when the voltage difference (I) between the B-terminal and the P-terminal is detected_chg*R_on) When a certain threshold is reached, in order to turn off the MOS transistor M2, the voltage of the control signal of the MOS transistor M2 changes from high (VDD, drive circuit supply voltage) to VB-, i.e., the gate G and the source S are shorted, VG-VS-VB-, the conduction channel of the MOS transistor M2 disappears, and thus the MOS transistor M2 is turned off.

From the explanations of fig. 3 to 6, it can be seen that, although the on-resistance can be reduced by using the MOS transistor M1 or M2 alone, the current path cannot be completely shut off when an overcurrent of the charging current or the discharging current occurs.

The present disclosure provides the following technical solutions to combine the problems of the prior art. In the embodiment of the present disclosure, the MOS transistor is in the form of an NMOSFET, but it should be understood by those skilled in the art that the MOS transistor may also be in the form of a PMOSFET, and the principle of the PMOSFET is the same as that described above, and therefore, for the sake of brevity, the description thereof is omitted.

In the present disclosure, in order to reduce the on-resistance of the NMOS transistor on the current path, a low withstand voltage NMOS transistor is used in combination with a high withstand voltage NMOS transistor, and for example, in the following description, the discharge control switch is replaced with the low withstand voltage NMOS transistor, and the charge control switch still uses the high withstand voltage NMOS transistor. Of course, it will be understood by those skilled in the art in light of the principles of this disclosure that the charge control switch could be replaced by a low withstand voltage NMOS transistor, while the discharge control switch still employs a high withstand voltage NMOS transistor.

The present disclosure provides a charge and discharge switching circuit for controlling a charge current and/or a discharge current of a battery/cell, comprising: the grid electrode of the first MOS transistor receives a first control signal so as to conduct and cut off, the first MOS transistor is a low voltage-resistant MOS transistor, and the source electrode or the drain electrode of the first MOS transistor is connected with the battery side; a gate of the second MOS transistor receives a second control signal to be turned on and off, the second MOS transistor is a high voltage-tolerant MOS transistor, a source or a drain of the second MOS transistor is connected to an external load or an external charger side, and a drain or a source of the second MOS transistor is connected to a drain or a source of the second MOS transistor; and one end of the switch is connected with the grid electrode of the second MOS transistor, and the other end of the switch is connected with the source electrode of the second MOS transistor, so that when the first MOS transistor is turned off, the switch is turned on to enable the second MOS transistor to be turned off before the first MOS transistor is turned off or to be turned off at the same time when the first MOS transistor is turned off.

Further, the first MOS transistor is a discharging MOS transistor and the first control signal is a discharging control signal, the second MOS transistor is a charging MOS transistor and the second control signal is a charging control signal, a source of the first MOS transistor is connected to a battery side, a source of the second MOS transistor is connected to an external load or an external charger side, and a drain of the second MOS transistor is connected to a drain of the second MOS transistor.

Further, the first MOS transistor is a charging MOS transistor and the first control signal is a discharging control signal, the second MOS transistor is a discharging MOS transistor and the second control signal is a discharging control signal, a drain of the first MOS transistor is connected to a battery side, a drain of the second MOS transistor is connected to an external load or an external charger side, and a source of the second MOS transistor is connected to a source of the second MOS transistor.

Further, the battery side is a low-voltage side of a battery, the external load or external charger side is a low-voltage side of the external load or a low-voltage side of the external charger, or the battery side is a high-voltage side of a battery, and the external load or external charger side is a high-voltage side of the external load or a high-voltage side of the external charger.

Further, the on-resistance of the first MOS transistor is smaller than the on-resistance of the second MOS transistor. Therefore, for the first MOS transistor and the second MOS transistor which are connected in series, as the on-resistance of the first MOS transistor is far smaller than that of the second MOS transistor, the on-resistance of the series circuit of the first MOS transistor and the second MOS transistor can be obviously reduced, and the power consumption is obviously reduced. In addition, in the case where the first and second MOS transistors have the same size, it is obvious that the on-resistance of the first MOS transistor with a low withstand voltage is much smaller than the on-resistance of the second MOS transistor with a high withstand voltage. Even if the on-resistance of the first MOS transistor is made equal to the on-resistance of the second MOS transistor under the condition of different size specifications, the manufacturing cost of the first MOS transistor with low withstand voltage is far less than that of the second MOS transistor with high withstand voltage, thereby effectively reducing the system cost.

Further, a high-voltage protection diode is connected between the source and the drain of the first MOS transistor.

The technical solution of the present disclosure will be explained below with reference to specific examples.

< first embodiment >

As shown in fig. 7, this embodiment provides a charge and discharge control device, which may include a VDD generator 10, a voltage acquisition unit 20, a logic control circuit 30, a driving unit 40, and a charge and discharge control switch 50.

The VDD generator 10 may be connected to the highest voltage of the battery/battery pack so as to generate a voltage VDD required inside the charge and discharge control device according to the highest voltage.

The voltage collecting unit 20 may be used to collect the voltage of the battery/battery pack, and in the case of a battery pack, the voltage collecting unit 20 may be used to collect the voltage of each battery.

The logic control circuit 30 may generate a control signal based on the collected voltage of the battery/battery pack. Of course, the logic control circuit 30 may additionally generate control signals depending on the charging current and the discharging current.

The driving unit 40 supplies a signal for driving the charge and discharge control switch 50 according to the control signal of the logic control circuit 30.

The charge and discharge control switch 50 controls the charge current and the discharge current according to the received switch control signal.

Among them, the charge and discharge control switch 50 may include a first low withstand voltage NMOS transistor 100 serving as a discharge switch, a high withstand voltage NMOS transistor 200 serving as a charge switch, and a switch NMOS transistor 300.

The first low withstand voltage NMOS transistor 100 and the high withstand voltage NMOS transistor 200 may be connected in series to either the high voltage side or the low voltage side of the battery/cell stack, and the order of the series connection of the two is not limited.

In this embodiment, the first low withstand voltage NMOS transistor 100 and the high withstand voltage NMOS transistor 200 are connected in series to the low voltage side of the battery/battery pack as an example, and the source S of the first low withstand voltage NMOS transistor 100 is connected to the low voltage side of the battery/battery pack as an example.

The gate of first low withstand voltage NMOS transistor 100 receives discharge control signal OD from drive unit 40, the gate of high withstand voltage NMOS transistor 200 receives charge control signal OC from drive unit 40, and the drain of first low withstand voltage NMOS transistor 100 is connected to the drain of high withstand voltage NMOS transistor 200. The first low withstand voltage NMOS transistor 100 has a first parasitic diode D1, and the high withstand voltage NMOS transistor 200 has a second parasitic diode D2.

The positive terminal of the first high voltage protection diode 102 is connected to the source of the first low withstand voltage NMOS transistor 100, and the negative terminal of the first high voltage protection diode 102 is connected to the drain of the first low withstand voltage NMOS transistor 100.

The drain of the switch NMOS transistor 300 is connected to the gate of the high withstand voltage NMOS transistor 200, and the source of the switch NMOS transistor 300 is connected to the source of the high withstand voltage NMOS transistor 200. A first resistor 302 is connected between the source and the drain of the switching NMOS transistor 300.

The gate of the switch NMOS transistor 300 receives the current signal OB from the drive unit 40, and the gate of the switch NMOS transistor 300 is connected to the source of the high withstand voltage NMOS transistor 200 through the second resistor 304. The switching NMOS transistor 300 can be in the form of a low withstand voltage and can be made small in size.

The source of the first low withstand voltage NMOS transistor 100 is connected to the low voltage terminal B of the battery/battery pack, and the source of the high withstand voltage NMOS transistor 200 is connected to the low voltage terminal P of the external load or charger. It will also be understood by those skilled in the art that the source of the high withstand voltage NMOS transistor 200 is connected to the low voltage terminal B-of the battery/battery pack, and the source of the first low withstand voltage NMOS transistor 100 is connected to the low voltage terminal P-of the external load or charger, which can also achieve the same function. Likewise, its connection to the high voltage side of the battery/cell stack may also perform the same function.

According to an embodiment of the present disclosure, the withstand voltage value of the first low withstand voltage NMOS transistor 100 may be 1.8 to 7V, i.e., V_GS、V_GD、V_DSCan be 1.8-7V. The withstand voltage of the high withstand voltage NMOS transistor 200 is related to the voltage of the battery, which is usually 1.5-2 times of the sum of the voltages of each battery, for example, in the case of 16 batteries, the voltage of each battery is usually 4.5V, the withstand voltage needs to be 4.5 × 16 (1.5-2), for example, the withstand voltage should be greater than 108V, i.e., V_GS、V_GD、V_DSGreater than 108V. According to the foregoing description, the on-resistance is related to the withstand voltage value, and therefore the on-resistance of the first low withstand voltage NMOS transistor 100 is significantly smaller than the on-resistance of the high withstand voltage NMOS transistor 200. The withstand voltage of the switching NMOS transistor 300 can be 10-20V.

With the design of the present disclosure, the first low withstand voltage NMOS transistor 100 is a low withstand voltage type transistor, and if so, when the first low withstand voltage NMOS transistor 100 is turned off, if the high withstand voltage NMOS transistor 200 cannot be turned off in time during the turn-off (e.g., before or at the same time as the turn-off of the first low withstand voltage NMOS transistor 100), the high withstand voltage NMOS transistor 200 remains in a turn-on state, so that the voltage of the P-terminal will be applied to the drain of the first low withstand voltage NMOS transistor 100. Since the voltage at the P-terminal will rise to the voltage at the P + terminal during the turn-off of the first low withstand voltage NMOS transistor 100 and the high withstand voltage NMOS transistor 200.

Since the high withstand voltage NMOS transistor 200 cannot be turned off in time, this will cause the rising voltage value of the P-terminal to be applied to the drain of the first low withstand voltage NMOS transistor 100, while since the first low withstand voltage NMOS transistor 100 is a low withstand voltage type transistor, if a high voltage is applied to its drain, it will inevitably cause damage to the first low withstand voltage NMOS transistor 100.

Thus, in this embodiment, by providing a switch (in the form of the switch NMOS transistor 300), the high withstand voltage NMOS transistor 200 is turned off in time during the turn-off (for example, before or at the same time as the turn-off of the first low withstand voltage NMOS transistor 100). So that the rising voltage value of the P-terminal is not applied to the drain of the first low withstand voltage NMOS transistor 100 but to the drain of the high withstand voltage NMOS transistor 200 (since the high withstand voltage NMOS transistor 200 is a high withstand voltage type transistor, the high voltage does not cause damage to the high withstand voltage NMOS transistor 200).

In the actual high withstand voltage NMOS transistor 200, a parasitic capacitance exists between the gate G and the source S, and due to the parasitic capacitance, even at V_GSThe high withstand voltage NMOS transistor 200 cannot be rapidly turned off even if the voltage of the control signal of the gate is less than the threshold voltage because a certain time is required for the charge discharge of the capacitor, so that the high withstand voltage NMOS transistor 200 cannot be rapidly turned off. The parasitic capacitance of the high withstand voltage NMOS transistor 200 requires a circuit with the first resistor 302 to realize the discharge of the charge. In this case, there is inevitably a case where the high withstand voltage NMOS transistor 200 is turned off with a delay.

In the present embodiment, the high withstand voltage NMOS transistor 200 is turned off quickly (parasitic capacitance is discharged quickly) when it needs to be turned off by a switch connected in series between the gate and the source of the high withstand voltage NMOS transistor 200.

When the high withstand voltage NMOS transistor 200 needs to be turned off, the driving voltage provides a current signal OB, and the current OB flows through the second resistor 304, and then a voltage is formed through the second resistor 304, which is greater than the gate-source voltage V of the switching NMOS transistor 300_GSThe switching NMOS transistor 300 is turned on rapidly, which forms a path between the gate and the source of the high withstand voltage NMOS transistor 200, which causes a parasitic capacitance between the gate and the source of the high withstand voltage NMOS transistor 200 to be discharged rapidly, thereby causing the high withstand voltage NMOS transistor 200 to be turned off rapidly. In this way, the rising P-terminalVoltage is not applied to the drain of the first low withstand voltage NMOS transistor 100, and the first low withstand voltage NMOS transistor 100 is not damaged.

In addition, the first high voltage protection diode 102 is connected in series between the source and the drain of the first low withstand voltage NMOS transistor 100 in order that when the first low withstand voltage NMOS transistor 100 is turned off and the high withstand voltage NMOS transistor 200 is not turned off in time, a high voltage of the P-terminal will be applied to the drain of the first low withstand voltage NMOS transistor 100, the first high voltage protection diode 102 will play a role of protection here, and the high voltage will make the first high voltage protection diode 102 breakdown in the reverse direction, thereby preventing the first low withstand voltage NMOS transistor 100 from being damaged. This is because the first high-voltage protection diode 102 is reverse-broken down, thereby preventing the drain voltage of the first low withstand voltage NMOS transistor 100 from being excessively high.

With the arrangement of the present embodiment, the on-resistance value of the series NMOS transistor from the B-terminal to the P-terminal is:

R_on＝R_DS,on(100)+R_DS,on(200) wherein R is_onIs the sum of the on-resistances of the first low withstand voltage NMOS transistor 100 and the high withstand voltage NMOS transistor 200, R_DS,on(100) Is the on-resistance of the first low withstand voltage NMOS transistor 100, and R_DS,on(200) Is the on-resistance of the high withstand voltage NMOS transistor 200.

And since the first low withstand voltage NMOS transistor 100 is a low withstand voltage NMOSFET, the physical structure of the low withstand voltage NMOSFET does not require a lowly doped withstand voltage drift region, that is, for the low withstand voltage NMOSFET, R_DS,on(100)＝R_s,metal+R_source+R_channel+R_drain+R_d,metal。

Therefore, R is the same physical size of NMOSFET_DS,on(100) Much less than R_DS,on(200) Then R is_on≈R_DS,on(200). Therefore, the series use of high-low voltage NMOSFETs can reduce the on-resistance of the MOSFETs in series by 1 time, so that the heat loss caused by the on-resistance is reduced by 2 times.

< second embodiment >

As shown in fig. 8, this embodiment provides a charge and discharge control device, which may include a VDD generator 10, a voltage acquisition unit 20, a logic control circuit 30, a driving unit 40, and a charge and discharge control switch 50.

The drain of the switch NMOS transistor 300 is connected to the gate of the high withstand voltage NMOS transistor 200, and the source of the switch NMOS transistor 300 is connected to the source of the high withstand voltage NMOS transistor 200. A second high-voltage protection diode 306 is connected between the source and the drain of the switch NMOS transistor 300, wherein a positive terminal of the second high-voltage protection diode 306 is connected to the source of the high withstand voltage NMOS transistor 200, and a negative terminal of the second high-voltage protection diode 306 is connected to the gate of the high withstand voltage NMOS transistor 200. Thus, when a current flows from the positive terminal to the negative terminal of the second high voltage protection diode 306, the breakdown voltage is 6.5-7.5V, which can ensure that the gate-source voltage of the high withstand voltage NMOS transistor 200 is greater than the threshold turn-on voltage, thereby turning on the high withstand voltage NMOS transistor 200.

The gate of the switch NMOS transistor 300 receives the current signal OB from the driving unit 40, and the gate of the switch NMOS transistor 300 is connected to the source of the high withstand voltage NMOS transistor 200 through a third high voltage protection diode 308, wherein the positive terminal of the third high voltage protection diode 308 is connected to the source of the high withstand voltage NMOS transistor 200, and the negative terminal of the third high voltage protection diode 308 is connected to the source of the switch NMOS transistor 300. The switching NMOS transistor 300 can be a low withstand voltage type diode and can be made small in size.

In the actual high withstand voltage NMOS transistor 200, a parasitic capacitance exists between the gate G and the source S, and due to the parasitic capacitance, even at V_GSThe high withstand voltage NMOS transistor 200 cannot be rapidly turned off even if the voltage of the control signal of the gate is less than the threshold voltage because a certain time is required for the charge discharge of the capacitor, so that the high withstand voltage NMOS transistor 200 cannot be rapidly turned off. The parasitic capacitance of the high withstand voltage NMOS transistor 200 requires a circuit with the second high voltage protection diode 306 to achieve the discharge of the charge. In this case, there is inevitably a case where the high withstand voltage NMOS transistor 200 is turned off with a delay.

When the high withstand voltage NMOS transistor 200 needs to be turned off, the driving voltage provides a current signal OB, and the current OB flows through the third high voltage protection diode 308, so that a voltage (when a current exists from the positive terminal to the negative terminal, the breakdown voltage is usually 6.5-7.5V) is formed by the third high voltage protection diode 308, which is greater than the gate-source voltage V of the switch NMOS transistor 300_GSThe switching NMOS transistor 300 is turned on rapidly, which forms a path between the gate and the source of the high withstand voltage NMOS transistor 200, which causes a parasitic capacitance between the gate and the source of the high withstand voltage NMOS transistor 200 to be discharged rapidly, thereby causing the high withstand voltage NMOS transistor 200 to be turned off rapidly. In this way, the rising P-terminal voltage is not applied to the drain of the first low withstand voltage NMOS transistor 100, and the first low withstand voltage NMOS transistor 100 is not damaged.

In addition, the first high voltage protection diode 102 is connected in series between the source and the drain of the first low withstand voltage NMOS transistor 100 in order that when the first low withstand voltage NMOS transistor 100 is turned off and the high withstand voltage NMOS transistor 200 is not turned off in time, a high voltage of the P-terminal will be applied to the drain of the first low withstand voltage NMOS transistor 100, the first high voltage protection diode 102 will play a role of protection here, and the high voltage will make the first high voltage protection diode 102 breakdown in the reverse direction, thereby preventing the first low withstand voltage NMOS transistor 100 from being damaged.

The on-resistance of the series NMOS transistor from B-terminal to P-terminal is thus:

< third embodiment >

As shown in fig. 9, this embodiment provides a charge and discharge control device, which may include a VDD generator 10, a voltage acquisition unit 20, a logic control circuit 30, a driving unit 40, and a charge and discharge control switch 50.

The drain of the N-channel junction field effect transistor 400 is connected to the gate of the high withstand voltage NMOS transistor 200, and the source of the N-channel junction field effect transistor 400 is connected to the source of the high withstand voltage NMOS transistor 200. A third resistor 404 is connected between the source and drain of the N-channel junction field effect transistor 400. The gate of the N-channel junction field effect transistor 400 is connected to the source of the high withstand voltage NMOS transistor 200. The N-channel junction field effect transistor 400 is a low withstand voltage N-channel junction field effect transistor.

According to an embodiment of the present disclosure, the withstand voltage value of the first low withstand voltage NMOS transistor 100 may be 1.8 to 7V, i.e., V_GS、V_GD、V_DSCan be 1.8-7V. The withstand voltage of the high withstand voltage NMOS transistor 200 is related to the voltage of the battery, which is usually 1.5-2 times of the sum of the voltages of each battery, for example, in the case of 16 batteries, the voltage of each battery is usually 4.5V, the withstand voltage needs to be 4.5 × 16 (1.5-2), for example, the withstand voltage should be greater than 108V, i.e., V_GS、V_GD、V_DSGreater than 108V. According to the foregoing description, the on-resistance is related to the withstand voltage value, and therefore the on-resistance of the first low withstand voltage NMOS transistor 100 is significantly smaller than the on-resistance of the high withstand voltage NMOS transistor 200. The voltage resistance of the N-channel JFET 400 can be 10-20V.

In the actual high withstand voltage NMOS transistor 200, a parasitic capacitance exists between the gate G and the source S, and due to the parasitic capacitance, even at V_GSThe high withstand voltage NMOS transistor 200 cannot be rapidly turned off even if the voltage of the control signal of the gate is less than the threshold voltage because a certain time is required for the charge discharge of the capacitor, so that the high withstand voltage NMOS transistor 200 cannot be rapidly turned off. The parasitic capacitance of the high withstand voltage NMOS transistor 200 requires a circuit with the third resistor 404 to realize the discharge of the charge. In this case, there is inevitably a case where the high withstand voltage NMOS transistor 200 is turned off with a delay.

When the high withstand voltage NMOS transistor 200 needs to be turned off, the N-channel junction field effect transistor 400 is turned on quickly, which forms a path between the gate and the source of the high withstand voltage NMOS transistor 200, which causes parasitic capacitance between the gate and the source of the high withstand voltage NMOS transistor 200 to be discharged quickly, thereby causing the high withstand voltage NMOS transistor 200 to be turned off quickly. In this way, the rising P-terminal voltage is not applied to the drain of the first low withstand voltage NMOS transistor 100, and the first low withstand voltage NMOS transistor 100 is not damaged.

Therefore, R is the same physical size of NMOSFET_DS,on(100) Much less than R_DS,on(200) Then R is_on≈R_DS,on(200). Therefore, the series connection of high-low voltage NMOSFET is adoptedThe on-resistance of the MOSFETs connected in series can be reduced by a factor of 1, so that the heat loss due to the on-resistance is reduced by a factor of 2.

< fourth embodiment >

As shown in fig. 10, this embodiment provides a charge and discharge control device, which may include a VDD generator 10, a voltage acquisition unit 20, a logic control circuit 30, a driving unit 40, and a charge and discharge control switch 50.

The drain of the switch NMOS transistor 300 is connected to the gate of the high withstand voltage NMOS transistor 200, and the source of the switch NMOS transistor 300 is connected to the source of the high withstand voltage NMOS transistor 200. A fourth high-voltage protection diode 402 is connected between the source and the drain of the switch NMOS transistor 300, wherein a positive terminal of the fourth high-voltage protection diode 402 is connected to the source of the high withstand voltage NMOS transistor 200, and a negative terminal of the fourth high-voltage protection diode 402 is connected to the gate of the high withstand voltage NMOS transistor 200.

In the actual high withstand voltage NMOS transistor 200, a parasitic capacitance exists between the gate G and the source S, and due to the parasitic capacitance, even at V_GSThe high withstand voltage NMOS transistor 200 cannot be rapidly turned off even if the voltage of the control signal of the gate is less than the threshold voltage because a certain time is required for the charge discharge of the capacitor, so that the high withstand voltage NMOS transistor 200 cannot be rapidly turned off. The parasitic capacitance of the high withstand voltage NMOS transistor 200 requires a circuit with the fourth high voltage protection diode 402 to achieve the discharge of the charge. In this case, there is inevitably a case where the high withstand voltage NMOS transistor 200 is turned off with a delay.

According to another embodiment of the present disclosure, there is provided a chip integrated with the charge and discharge control switching circuit as described above, for example, a portion shown as reference numeral 50 in fig. 11. The chip may be integrated with the charge/discharge control device as described above, for example, a portion shown by reference numeral 1000 in fig. 1.

According to another embodiment of the present disclosure, a battery management system includes the charge and discharge control switching circuit as described above, or includes the charge and discharge control device as described above.

As shown in fig. 12, the present disclosure also provides an electrical device that may include a battery/battery pack for powering other components in the electrical device; the electrical device may further comprise a charge and discharge control switching circuit, a charge and discharge control device, or a chip as described above.

In the description herein, reference to the description of the terms "one embodiment/mode," "some embodiments/modes," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/mode or example is included in at least one embodiment/mode or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to be the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/aspects or examples and features of the various embodiments/aspects or examples described in this specification can be combined and combined by one skilled in the art without conflicting therewith.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.

Claims

1. A charge and discharge switching circuit for controlling a charge current and/or a discharge current of a battery/cell, comprising:

2. The charge and discharge switching circuit according to claim 1, wherein the first MOS transistor is a discharge MOS transistor and the first control signal is a discharge control signal, the second MOS transistor is a charge MOS transistor and the second control signal is a charge control signal, a source of the first MOS transistor is connected to a battery side, a source of the second MOS transistor is connected to an external load or an external charger side, and a drain of the second MOS transistor is connected to a drain of the second MOS transistor.

3. The charge and discharge switching circuit according to claim 1, wherein the first MOS transistor is a charge MOS transistor and the first control signal is a discharge control signal, the second MOS transistor is a discharge MOS transistor and the second control signal is a discharge control signal, a drain of the first MOS transistor is connected to a battery side, a drain of the second MOS transistor is connected to an external load or an external charger side, and a source of the second MOS transistor is connected to a source of the second MOS transistor.

4. The charge-discharge switching circuit according to claim 1,

the battery side is a low-voltage side of the battery, and the external load or external charger side is a low-voltage side of the external load or a low-voltage side of the external charger, or

The battery side is a high-voltage side of the battery, and the external load or external charger side is a high-voltage side of the external load or a high-voltage side of the external charger.

5. The charge and discharge switching circuit according to any one of claims 1 to 4, wherein a high voltage protection diode is connected between the source and the drain of the first MOS transistor;

preferably, the on-resistance of the first MOS transistor is smaller than the on-resistance of the second MOS transistor;

preferably, the first MOS transistor and the second MOS transistor are NMOS transistors;

preferably, the switch further comprises a second resistor, the switch is an NMOS transistor for switch, one end of the second resistor is connected to the gate of the NMOS transistor for switch and the other end of the second resistor is connected to the source of the NMOS transistor for switch, the gate of the NMOS transistor for switch is connected to a current signal, the drain of the NMOS transistor for switch is connected to the gate of the second MOS transistor, and the source of the NMOS transistor for switch is connected to the source of the second MOS transistor;

preferably, when it is required to turn off the second MOS transistor, the current signal is provided, and the second MOS transistor is rapidly turned off by a voltage formed on the second resistor;

preferably, the transistor further comprises a first resistor, one end of the first resistor is connected with the gate of the second MOS transistor, and the other end of the first resistor is connected with the source of the second MOS transistor;

preferably, the switch further comprises a second high-voltage protection diode, the switch is an NMOS transistor for switch, a positive terminal of the second high-voltage protection diode is connected to a gate of the NMOS transistor for switch and a negative terminal of the second high-voltage protection diode is connected to a source of the NMOS transistor for switch, the gate of the NMOS transistor for switch is connected to a current signal, a drain of the NMOS transistor for switch is connected to a gate of the second MOS transistor, and the source of the NMOS transistor for switch is connected to the source of the second MOS transistor;

preferably, when it is desired to turn off the second MOS transistor, the current signal is provided such that the second MOS transistor is rapidly turned off by a voltage developed across the second high voltage protection diode.

6. The charge and discharge switch circuit according to any one of claims 1 to 5, further comprising a first high voltage protection diode, a positive terminal of the first high voltage protection diode being connected to the gate of the second MOS transistor and a negative terminal of the high voltage protection diode being connected to the source of the second MOS transistor;

preferably, the switch is an N-channel junction field effect transistor, a gate of the N-channel junction field effect transistor is connected to a source of the second MOS transistor, a drain of the N-channel junction field effect transistor is connected to a gate of the second MOS transistor, and a source of the N-channel junction field effect transistor is connected to a source of the second MOS transistor;

preferably, when the second MOS transistor needs to be turned off, the N-channel junction field effect transistor is rapidly turned off so that the second MOS transistor is rapidly turned off;

preferably, the MOS transistor further comprises a first high voltage protection diode, wherein the positive end of the first high voltage protection diode is connected with the grid electrode of the second MOS transistor, and the negative end of the first high voltage protection diode is connected with the source electrode of the second MOS transistor.

7. A charge-discharge control device for controlling a charge current and/or a discharge current of a battery/battery pack, comprising:

the charge-discharge switching circuit according to any one of claims 1 to 6; and

a drive circuit for providing the first control signal and the second control signal,

preferably, the method further comprises the following steps:

8. A chip incorporating the charge-discharge switching circuit according to any one of claims 1 to 6 or incorporating the charge-discharge control device according to claim 7.

9. A battery management system comprising the charge and discharge switching circuit according to any one of claims 1 to 6, or comprising the charge and discharge control device according to claim 7, or comprising the chip according to claim 8.

10. An electrical device, comprising:

a battery/pack for powering other components in the electrical device; and

the charge and discharge switching circuit according to any one of claims 1 to 6, or the charge and discharge control device according to claim 7, or the chip according to claim 8, or the battery management system according to claim 9.