CN218633895U

CN218633895U - Semiconductor device for battery protection switch

Info

Publication number: CN218633895U
Application number: CN202122373905.1U
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Zhuhai Maiju Microelectronics Co Ltd
Current assignee: Zhuhai Maiju Microelectronics Co Ltd
Priority date: 2020-10-14
Filing date: 2021-09-28
Publication date: 2023-03-14
Anticipated expiration: 2031-09-28
Also published as: CN112398463A; CN113824438A

Abstract

The present disclosure provides a semiconductor device for a battery protection switch, including: the first cell area is provided with a first MOS transistor, and the first MOS transistor receives a first control signal to enable the first MOS transistor to be switched on or switched off; the second cell area is provided with a second MOS transistor, the second MOS transistor receives a second control signal to enable the second MOS transistor to be switched on or switched off, and the first cell area and the second cell area are adjacently arranged; and a third cell area, the third cell area being disposed adjacent to the second cell area, the third cell area being formed with a switch, the switch receiving a third control signal to control: when the first MOS transistor is turned off, the switch is turned on to turn off the second MOS transistor before or simultaneously with the first MOS transistor.

Description

Semiconductor device for battery protection switch

Technical Field

The present disclosure belongs to the field of semiconductor technology, and particularly relates to a semiconductor device for a battery protection switch.

Background

In the battery system, overcharge and overdischarge of the battery not only reduce the lifespan of the battery, but also cause safety accidents of explosion and fire when serious. The battery is, for example, a lithium battery pack or the like.

In the prior art, a device for controlling charging and discharging of a battery in a battery system often cannot completely turn off a charging current or a discharging circuit under the condition of over-charging or over-discharging of the battery, so that potential safety hazards exist.

SUMMERY OF THE UTILITY MODEL

In order to solve one of the above technical problems, the present disclosure provides a semiconductor device for a battery protection switch.

The semiconductor device for the battery protection switch of the present disclosure is realized by the following technical solutions.

According to an aspect of the present disclosure, there is provided a semiconductor device for a battery protection switch, including: the first cell area is provided with a first MOS transistor, and the first MOS transistor receives a first control signal to enable the first MOS transistor to be switched on or switched off; a second cell region formed with a second MOS transistor that receives a second control signal to turn on or off the second MOS transistor, the first cell region being disposed adjacent to the second cell region; and a third cell area, the third cell area being disposed adjacent to the second cell area, the third cell area being formed with a switch, the switch receiving a third control signal to control: when the first MOS transistor is turned off, the switch is turned on to turn off the second MOS transistor before the first MOS transistor is turned off or simultaneously with the first MOS transistor being turned off.

According to a semiconductor device of at least one embodiment of the present disclosure, the first cell region includes a first gate region, a first source region, and a first drain region, the first cell region has a first parasitic diode formed therein, and the first parasitic diode is formed between the first source region and the first drain region.

According to a semiconductor device of at least one embodiment of the present disclosure, the second cell region includes a second gate region, a second source region, and a first drain region, the second cell region having a second parasitic diode formed therein, the second parasitic diode being formed between the second source region and the first drain region.

According to a semiconductor device of at least one embodiment of the present disclosure, the first parasitic diode and the second parasitic diode constitute an inverse series structure, and the first cell region and the second cell region share the first drain region.

A semiconductor device according to at least one embodiment of the present disclosure, further comprising a fourth cell region disposed adjacent to the first cell region, the fourth cell region having a protection diode formed therein, the fourth cell region including a first source region and a second drain region, the fourth cell region sharing a first source region with the first cell region, the first drain region of the first cell region and the second drain region of the fourth cell region being connectable such that the protection diode is connected in parallel with the first parasitic diode such that the second MOS transistor is rapidly turned off by a voltage formed on the protection diode when the second MOS transistor needs to be turned off.

According to the semiconductor device of at least one embodiment of the present disclosure, the third cell region includes a third gate region, a second source region and a third drain region, the third cell region shares the second source region with the second cell region, and the third drain region of the third cell region and the second gate region of the second cell region can be connected.

According to the semiconductor device of at least one embodiment of the present disclosure, the protection diode is a high voltage diode.

The semiconductor device according to at least one embodiment of the present disclosure further includes a substrate electrode region, and the first cell region, the second cell region, the third cell region, and the fourth cell region are formed on a common substrate.

According to the semiconductor device of at least one embodiment of the present disclosure, the first MOS transistor is an NMOS transistor, and the substrate is a P-type substrate; the first cell region comprises a first gate region, a first source region and a first drain region, and the first cell region comprises a P-type substrate and a dielectric layer; at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a first P-type well region is formed in the N-type drift region, at least a first P-type high-doping region and a first N-type high-doping region are formed in the first P-type well region, the first P-type well region and the P-type substrate are spaced through the N-type drift region, and a second N-type high-doping region is formed in the N-type drift region; the first source region is formed on the dielectric layer, and at least one part of the first source region penetrates through the dielectric layer to be in contact with the first N-type high-doping region and the first P-type high-doping region; the first drain electrode region is formed on the dielectric layer, and at least one part of the first drain electrode region penetrates through the dielectric layer to be in contact with the second N-type high-doping region; the first gate region is formed in the dielectric layer.

According to the semiconductor device of at least one embodiment of the present disclosure, the second MOS transistor is an NMOS transistor, and the substrate is a P-type substrate; the second cell area comprises a second gate area, a second source area and a first drain area, and the second cell area comprises a P-type substrate and a dielectric layer; at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a second P-type well region is formed in the N-type drift region, at least a third P-type highly-doped region and a third N-type highly-doped region are formed in the second P-type well region, the second P-type well region and the P-type substrate are spaced through the N-type drift region, and a second N-type highly-doped region is formed in the N-type drift region; the second source region is formed on the dielectric layer, and at least one part of the second source region penetrates through the dielectric layer to be in contact with the third N-type high-doping region and the third P-type high-doping region; the first drain electrode region is formed on the dielectric layer, and at least one part of the first drain electrode region penetrates through the dielectric layer to be in contact with the second N-type high-doping region; the second gate region is formed in the dielectric layer.

According to the semiconductor device of at least one embodiment of the present disclosure, the third unit cell region comprises a third gate region, a second source region and a third drain region, and the third unit cell region comprises a P-type substrate and a dielectric layer; at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a third P-type well region is formed in the N-type drift region, at least a fourth P-type highly-doped region and a fourth N-type highly-doped region are formed in the third P-type well region, the third P-type well region and the P-type substrate are spaced through the N-type drift region, and a fifth N-type highly-doped region is formed in the N-type drift region; the second source region is formed on the dielectric layer, and at least one part of the second source region penetrates through the dielectric layer to be in contact with the fourth N-type high-doping region and the fourth P-type high-doping region; the third drain electrode region is formed on the dielectric layer, and at least one part of the third drain electrode region penetrates through the dielectric layer to be in contact with the fifth N-type high-doping region; the third gate region is formed in the dielectric layer.

According to the semiconductor device of at least one embodiment of the present disclosure, the fourth cell region includes a first source region and a second drain region; the fourth cell area comprises a P-type substrate and a dielectric layer; at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a fourth P-type well region is formed in the N-type drift region, at least a sixth P-type highly-doped region is formed in the fourth P-type well region, the fourth P-type well region is spaced from the P-type substrate through the N-type drift region, and a sixth N-type highly-doped region is formed in the N-type drift region; the first source region is formed on the dielectric layer, and at least one part of the first source region penetrates through the dielectric layer to be in contact with the sixth P-type high-doping region; the second drain region is formed on the dielectric layer, and at least one part of the second drain region penetrates through the dielectric layer to be in contact with the sixth N-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, a fifth P-type highly doped region is further formed on the substrate, the substrate electrode region is formed on the dielectric layer, and at least a part of the substrate electrode region penetrates through the dielectric layer to contact with the fifth P-type highly doped region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first MOS transistor is a PMOS transistor, and the substrate is an N-type substrate; the first cell region comprises a first gate region, a first source region and a first drain region, and the first cell region comprises an N-type substrate and a dielectric layer; at least a P-type drift region is formed between the N-type substrate and the dielectric layer, a first N-type well region is formed in the P-type drift region, at least a first N-type high-doping region and a first P-type high-doping region are formed in the first N-type well region, the first N-type well region and the N-type substrate are separated by the P-type drift region, and a second P-type high-doping region is formed in the P-type drift region; the first source region is formed on the dielectric layer, and at least one part of the first source region penetrates through the dielectric layer to be in contact with the first P-type highly-doped region and the first N-type highly-doped region; the first drain electrode region is formed on the dielectric layer, and at least one part of the first drain electrode region penetrates through the dielectric layer to be in contact with the second P-type high-doping region; the first gate region is formed in the dielectric layer.

According to the semiconductor device of at least one embodiment of the present disclosure, the second MOS transistor is a PMOS transistor, and the substrate is an N-type substrate; the second cell area comprises a second gate area, a second source area and a first drain area, and the second cell area comprises an N-type substrate and a dielectric layer; at least a P-type drift region is formed between the N-type substrate and the dielectric layer, a second N-type well region is formed in the P-type drift region, at least a third N-type high-doping region and a third P-type high-doping region are formed in the second N-type well region, the second N-type well region and the N-type substrate are separated by the P-type drift region, and a second P-type high-doping region is formed in the P-type drift region; the second source region is formed on the dielectric layer, and at least one part of the second source region penetrates through the dielectric layer to be in contact with the third P-type highly-doped region and the third N-type highly-doped region; the first drain electrode region is formed on the dielectric layer, and at least one part of the first drain electrode region penetrates through the dielectric layer to be in contact with the second P-type highly doped region; the second gate region is formed in the dielectric layer.

According to the semiconductor device of at least one embodiment of the present disclosure, the third cell region includes a third gate region, a second source region and a third drain region, and the third cell region includes an N-type substrate and a dielectric layer; at least a P-type drift region is formed between the N-type substrate and the dielectric layer, a third N-type well region is formed in the P-type drift region, at least a fourth N-type highly-doped region and a fourth P-type highly-doped region are formed in the third N-type well region, the third N-type well region and the N-type substrate are separated by the P-type drift region, and a fifth P-type highly-doped region is formed in the P-type drift region; the second source region is formed on the dielectric layer, and at least one part of the second source region penetrates through the dielectric layer to be in contact with the fourth P-type high-doping region and the fourth N-type high-doping region; the third drain electrode region is formed on the dielectric layer, and at least one part of the third drain electrode region penetrates through the dielectric layer to be in contact with the fifth P-type highly doped region; the third gate region is formed in the dielectric layer.

According to the semiconductor device of at least one embodiment of the present disclosure, the fourth cell region includes a first source region and a second drain region; the fourth cell area comprises an N-type substrate and a dielectric layer; at least a P-type drift region is formed between the N-type substrate and the dielectric layer, a fourth N-type well region is formed in the P-type drift region, at least a sixth N-type highly doped region is formed in the fourth N-type well region, the fourth N-type well region and the N-type substrate are separated by the P-type drift region, and a sixth P-type highly doped region is formed in the P-type drift region; the first source region is formed on the dielectric layer, and at least one part of the first source region penetrates through the dielectric layer to be in contact with the sixth N-type high-doping region; the second drain region is formed on the dielectric layer, and at least one part of the second drain region penetrates through the dielectric layer to be in contact with the sixth P-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, a fifth N-type highly doped region is further formed on the substrate, the substrate electrode region is formed on the dielectric layer, and at least a portion of the substrate electrode region passes through the dielectric layer to contact the fifth N-type highly doped region.

According to the semiconductor device of at least one embodiment of the present disclosure, a region between the dielectric layer and the substrate of the first cell region and a region between the dielectric layer and the substrate of the fourth cell region are isolated by a PN junction; the region between the dielectric layer and the substrate of the second cell region and the region between the dielectric layer and the substrate of the third cell region are isolated through PN junctions; and the region between the dielectric layer of the third unit cell region and the substrate and the doped region between the electrode region of the substrate and the substrate are isolated through PN junctions.

According to the semiconductor device of at least one embodiment of the present disclosure, a region between the dielectric layer of the first cell region and the substrate and a region between the dielectric layer of the fourth cell region and the substrate are isolated by an isolation dielectric; the region between the dielectric layer of the second cell region and the substrate and the region between the dielectric layer of the third cell region and the substrate are isolated through an isolation medium; and the region between the dielectric layer of the third unit cell region and the substrate and the doped region between the electrode region of the substrate and the substrate are isolated by an isolation medium.

According to the semiconductor device of at least one embodiment of the present disclosure, the first cell region includes a first source region, a drain region and a first gate region, an N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a P-type well region is formed in the N-type drift region, a P-type highly doped region is formed in the P-type well region, an N-type highly doped region is formed on the P-type well region, the first cell region further includes a dielectric layer, and at least a portion of the first source region sequentially passes through the dielectric layer and the N-type highly doped region and then contacts with the P-type highly doped region; two isolation medium regions are symmetrically formed in the P-type well region, and one first gate region is formed in each isolation medium region.

According to the semiconductor device of at least one embodiment of the present disclosure, the second cell region includes a second source region, a drain region and a second gate region, an N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a P-type well region is formed in the N-type drift region, a P-type highly doped region is formed in the P-type well region, an N-type highly doped region is formed on the P-type well region, the second cell region further includes a dielectric layer, and at least a portion of the second source region sequentially passes through the dielectric layer and the N-type highly doped region and then contacts with the P-type highly doped region; two isolation medium regions are symmetrically formed in the P-type well region, and one second gate region is formed in each isolation medium region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first cell region and the second cell region share the dielectric layer, the drain region and the N-type highly doped region.

According to the semiconductor device of at least one embodiment of the present disclosure, at least one isolation dielectric region is formed at least between the P-type well region of the first cell region and the P-type well region of the second cell region, and a metal floating region is formed in the isolation dielectric region.

According to the semiconductor device of at least one embodiment of the present disclosure, at least one isolation dielectric region is formed at least between the P-type well region of the first cell region and the P-type well region of the fourth cell region, and a metal floating region is formed in the isolation dielectric region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first gate region and the second gate region are both trench gate structures.

According to the semiconductor device of at least one embodiment of the present disclosure, the first gate region and the second gate region are both of a split trench gate structure.

According to the semiconductor device of at least one embodiment of the present disclosure, the first cell region and the second cell region each employ a super junction structure.

According to the semiconductor device of at least one embodiment of the present disclosure, the first cell region includes a first source region, a drain region and a first gate region, a P-type highly doped region is formed on the drain region, a P-type drift region is formed on the P-type highly doped region, an N-type well region is formed in the P-type drift region, an N-type highly doped region is formed in the N-type well region, a P-type highly doped region is formed on the N-type well region, the first cell region further includes a dielectric layer, and at least a part of the first source region sequentially passes through the dielectric layer and the P-type highly doped region and then contacts with the N-type highly doped region; two isolation medium regions are symmetrically formed in the N-type well region, and one first gate region is formed in each isolation medium region.

According to the semiconductor device of at least one embodiment of the present disclosure, the second cell region includes a second source region, a drain region and a second gate region, a P-type highly doped region is formed on the drain region, a P-type drift region is formed on the P-type highly doped region, an N-type well region is formed in the P-type drift region, an N-type highly doped region is formed in the N-type well region, a P-type highly doped region is formed on the N-type well region, the second cell region further includes a dielectric layer, and at least a portion of the second source region sequentially passes through the dielectric layer and the P-type highly doped region and then contacts with the N-type highly doped region; two isolation medium regions are symmetrically formed in the N-type well region, and one second gate region is formed in each isolation medium region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first cell region and the second cell region share the dielectric layer, the drain region and the P-type highly doped region.

According to the semiconductor device of at least one embodiment of the present disclosure, at least one isolation medium region is formed between the N-type well region of the first cell region and the N-type well region of the second cell region, and a metal floating area is formed in the isolation medium region.

According to the semiconductor device of at least one embodiment of the present disclosure, at least one isolation dielectric region is formed at least between the N-type well region of the first cell region and the N-type well region of the fourth cell region, and a metal floating region is formed in the isolation dielectric region.

According to the semiconductor device of at least one embodiment of the present disclosure, the thickness of the drift region of the first cell region is smaller than the thickness of the drift region of the second cell region, so that the first MOS transistor formed by the first cell region has low withstand voltage performance and the second MOS transistor formed by the second cell region has high withstand voltage performance.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 is a schematic configuration diagram of a circuit configuration corresponding to a semiconductor device for a battery protection switch according to an embodiment of the present disclosure, when the circuit configuration is used for a charge/discharge control device.

Fig. 2 is a schematic structural diagram of a semiconductor device for a battery protection switch according to an embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram of respective cell regions of a semiconductor device for a battery protection switch according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of a semiconductor device for a battery protection switch according to still another embodiment of the present disclosure.

Fig. 5 is a schematic structural diagram of a semiconductor device for a battery protection switch according to still another embodiment of the present disclosure.

Fig. 6 is a schematic structural diagram of a semiconductor device for a battery protection switch according to still another embodiment of the present disclosure.

Fig. 7 is a schematic structural view of a semiconductor device for a battery protection switch according to still another embodiment of the present disclosure.

Fig. 8 is a schematic structural view of a semiconductor device for a battery protection switch according to still another embodiment of the present disclosure.

Fig. 9 is a schematic structural view of a semiconductor device for a battery protection switch according to still another embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant matter and not restrictive of the disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.

The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.

When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "under 8230; \8230;,"' under 8230; \8230; below 8230; under 8230; above, on, above 8230; higher "and" side (e.g., as in "side wall)", etc., to describe the relationship of one component to another (other) component as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "at 8230 \8230;" below "may encompass both an orientation of" above "and" below ". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.

Fig. 1 is a schematic configuration diagram of a circuit configuration corresponding to a semiconductor device for a battery protection switch according to an embodiment of the present disclosure when used in a charge/discharge control device. Wherein 50 is a circuit structure corresponding to the semiconductor device for the battery protection switch.

As shown in fig. 1, the charge and discharge control apparatus may include a VDD generator 10, a voltage acquisition unit 20, a logic control circuit 30, a driving unit 40, and a charge and discharge control switch 50 (which may be implemented by the semiconductor device for a battery protection switch of the present disclosure).

The VDD generator 10 may be connected to the highest voltage of the battery/battery pack so as to generate a voltage VDD required inside the charge and discharge control device according to the highest voltage.

The voltage collecting unit 20 may be used to collect the voltage of the battery/battery pack, and in the case of a battery pack, the voltage collecting unit 20 may be used to collect the voltage of each battery.

The logic control circuit 30 may generate a control signal based on the collected voltage of the battery/battery pack. Of course, the logic control circuit 30 may additionally generate control signals depending on the charging current and the discharging current.

The driving unit 40 supplies a signal for driving the charge and discharge control switch 50 according to a control signal of the logic control circuit 30.

The charge and discharge control switch 50 controls the charge current and the discharge current according to the received switch control signal.

Taking NMOS transistors as an example, the charge and discharge control switch 50 may include a low withstand voltage NMOS transistor 100 serving as a discharge switch, a high withstand voltage NMOS transistor 200 serving as a charge switch, and a switch NMOS transistor 300, among others.

The low withstand voltage NMOS transistor 100 and the high withstand voltage NMOS transistor 200 may be connected in series to either the high voltage side or the low voltage side of the battery/cell stack, and the order of the series connection of the two is not limited.

In this embodiment, the low withstand voltage NMOS transistor 100 and the high withstand voltage NMOS transistor 200 are connected in series to the low voltage side of the battery/battery pack as an example, and the source S1 of the low withstand voltage NMOS transistor 100 is connected to the low voltage side of the battery/battery pack as an example.

The gate G1 of the low withstand voltage NMOS transistor 100 receives the discharge control signal OD from the driving unit 40, the gate G2 of the high withstand voltage NMOS transistor 200 receives the charge control signal OC from the driving unit 40, and the drain D1 of the low withstand voltage NMOS transistor 100 is connected to the drain D2 of the high withstand voltage NMOS transistor 200. The low withstand voltage NMOS transistor 100 has a first parasitic diode D1, and the high withstand voltage NMOS transistor 200 has a second parasitic diode D2.

The positive terminal of the first high-voltage protection diode D1 is connected to the source of the low withstand voltage NMOS transistor 100, and the negative terminal of the first high-voltage protection diode D1 is connected to the drain of the low withstand voltage NMOS transistor 100.

The drain of the switch NMOS transistor 300 is connected to the gate of the high withstand voltage NMOS transistor 200, and the source of the switch NMOS transistor 300 is connected to the source of the high withstand voltage NMOS transistor 200. A first resistor R1 may be connected between the source and the drain of the switching NMOS transistor 300.

The gate of the switch NMOS transistor 300 receives the current signal OB from the drive unit 40, and the gate of the switch NMOS transistor 300 is connected to the source of the high withstand voltage NMOS transistor 200 through the second resistor R2. The switching NMOS transistor 300 can be in the form of a low withstand voltage and can be made small in size.

The source of the low withstand voltage NMOS transistor 100 is connected to the low voltage terminal B-of the battery/cell stack, and the source of the high withstand voltage NMOS transistor 200 is connected to the low voltage terminal P-of the external load or charger. It will also be understood by those skilled in the art that the source of the high withstand voltage NMOS transistor 200 is connected to the low voltage terminal B-of the battery/battery pack, and the source of the first low withstand voltage NMOS transistor 100 is connected to the low voltage terminal P-of the external load or charger, which can also achieve the same function. Likewise, its connection to the high voltage side of the battery/cell stack may also perform the same function.

The withstand voltage value of the low withstand voltage NMOS transistor 100 may be 1.8 to 7V, i.e., V _GS 、V _GD 、V _DS Can be between 1.8 and 7V. The withstand voltage of the high withstand voltage NMOS transistor 200 is related to the voltage of the battery, which is usually 1.5 to 2 times the sum of the voltages of each battery, for example, in the case of 16 batteries, the voltage of each battery is usually 4.5V, and the withstand voltage thereof needs to be 4.5 × 16 (1.5 to 2) V, for example, the withstand voltage thereof should be more than 108V, that is, V _GS 、V _GD 、V _DS Greater than 108V. According to the foregoing description, the on-resistance is related to the withstand voltage value, and therefore the on-resistance of the low withstand voltage NMOS transistor 100 is significantly smaller than the on-resistance of the high withstand voltage NMOS transistor 200. And the withstand voltage value of the switching NMOS transistor 300 may be 10 to 20V.

If the low withstand voltage NMOS transistor 100 is a low withstand voltage type transistor, then, when the low withstand voltage NMOS transistor 100 is turned off, if the high withstand voltage NMOS transistor 200 cannot be turned off in time during the turn-off (for example, before or at the same time as the turn-off of the low withstand voltage NMOS transistor 100), the high withstand voltage NMOS transistor 200 remains in the on state, so that the voltage of the P-terminal will be applied to the drain of the low withstand voltage NMOS transistor 100. Since the voltage at the P-terminal will rise to the voltage at the P + terminal during the turn-off of the low withstand voltage NMOS transistor 100 and the high withstand voltage NMOS transistor 200.

Since the high withstand voltage NMOS transistor 200 cannot be turned off in time, this will cause a rising voltage value of the P-terminal to be applied to the drain of the low withstand voltage NMOS transistor 100, while since the low withstand voltage NMOS transistor 100 is of a low withstand voltage type, if a high voltage is applied to the drain thereof, damage of the low withstand voltage NMOS transistor 100 will certainly be caused.

By providing a switch (in the form of a switch NMOS transistor 300), the high withstand voltage NMOS transistor 200 is turned off in time during the turn-off (for example, before or at the same time as the turn-off of the low withstand voltage NMOS transistor 100). So that the rising voltage value of the P-terminal is not applied to the drain of the low withstand voltage NMOS transistor 100 but to the drain of the high withstand voltage NMOS transistor 200 (since the high withstand voltage NMOS transistor 200 is a high withstand voltage type transistor, the high voltage does not cause damage to the high withstand voltage NMOS transistor 200).

In the actual high withstand voltage NMOS transistor 200, a parasitic capacitance exists between the gate G and the source S, and due to the parasitic capacitance, V is a capacitance that is equal to V _GS The high withstand voltage NMOS transistor 200 cannot be rapidly turned off even if the voltage of the control signal of the gate is less than the threshold voltage because a certain time is required for the charge discharge of the capacitor, so that the high withstand voltage NMOS transistor 200 cannot be rapidly turned off. The parasitic capacitance of the high withstand voltage NMOS transistor 200 needs a circuit with the first resistor R1 to realize the discharge of the electric charge. In this case, there is inevitably a case where the high withstand voltage NMOS transistor 200 is turned off with a delay.

By the switch connected in series between the gate and the source of the high withstand voltage NMOS transistor 200, the high withstand voltage NMOS transistor 200 is quickly turned off (parasitic capacitance is quickly discharged) when it needs to be turned off.

When the high withstand voltage NMOS transistor 200 needs to be turned off, the driving voltage provides a current signal OB, and the current OB flows through the second resistor R2, and then a voltage is formed through the second resistor R2, which is greater than the gate-source voltage V of the switching NMOS transistor 300 _GS The switching NMOS transistor 300 is turned on rapidly, which forms a path between the gate and the source of the high withstand voltage NMOS transistor 200, which causes a parasitic capacitance between the gate and the source of the high withstand voltage NMOS transistor 200 to be discharged rapidly, thereby causing the high withstand voltage NMOS transistor 200 to be turned off rapidly. In this way, the rising P-terminal voltage is not applied to the drain of the first low withstand voltage NMOS transistor 100, and the low withstand voltage isThe NMOS transistor 100 is not damaged.

In addition, the high voltage protection diode D3 is connected in series between the source and the drain of the low withstand voltage NMOS transistor 100, so that when the low withstand voltage NMOS transistor 100 is turned off and the high withstand voltage NMOS transistor 200 is not turned off in time, a high voltage at the P-terminal will be applied to the drain of the low withstand voltage NMOS transistor 100, the high voltage protection diode D3 will play a role in protection, and the high voltage will make the high voltage protection diode D3 breakdown in the reverse direction, thereby preventing the low withstand voltage NMOS transistor 100 from being damaged. This is because the high voltage protection diode D3 is reverse-broken down, thereby preventing the drain voltage of the low withstand voltage NMOS transistor 100 from being excessively high.

The on-resistance of the series NMOS transistor from B-terminal to P-terminal is:

R _on ＝R _DS,on (100)+R _DS,on (200) Wherein R is _on Is the sum of the on-resistances of the low withstand voltage NMOS transistor 100 and the high withstand voltage NMOS transistor 200, R _DS,on (100) Is the on-resistance of the low withstand voltage NMOS transistor 100, and R _DS,on (200) Is the on-resistance of the high withstand voltage NMOS transistor 200.

And since low withstand voltage NMOS transistor 100 is a low withstand voltage NMOSFET, the physical structure of the low withstand voltage NMOSFET does not require a lowly doped withstand voltage drift region, that is, for the low withstand voltage NMOSFET, R _DS,on (100)＝R _s,metal +R _source +R _channel +R _drain +R _d,metal 。

Therefore, R is the same physical size of NMOSFET _DS,on (100) Much less than R _DS,on (200) Then R is _on ≈R _DS,on (200). Therefore, the series connection of the high-voltage NMOSFETs and the low-voltage NMOSFETs can reduce the on-resistance of the MOSFETs connected in series by 1 time, so that the heat loss caused by the on-resistance is reduced by 2 times.

As shown in fig. 2 and 3, the semiconductor device for a battery protection switch includes: the first cell area (MNLV 1), the first cell area (MNLV 1) is formed with the first MOS transistor, the first MOS transistor receives the first control signal in order to make the first MOS transistor turn on or turn off;

a second cell region (MNHV 2), wherein a second MOS transistor is formed on the second cell region (MNHV 2), the second MOS transistor receives a second control signal to enable the second MOS transistor to be switched on or off, and the first cell region and the second cell region are adjacently arranged; and

a third cell area (MN 3) disposed adjacent to the second cell area, the third cell area being formed with a switch that receives a third control signal to control: when the first MOS transistor performs an off action, the switch is turned on so that the second MOS transistor is turned off before the first MOS transistor is turned off or is turned off at the same time as the first MOS transistor is turned off.

According to a preferred embodiment of the present disclosure, the first cell region includes a first gate region G1, a first source region S1, and a first drain region D, the first cell region has a first parasitic diode D1 formed therein, and the first parasitic diode D1 is formed between the first source region S1 and the first drain region D.

According to a preferred embodiment of the present disclosure, the second cell region includes a second gate region G2, a second source region S2, and a first drain region D, the second cell region having a second parasitic diode D2 formed therein, the second parasitic diode D2 being formed between the second source region S2 and the first drain region D.

As shown in fig. 2 and 3, the first parasitic diode D1 and the second parasitic diode D2 constitute an inverse series structure, and the first drain region D is shared by the first cell region (MNLV 1) and the second cell region (MNHV 2).

As shown in fig. 3, the semiconductor device further includes a fourth cell region (D3), the fourth cell region (D3) is disposed adjacent to the first cell region (MNLV 1), the fourth cell region has a protection diode D3 formed therein, the fourth cell region includes a first source region S1 and a second drain region D, the fourth cell region shares the first source region S1 with the first cell region, the first drain region D of the first cell region and the second drain region D of the fourth cell region can be connected such that the protection diode D3 is connected in parallel with the first parasitic diode D1, such that when it is necessary to turn off the second MOS transistor, the second MOS transistor is rapidly turned off by a voltage formed on the protection diode D3.

As shown in fig. 3, the third cell region (MN 3) includes a third gate region G3, a second source region S2 and a third drain region G2, the third cell region and the second cell region share the second source region S2, and the third drain region G2 of the third cell region and the second gate region G2 of the second cell region can be connected.

In the above embodiments, the protection diode D3 is a high voltage diode.

As shown in fig. 2 and 3, the semiconductor device further includes a substrate electrode region B. The first cell region, the second cell region, the third cell region, and the fourth cell region are formed on a common substrate (Psub).

According to one embodiment of the present disclosure, a first MOS transistor of a semiconductor device is an NMOS transistor, and a substrate is a P-type substrate (Psub); the first unit cell region (MNLV 1) comprises a first gate region G1, a first source region S1 and a first drain region D, and the first unit cell region comprises a P-type substrate and a dielectric layer; at least an N-type drift region ND is formed between the P-type substrate and the dielectric layer, a first P-type well region PW is formed in the N-type drift region ND, at least a first P-type highly-doped region P + and a first N-type highly-doped region N + are formed in the first P-type well region PW, the first P-type well region PW and the P-type substrate are spaced through the N-type drift region ND, and a second N-type highly-doped region N + is formed in the N-type drift region ND; the first source region S1 is formed on the dielectric layer, and at least one part of the first source region S1 penetrates through the dielectric layer to be in contact with the first N-type highly-doped region N + and in contact with the first P-type highly-doped region P +; the first drain electrode region D is formed on the dielectric layer, and at least one part of the first drain electrode region D penetrates through the dielectric layer to be in contact with the second N-type highly doped region N +; the first gate region G1 is formed in the dielectric layer.

The second MOS transistor is an NMOS transistor, and the substrate is a P-type substrate; the second cell region (MNHV 2) comprises a second gate region G2, a second source region S2 and a first drain region D, and the second cell region comprises a P-type substrate and a dielectric layer; at least an N-type drift region ND is formed between the P-type substrate and the dielectric layer, a second P-type well region PW is formed in the N-type drift region ND, at least a third P-type highly-doped region P + and a third N-type highly-doped region N + are formed in the second P-type well region PW, the second P-type well region PW and the P-type substrate are spaced through the N-type drift region ND, and a second N-type highly-doped region N + is formed in the N-type drift region ND; the second source region S2 is formed on the dielectric layer, and at least one part of the second source region S2 penetrates through the dielectric layer to be in contact with the third N-type highly-doped region N + and in contact with the third P-type highly-doped region P +; the first drain electrode region D is formed on the dielectric layer, and at least one part of the first drain electrode region D penetrates through the dielectric layer to be in N + contact with the second N-type highly-doped region; the second gate region G2 is formed in the dielectric layer.

The third unit cell region (MN 3) comprises a third gate region G3, a second source region S2 and a third drain region (G2), and the third unit cell region comprises a P-type substrate and a dielectric layer; at least an N-type drift region ND is formed between the P-type substrate and the dielectric layer, a third P-type well region PW is formed in the N-type drift region ND, at least a fourth P-type highly-doped region P + and a fourth N-type highly-doped region N + are formed in the third P-type well region PW, the third P-type well region PW and the P-type substrate are separated through the N-type drift region ND, and a fifth N-type highly-doped region N + is formed in the N-type drift region ND; the second source region S2 is formed on the dielectric layer, and at least one part of the second source region S2 penetrates through the dielectric layer to be in contact with the fourth N-type highly-doped region N + and in contact with the fourth P-type highly-doped region P +; the third drain electrode region G2 is formed on the dielectric layer, and at least one part of the third drain electrode region G2 penetrates through the dielectric layer to be in contact with the fifth N-type highly doped region N +; the third gate region G3 is formed in the dielectric layer.

The fourth cell region (D3) includes a first source region S1 and a second drain region D; the fourth cell area comprises a P-type substrate and a dielectric layer; at least an N-type drift region ND is formed between the P-type substrate and the dielectric layer, a fourth P-type well region PW is formed in the N-type drift region ND, at least a sixth P-type highly doped region P + is formed in the fourth P-type well region PW, the fourth P-type well region PW is separated from the P-type substrate through the N-type drift region ND, and a sixth N-type highly doped region N + is formed in the N-type drift region ND; the first source region S1 is formed on the dielectric layer, and at least one part of the first source region S1 penetrates through the dielectric layer to be in contact with the sixth P-type highly doped region P +; the second drain electrode region D is formed on the dielectric layer, and at least one part of the second drain electrode region D penetrates through the dielectric layer to be in contact with the sixth N-type highly doped region N +.

The doping concentration of the N + region is greater than that of the ND region, and the doping concentration of the P + region is greater than that of the PW region.

The source region can be made of a metal material, the dielectric layer is an oxide layer, the substrate electrode region is made of a metal material, the gate region can be made of polycrystalline silicon, the P-type high-doping region is made of P-type doped silicon, the P-type well region is made of P-type doped silicon, the N-type high-doping region is made of N-type doped silicon, the N-type well region is made of N-type doped silicon, the N-type drift region ND is made of N-type doped silicon, and the drain region can be made of a metal material.

As shown in fig. 2 and 3, in the first cell region, a first parasitic diode D1 is formed between the PW region and the ND region, in the second cell region, a second parasitic diode D2 is formed between the PW region and the ND region, and in the fourth cell region, a protection diode D3 is formed between the PW region and the ND region.

In the above embodiments, the substrate (Psub) further has a fifth P-type highly doped region P +, the substrate electrode region B is formed on the dielectric layer, and at least a portion of the substrate electrode region B passes through the dielectric layer and contacts with the fifth P-type highly doped region P +.

In the above embodiments, the MOS transistors of the semiconductor device are all NMOS transistors, and it should be understood by those skilled in the art that the MOS transistors may also be designed as PMOS transistors, and if the MOS transistors are designed as PMOS transistors, the above embodiments are "P-type" and "N-type" interchanged, so that a plurality of embodiments of semiconductor devices for battery protection switches using PMOS transistors can be formed.

In the embodiment shown in fig. 2 and 3, the region between the dielectric layer and the substrate in the first cell region and the region between the dielectric layer and the substrate in the fourth cell region are isolated by an isolation dielectric; the region between the dielectric layer of the second cell region and the substrate and the region between the dielectric layer of the third cell region and the substrate are isolated through an isolation medium; and the region between the dielectric layer of the third unit cell region and the substrate and the doped region between the electrode region of the substrate and the substrate are isolated by an isolation medium.

Wherein, the isolation medium can adopt an oxide layer.

In fig. 4, the region between the dielectric layer of the first cell region and the substrate and the region between the dielectric layer of the fourth cell region and the substrate are isolated by a PN junction; the region between the dielectric layer of the second cell region and the substrate and the region between the dielectric layer of the third cell region and the substrate are isolated through PN junctions; and the region between the dielectric layer of the third unit cell region and the substrate and the doped region between the electrode region of the substrate and the substrate are isolated through a PN junction.

A PN junction is formed between the region between the dielectric layer of the first cell region and the substrate and the region between the dielectric layer of the fourth cell region and the substrate by extending the region extending from the substrate (Psub) in the drift region and extending to the dielectric layer; PN junctions are formed between the area between the dielectric layer of the second cell area and the substrate and the area between the dielectric layer of the third cell area and the substrate; PN junctions are formed between the area between the dielectric layer of the third unit cell area and the substrate and the doped area between the electrode area of the substrate and the substrate.

The device structure in fig. 5 employs a Loscos structure design.

The device structure in fig. 6 employs a RESURF structure design.

Fig. 7 is a schematic structural diagram of a semiconductor device for a battery protection switch according to still another embodiment of the present disclosure.

A partial structure of a semiconductor device for a battery protection switch of one embodiment is shown in fig. 7, which includes a structure of a first cell region (MNLV 1) and a second cell region (MNHV 2).

A partial structure of a semiconductor device for a battery protection switch of one embodiment, including a structure of a first cell region (MNLV 1) and a second cell region (MNHV 2), is shown in fig. 8.

A partial structure of a semiconductor device for a battery protection switch of one embodiment is shown in fig. 9, which includes a structure of a first cell region (MNLV 1) and a second cell region (MNHV 2).

As shown in fig. 7, VDMOS design is adopted for the first cell region (MNLV 1) and the second cell region (MNHV 2).

As shown in fig. 7, the first unit cell region includes a first source region S1, a drain region D and a first gate region G1, an N-type highly doped region N + is formed on the drain region D, an N-type drift region is formed on the N-type highly doped region N +, a P-type well region is formed in the N-type drift region, a P-type highly doped region is formed in the P-type well region, an N-type highly doped region is formed on the P-type well region, the first unit cell region further includes a dielectric layer, and at least a portion of the first source region S1 sequentially passes through the dielectric layer and the N-type highly doped region and then contacts with the P-type highly doped region; two isolation medium regions are symmetrically formed in the P-type well region, and a first gate region G1 is formed in each isolation medium region.

The second cell area comprises a second source electrode area S2, a drain electrode area D and a second gate electrode area G2, an N-type high-doping area N + is formed on the drain electrode area D, an N-type drift area is formed on the N-type high-doping area N +, a P-type well area is formed in the N-type drift area, a P-type high-doping area is formed in the P-type well area, an N-type high-doping area is formed on the P-type well area, the second cell area further comprises a dielectric layer, and at least one part of the second source electrode area S2 sequentially penetrates through the dielectric layer and the N-type high-doping area and then contacts with the P-type high-doping area; two isolation medium regions are symmetrically formed in the P-type well region, and a second gate region G2 is formed in each isolation medium region.

As shown in fig. 7, the first cell region and the second cell region share the dielectric layer, the drain region and the N-type highly doped region N +.

Preferably, at least one isolation medium region is formed between the P-type well region PW of the first cell region and the P-type well region PW of the second cell region, and a metal floating region is formed in the isolation medium region.

Preferably, at least one isolation medium region is formed between the P-type well region PW of at least the first cell region and the P-type well region PW of the fourth cell region, and a metal floating region is formed in the isolation medium region.

Preferably, the thickness of the drift region ND of the first cell region (MNLV 1) is smaller than the thickness of the drift region ND of the second cell region (MNHV 2), so that the first MOS transistor formed of the first cell region has a low withstand voltage performance and the second MOS transistor formed of the second cell region has a high withstand voltage performance.

The first gate region G1 and the second gate region G2 in fig. 7 are both trench gate structures.

The first gate region G1 and the second gate region G2 in fig. 8 are both split trench gate structures.

In fig. 9, the first cell region and the second cell region both adopt a super junction structure.

In the embodiments shown in fig. 7 to 9, the MOS transistors of the semiconductor device are all NMOS transistors, and it should be understood by those skilled in the art that the MOS transistors may also be designed as PMOS transistors, and if the MOS transistors are designed as PMOS transistors, the "P type" and the "N type" in the embodiments shown in fig. 7 to 9 are interchanged, so that a plurality of embodiments of semiconductor devices for a battery protection switch using PMOS transistors may be formed.

It should be understood by those skilled in the art that the sizes and shapes of the D region, the N + region, the ND region, the PW region, the G region, the S region, the B region, the N + region, the P + region, the dielectric layer, the isolation dielectric, etc. in the above embodiments are all exemplary, and those skilled in the art can appropriately adjust the sizes and shapes, and fall within the protection scope of the present disclosure.

It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.

Claims

1. A semiconductor device for a battery protection switch, comprising:

the first cell area is provided with a first MOS transistor, and the first MOS transistor receives a first control signal to enable the first MOS transistor to be switched on or switched off;

a second cell region formed with a second MOS transistor that receives a second control signal to turn on or off the second MOS transistor, the first cell region being disposed adjacent to the second cell region; and

a third cell area disposed adjacent to the second cell area, the third cell area being formed with a switch that receives a third control signal to control: when the first MOS transistor is turned off, the switch is turned on to turn off the second MOS transistor before the first MOS transistor is turned off or simultaneously with the first MOS transistor being turned off.

2. The semiconductor device of claim 1, wherein the first cell region comprises a first gate region, a first source region, and a first drain region, wherein a first parasitic diode is formed in the first cell region, and wherein the first parasitic diode is formed between the first source region and the first drain region.

3. The semiconductor device of claim 2, wherein the second cell region comprises a second gate region, a second source region, and a first drain region, wherein a second parasitic diode is formed in the second cell region, wherein the second parasitic diode is formed between the second source region and the first drain region.

4. The semiconductor device according to claim 3, wherein the first parasitic diode and the second parasitic diode constitute an inverse series structure, and the first cell region and the second cell region share the first drain region.

5. The semiconductor device according to claim 3, further comprising a fourth cell region disposed adjacent to the first cell region, the fourth cell region having a protection diode formed therein, the fourth cell region including a first source region and a second drain region, the fourth cell region sharing a first source region with the first cell region, the first drain region of the first cell region and the second drain region of the fourth cell region being connectable such that the protection diode is connected in parallel with the first parasitic diode such that the second MOS transistor is rapidly turned off by a voltage formed across the protection diode when the second MOS transistor is required to be turned off.

6. The semiconductor device of claim 5, wherein the third cell region comprises a third gate region, a second source region, and a third drain region, the third cell region and the second cell region sharing the second source region, the third drain region of the third cell region and the second gate region of the second cell region being connectable.

7. The semiconductor device according to claim 5, wherein the protection diode is a high-voltage diode.

8. The semiconductor device according to claim 6, further comprising a substrate electrode region, wherein the first cell region, the second cell region, the third cell region, and the fourth cell region are formed on a common substrate.

9. The semiconductor device according to claim 8, wherein the first MOS transistor is an NMOS transistor, and the substrate is a P-type substrate;

the first unit cell region comprises a first gate region, a first source region and a first drain region, and the first unit cell region comprises a P-type substrate and a dielectric layer;

at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a first P-type well region is formed in the N-type drift region, at least a first P-type high-doping region and a first N-type high-doping region are formed in the first P-type well region, the first P-type well region and the P-type substrate are spaced through the N-type drift region, and a second N-type high-doping region is formed in the N-type drift region;

the first source region is formed on the dielectric layer, and at least one part of the first source region penetrates through the dielectric layer to be in contact with the first N-type high-doping region and the first P-type high-doping region;

the first drain electrode region is formed on the dielectric layer, and at least one part of the first drain electrode region penetrates through the dielectric layer to be in contact with the second N-type high-doping region;

the first gate region is formed in the dielectric layer.

10. The semiconductor device according to any one of claims 1 to 3, wherein the second MOS transistor is an NMOS transistor, and the substrate is a P-type substrate;

the second cell area comprises a second gate area, a second source area and a first drain area, and the second cell area comprises a P-type substrate and a dielectric layer;

at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a second P-type well region is formed in the N-type drift region, at least a third P-type highly-doped region and a third N-type highly-doped region are formed in the second P-type well region, the second P-type well region and the P-type substrate are spaced through the N-type drift region, and a second N-type highly-doped region is formed in the N-type drift region;

the second source region is formed on the dielectric layer, and at least one part of the second source region penetrates through the dielectric layer to be in contact with the third N-type high-doping region and the third P-type high-doping region;

the second gate region is formed in the dielectric layer.

11. The semiconductor device of claim 6, wherein the third cell region comprises a third gate region, a second source region, and a third drain region, and the third cell region comprises a P-type substrate and a dielectric layer;

at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a third P-type well region is formed in the N-type drift region, at least a fourth P-type highly-doped region and a fourth N-type highly-doped region are formed in the third P-type well region, the third P-type well region and the P-type substrate are spaced through the N-type drift region, and a fifth N-type highly-doped region is formed in the N-type drift region;

the second source region is formed on the dielectric layer, and at least one part of the second source region penetrates through the dielectric layer to be in contact with the fourth N-type high-doping region and the fourth P-type high-doping region;

the third drain electrode region is formed on the dielectric layer, and at least one part of the third drain electrode region penetrates through the dielectric layer to be in contact with the fifth N-type high-doping region;

the third gate region is formed in the dielectric layer.

12. The semiconductor device of claim 5, wherein the fourth cell region comprises a first source region and a second drain region; the fourth cell area comprises a P-type substrate and a dielectric layer;

at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a fourth P-type well region is formed in the N-type drift region, at least a sixth P-type highly-doped region is formed in the fourth P-type well region, the fourth P-type well region is spaced from the P-type substrate through the N-type drift region, and a sixth N-type highly-doped region is formed in the N-type drift region;

the first source region is formed on the dielectric layer, and at least one part of the first source region penetrates through the dielectric layer to be in contact with the sixth P-type high-doping region;

the second drain region is formed on the dielectric layer, and at least one part of the second drain region penetrates through the dielectric layer to be in contact with the sixth N-type highly doped region.

13. The semiconductor device of claim 9, wherein a fifth P-type highly doped region is further formed on the substrate, the substrate electrode region is formed on the dielectric layer, and at least a portion of the substrate electrode region contacts the fifth P-type highly doped region through the dielectric layer.

14. The semiconductor device according to claim 1, wherein the first MOS transistor is a PMOS transistor, and the substrate is an N-type substrate;

the first unit cell region comprises a first gate region, a first source region and a first drain region, and the first unit cell region comprises an N-type substrate and a dielectric layer;

at least a P-type drift region is formed between the N-type substrate and the dielectric layer, a first N-type well region is formed in the P-type drift region, at least a first N-type high-doping region and a first P-type high-doping region are formed in the first N-type well region, the first N-type well region and the N-type substrate are separated by the P-type drift region, and a second P-type high-doping region is formed in the P-type drift region;

the first source region is formed on the dielectric layer, and at least one part of the first source region penetrates through the dielectric layer to be in contact with the first P-type highly-doped region and the first N-type highly-doped region;

the first drain electrode region is formed on the dielectric layer, and at least one part of the first drain electrode region penetrates through the dielectric layer to be in contact with the second P-type high-doping region;

the first gate region is formed in the dielectric layer.

15. The semiconductor device according to claim 1, wherein the second MOS transistor is a PMOS transistor, and wherein the substrate is an N-type substrate;

the second cell area comprises a second gate area, a second source area and a first drain area, and the second cell area comprises an N-type substrate and a dielectric layer;

at least a P-type drift region is formed between the N-type substrate and the dielectric layer, a second N-type well region is formed in the P-type drift region, at least a third N-type highly-doped region and a third P-type highly-doped region are formed in the second N-type well region, the second N-type well region and the N-type substrate are separated through the P-type drift region, and a second P-type highly-doped region is formed in the P-type drift region;

the second source region is formed on the dielectric layer, and at least one part of the second source region penetrates through the dielectric layer to be in contact with the third P-type high-doping region and the third N-type high-doping region;

the first drain electrode region is formed on the dielectric layer, and at least one part of the first drain electrode region penetrates through the dielectric layer to be in contact with the second P-type highly doped region;

the second gate region is formed in the dielectric layer.

16. The semiconductor device of claim 6, wherein the third cell region comprises a third gate region, a second source region, and a third drain region, the third cell region comprising an N-type substrate and a dielectric layer;

at least a P-type drift region is formed between the N-type substrate and the dielectric layer, a third N-type well region is formed in the P-type drift region, at least a fourth N-type highly-doped region and a fourth P-type highly-doped region are formed in the third N-type well region, the third N-type well region and the N-type substrate are separated by the P-type drift region, and a fifth P-type highly-doped region is formed in the P-type drift region;

the second source region is formed on the dielectric layer, and at least one part of the second source region penetrates through the dielectric layer to be in contact with the fourth P-type high-doping region and the fourth N-type high-doping region;

the third drain electrode region is formed on the dielectric layer, and at least one part of the third drain electrode region penetrates through the dielectric layer to be in contact with the fifth P-type high-doping region;

the third gate region is formed in the dielectric layer.

17. The semiconductor device of claim 5, wherein the fourth cell region comprises a first source region and a second drain region; the fourth cell area comprises an N-type substrate and a dielectric layer;

at least a P-type drift region is formed between the N-type substrate and the dielectric layer, a fourth N-type well region is formed in the P-type drift region, at least a sixth N-type highly doped region is formed in the fourth N-type well region, the fourth N-type well region is separated from the N-type substrate through the P-type drift region, and a sixth P-type highly doped region is formed in the P-type drift region;

the first source region is formed on the dielectric layer, and at least one part of the first source region penetrates through the dielectric layer to be in contact with the sixth N-type high-doping region;

the second drain region is formed on the dielectric layer, and at least one part of the second drain region penetrates through the dielectric layer to be in contact with the sixth P-type highly doped region.

18. The semiconductor device of claim 9, wherein a fifth highly N-doped region is further formed on the substrate, the substrate electrode region being formed on the dielectric layer, at least a portion of the substrate electrode region being in contact with the fifth highly N-doped region through the dielectric layer.

19. The semiconductor device according to claim 17, wherein a region between the dielectric layer and the substrate of the first cell region and a region between the dielectric layer and the substrate of the fourth cell region are isolated by a PN junction;

the region between the dielectric layer and the substrate of the second cell region and the region between the dielectric layer and the substrate of the third cell region are isolated through PN junctions;

and the region between the dielectric layer of the third unit cell region and the substrate and the doped region between the electrode region of the substrate and the substrate are isolated through a PN junction.

20. The semiconductor device according to claim 17, wherein a region between the dielectric layer of the first cell region and the substrate and a region between the dielectric layer of the fourth cell region and the substrate are isolated by an isolation dielectric;

the region between the dielectric layer of the second cell region and the substrate and the region between the dielectric layer of the third cell region and the substrate are isolated through an isolation dielectric;

and the region between the dielectric layer of the third unit cell region and the substrate and the doped region between the electrode region of the substrate and the substrate are isolated by an isolation medium.

21. The semiconductor device according to claim 5, wherein the first cell region comprises a first source region, a drain region and a first gate region, wherein an N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a P-type well region is formed in the N-type drift region, a P-type highly doped region is formed in the P-type well region, an N-type highly doped region is formed on the P-type well region, the first cell region further comprises a dielectric layer, and at least a part of the first source region sequentially passes through the dielectric layer and the N-type highly doped region and then contacts with the P-type highly doped region;

two isolation medium regions are symmetrically formed in the P-type well region, and one first gate region is formed in each isolation medium region.

22. The semiconductor device of claim 21, wherein the second cell region comprises a second source region, a drain region and a second gate region, wherein an N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a P-type well region is formed in the N-type drift region, a P-type highly doped region is formed in the P-type well region, an N-type highly doped region is formed on the P-type well region, the second cell region further comprises a dielectric layer, and at least a portion of the second source region sequentially passes through the dielectric layer and the N-type highly doped region and then contacts the P-type highly doped region;

two isolation medium regions are symmetrically formed in the P-type well region, and one second gate region is formed in each isolation medium region.

23. The semiconductor device of claim 22, wherein the first cell region and the second cell region share the dielectric layer, a drain region, and an N-type highly doped region.

24. The semiconductor device of claim 23, wherein at least one isolation dielectric region is formed between the P-type well region of the first cell region and the P-type well region of the second cell region, and wherein a metal floating region is formed in the isolation dielectric region.

25. The semiconductor device of claim 24, wherein at least one isolation dielectric region is formed between the P-type well region of the first cell region and the P-type well region of the fourth cell region, and wherein a metal floating region is formed in the isolation dielectric region.

26. The semiconductor device of any one of claims 22 to 25, wherein the first gate region and the second gate region are both trench gate structures.

27. The semiconductor device of any one of claims 22 to 25, wherein the first gate region and the second gate region are both split trench gate structures.

28. The semiconductor device according to any one of claims 22 to 25, wherein the first cell region and the second cell region each employ a super junction structure.

29. The semiconductor device according to claim 5, wherein the first cell region comprises a first source region, a drain region and a first gate region, a P-type highly doped region is formed on the drain region, a P-type drift region is formed on the P-type highly doped region, an N-type well region is formed in the P-type drift region, an N-type highly doped region is formed in the N-type well region, a P-type highly doped region is formed on the N-type well region, the first cell region further comprises a dielectric layer, and at least a portion of the first source region sequentially passes through the dielectric layer and the P-type highly doped region and then contacts the N-type highly doped region;

two isolation medium regions are symmetrically formed in the N-type well region, and one first gate region is formed in each isolation medium region.

30. The semiconductor device of claim 29, wherein the second cell region comprises a second source region, a drain region and a second gate region, wherein a P-type heavily doped region is formed on the drain region, a P-type drift region is formed on the P-type heavily doped region, an N-type well region is formed in the P-type drift region, an N-type heavily doped region is formed in the N-type well region, a P-type heavily doped region is formed on the N-type well region, the second cell region further comprises a dielectric layer, and at least a portion of the second source region sequentially passes through the dielectric layer and the P-type heavily doped region and then contacts the N-type heavily doped region;

two isolation medium regions are symmetrically formed in the N-type well region, and one second gate region is formed in each isolation medium region.

31. The semiconductor device of claim 30, wherein the first cell region and the second cell region share the dielectric layer, a drain region, and a P-type highly doped region.

32. The semiconductor device of claim 31, wherein at least one isolation dielectric region is formed between the N-type well region of the first cell region and the N-type well region of the second cell region, and wherein a metal floating region is formed in the isolation dielectric region.

33. The semiconductor device of claim 32, wherein at least one isolation dielectric region is formed between the N-type well region of the first cell region and the N-type well region of the fourth cell region, and wherein a metal floating region is formed in the isolation dielectric region.

34. The semiconductor device of any one of claims 30 to 33, wherein the first gate region and the second gate region are both trench gate structures.

35. The semiconductor device of any one of claims 30 to 33, wherein the first gate region and the second gate region are both split trench gate structures.

36. The semiconductor device according to any one of claims 1 to 8, wherein a thickness of a drift region of the first cell region is smaller than a thickness of a drift region of the second cell region, so that the first MOS transistor formed by the first cell region has low withstand voltage performance and the second MOS transistor formed by the second cell region has high withstand voltage performance.