CN114020679A - I2C bus control circuit and circuit system for ship - Google Patents
I2C bus control circuit and circuit system for ship Download PDFInfo
- Publication number
- CN114020679A CN114020679A CN202111338596.2A CN202111338596A CN114020679A CN 114020679 A CN114020679 A CN 114020679A CN 202111338596 A CN202111338596 A CN 202111338596A CN 114020679 A CN114020679 A CN 114020679A
- Authority
- CN
- China
- Prior art keywords
- signal
- resistor
- bus
- control circuit
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012937 correction Methods 0.000 claims abstract description 21
- 238000012544 monitoring process Methods 0.000 claims description 22
- 238000012545 processing Methods 0.000 claims description 13
- 230000002159 abnormal effect Effects 0.000 claims description 11
- 230000005540 biological transmission Effects 0.000 abstract description 13
- 230000009467 reduction Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 11
- 230000005856 abnormality Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000003862 health status Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention provides an I2C bus interface control circuit and a circuit system for a ship, wherein the I2C bus interface control circuit comprises: the bus driving unit divides a data transmission link between the master device and the slave device into a sending link and a receiving link, monitors the level of a feedback signal sent from the slave device to the master device, and transmits the feedback signal sent from the slave device to the master device on the receiving link of the bus driving unit after data correction, so that wrong data acquisition caused by the reduction of the I2C bus level is avoided, and the safety and reliability of the whole circuit system are guaranteed.
Description
Technical Field
The invention relates to the technical field of I2C integrated circuits, in particular to an I2C bus control circuit and a circuit system for a ship.
Background
An Inter Integrated Circuit (I2C) bus is a simple bidirectional two-wire synchronous Serial bus, and includes two signal lines, namely a Serial Data (SDA) line and a Serial Clock (SCL) line. The SDA lines of all the devices accessing the I2C bus are connected to the SDA line of the I2C bus, and the SCL lines of all the devices accessing the I2C bus are connected to the SCL line of the I2C bus.
The devices accessing the I2C bus include at least one I2C master and at least one I2C slave. The I2C master device is a device configured in the master mode, and can initialize transmission, generate a clock signal and terminate transmission, namely control data transmission of the I2C bus; and the I2C slave is a device configured in slave mode, addressed by the I2C master when the I2C bus is transmitting data.
The I2C bus is widely applied to the design of electronic devices of automatic control systems of ships, and in practice, it is found that the level transmitted on the data line of the I2C bus of the I2C chip is continuously reduced in a period of a critical state just before the chip is damaged, which results in data analysis errors at the receiving end of the main device, and the errors cannot be avoided by software, and the errors have a great influence on the reliable operation of the circuit system and the electronic devices controlled by the I2C bus.
Therefore, it is necessary to provide an I2C bus control circuit and a circuit system for a ship, so as to overcome the above-mentioned drawbacks, and to realize data correction when an I2C bus level is abnormal, so as to ensure the safety and reliability of the whole circuit system.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide an I2C bus control circuit and a circuit system for a ship, so as to solve the problem of error data acquisition caused by abnormal I2C bus level in the prior art.
The purpose of the invention is realized by adopting the following technical scheme:
according to an aspect of the present invention, there is provided a semiconductor device including: a bus driving unit connected on an I2C bus between a master device and a slave device, the master device and the slave device communicating via the I2C bus, wherein the bus driving unit directly transmits a data signal output by the master device to the slave device via a data line of the I2C bus and directly transmits a clock signal output by the master device to the slave device via a clock line of the I2C bus; a level monitoring unit electrically connected to the data line of the I2C bus to receive a feedback signal sent by the slave device to the master device and to output a first signal and a second signal based on the feedback signal, the first signal and the second signal reflecting the feedback signal and a voltage range thereof; a data correction unit electrically connected with the bus driving unit and the level monitoring unit, respectively, to receive the first signal and the second signal, and to generate a corrected feedback signal based on the first signal and the second signal, and to transmit the corrected feedback signal to the master device via the bus driving unit.
Further, the bus driving unit reinforces the corrected feedback signal and transmits the reinforced feedback signal to the master device.
Further, the control circuit further comprises an alarm processing unit, wherein the alarm processing unit is electrically connected with the level monitoring unit to receive the first signal and the second signal and generate an alarm signal based on the first signal and the second signal to trigger an upper computer to implement alarm operation.
Further, the level monitoring unit includes a first comparator and a second comparator, the first comparator and the second comparator each have a positive input terminal and a negative input terminal, and the positive input terminals of the first comparator and the second comparator are used for receiving the feedback signal;
the negative input end of the first comparator is connected to an intermediate node formed by connecting a third resistor and a fourth resistor in series, and the third resistor and the fourth resistor are connected between a power supply and the ground in series so as to input the voltage divided by the third resistor and the fourth resistor to the negative input end of the first comparator; the negative input end of the second comparator is connected to an intermediate node formed by connecting a sixth resistor and a seventh resistor in series, and the sixth resistor and the seventh resistor are connected between a power supply and the ground in series so as to input the voltage divided by the sixth resistor and the seventh resistor to the negative input end of the second comparator; wherein the output terminal of the first comparator outputs the first signal, and the output terminal of the second comparator outputs the second signal.
Further, the level monitoring unit further comprises a first resistor, a second resistor and a fifth resistor; the first end of the first resistor is connected with a power supply, and the second end of the first resistor is electrically connected with a data line for transmitting the feedback signal; a first end of the second resistor is connected with a power supply, and a second end of the second resistor is electrically connected with an output end of the first comparator for outputting the first signal; and a first end of the fifth resistor is connected with a power supply, and a second end of the fifth resistor is electrically connected with an output end of the second comparator for outputting the second signal.
Further, the data correction unit includes a logic or gate, two input terminals of the logic or gate respectively receive the first signal and the second signal, and an output terminal of the logic or gate outputs the corrected feedback signal.
Further, the alarm processing unit includes a logic exclusive or gate, two input ends of the logic exclusive or gate respectively receive the first signal and the second signal, and an output end of the logic exclusive or gate outputs the alarm signal.
Further, the values of the first signal and the second signal reflect a voltage range of the feedback signal, wherein the voltage range includes a normal region, an abnormal early warning region, and a failure region.
Further, the alarm signal triggers the upper computer to alarm when the logic level value of the alarm signal is '1', and the alarm signal does not trigger the upper computer to alarm when the logic level value of the alarm signal is '0'.
According to another aspect of the invention there is also provided circuitry for a marine vessel, the circuitry comprising the I2C bus control circuit described above.
Compared with the prior art, the I2C bus control circuit and the circuit system for the ship provided by the embodiment of the invention, wherein the I2C bus interface control circuit comprises: the bus driving unit divides a data transmission link between the master device and the slave device into a sending link and a receiving link, monitors the level of a feedback signal sent from the slave device to the master device, and transmits the feedback signal sent from the slave device to the master device on the receiving link of the bus driving unit after data correction, so that wrong data acquisition caused by the reduction of the I2C bus level is avoided, and the safety and reliability of the whole circuit system are guaranteed.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a block diagram of an overall structure of an I2C bus control circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of an overall structure of another I2C bus control circuit according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of the bus driver of FIG. 1;
FIG. 4 is a schematic circuit diagram of the level monitor unit of FIG. 1;
FIG. 5 is a schematic circuit diagram of the data correction unit in FIG. 1;
fig. 6 is a schematic circuit diagram of the alarm processing unit in fig. 2;
FIG. 7 is a schematic diagram of a simulation of slave device data level voltage value anomalies;
FIG. 8 is a schematic diagram of a simulation of a data level voltage value anomaly of yet another slave device.
Detailed Description
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Fig. 1 is a block diagram of an overall structure of an I2C bus control circuit according to an embodiment of the present invention, fig. 3 is a schematic circuit structure of a bus driving unit in fig. 1, fig. 4 is a schematic circuit structure of a level monitoring unit in fig. 1, and fig. 5 is a schematic circuit structure of a data correcting unit in fig. 1.
Referring to fig. 1, 3-5, the present invention provides an I2C bus control circuit 100, comprising: a bus driving unit 50, a level monitoring unit 60, and a data correcting unit 70; the bus driving unit 50 is connected on an I2C bus between a master device 1 and a slave device 2, the master device 1 and the slave device 2 communicating via the I2C bus, wherein the bus driving unit 50 directly transmits a data signal output by the master device 1 to the slave device 2 via a data line 3 of the I2C bus and directly transmits a clock signal output by the master device 1 to the slave device 2 via a clock line 4 of the I2C bus; a level monitoring unit 60, wherein the level monitoring unit 60 is electrically connected with the data line 3 of the I2C bus to receive a feedback signal sent by the slave device 2 to the master device 1, and outputs a first signal 61 and a second signal 62 based on the feedback signal, and the first signal 61 and the second signal 62 reflect the feedback signal and the level range thereof; the data correction unit 70 is electrically connected to the bus driving unit 50 and the level monitoring unit 60 to receive the first signal 61 and the second signal 62, respectively, and generates a corrected feedback signal based on the first signal 61 and the second signal 62, and transmits the corrected feedback signal to the master device 1 via the bus driving unit 50.
In the prior art, when data is transmitted by an I2C bus, data is transmitted on the same data line (SDA line) between a master device and a slave device, and a data signal is sent from the master device to the slave device and a response signal is fed back from the slave device to the master device in different time slots by matching with clock pulses of a clock signal line (SCL line); for example, each time the master device 1 sends a byte, the data line (SDA line) is released during the 9 th clock pulse, and then an acknowledge signal is fed back by the slave device, which when low is defined as a valid acknowledge bit (ACK) indicating that the slave device has successfully received the byte; when the acknowledge signal is high, a non-acknowledge bit (NACK) is specified, generally indicating that the slave device has not successfully received the byte. The slave device transmits a NACK signal after receiving the last byte to control the master device to end data transmission and release the data line (SDA line) so that the master device 1 transmits a stop signal. After releasing the I2C bus, the level on the data line (SDA line) should remain high if there is no acknowledge signal.
In the embodiment of the present invention, however, the bus driving unit 50 divides the data transmission link between the master device 1 and the slave device 2 in the I2C bus into a transmitting link and a receiving link, the transmitting link is configured to transmit a transmitting signal (data signal) sent by the Master device 1 to the Slave device 2, the receiving link is configured to transmit a receiving signal (feedback signal) sent by the Slave device 2 to the Master device 1, the data signal (SDA _ Master) sent by the Master device 1 on the data line 3 is converted into (SDA _ Master _ Tx) via the bus driving unit 50 and directly transmitted to the SDA interface of the Slave device 2 on the transmitting link of the bus driving unit 50, and the feedback signal (SDA _ Rx _ Slave) sent by the Slave device 2 to the Master device 1 passes through the level monitoring unit 60 and the data correcting unit 70 and is transmitted to the SDA interface of the Master device 1 on the receiving link of the bus driving unit 50. A clock signal (SCL _ Master) sent by the Master device 1 on the clock line 4 passes through the bus driving unit 50 and is then directly sent to the SCL interface of the slave device 2.
Wherein the level monitoring unit 60 outputs two signals (a first signal 61 and a second signal 62) based on receiving a feedback signal (SDA _ Rx _ Slave) transmitted from the Slave device 2 to the master device 1, and then inputs the two signals into the data correction unit 70.
Wherein the data correction unit 70 is electrically connected to the bus driving unit 50 and the level monitoring unit 60, respectively, i.e. the data correction unit 70 is electrically connected between the bus driving unit 50 and the level monitoring unit 60, the data correction unit 70 outputs a corrected feedback signal (SDA _ Slave _ OR) based on the received first signal 61 and second signal 62, and transmits the corrected feedback signal (SDA _ Slave _ OR) to the master device 1 on the receiving link of the bus driving unit 50.
The I2C bus control circuit provided by the embodiment of the present invention, wherein the I2C bus interface control circuit includes: the bus driving unit divides a data transmission link between the master device and the slave device into a sending link and a receiving link, monitors the level of a feedback signal sent from the slave device to the master device, and transmits the feedback signal sent from the slave device to the master device on the receiving link of the bus driving unit after data correction, so that wrong data acquisition caused by the reduction of the I2C bus level is avoided, and the safety and reliability of the whole circuit system are guaranteed.
Further, the bus driving unit 50 boosts the corrected feedback signal and transmits the boosted feedback signal to the master device 1.
Fig. 2 is a block diagram of an overall structure of another I2C bus control circuit according to an embodiment of the present invention. As shown in fig. 2, the control circuit 100 further includes an Alarm processing unit 80, and the Alarm processing unit 80 is electrically connected to the level monitoring unit 60 to receive the first signal 61 and the second signal 62, and generate an Alarm signal (I2C Alarm) based on the first signal 61 and the second signal 62 to trigger the upper computer 9 to perform an Alarm operation. If the electrical level is abnormal, the electrical level output by the alarm processing unit 80 is inverted to feed back the health status of the current I2C bus data level transmission to the outside, the upper computer 9 is used for receiving and displaying the abnormal status, and meanwhile, corresponding alarm operation processing can be implemented through the operation interface of the upper computer 9, such as timely cutting off the I2C bus circuit or replacing the I2C bus chip.
Referring to fig. 4, the level monitoring unit 60 includes a first comparator 63 and a second comparator 64, the first comparator 63 and the second comparator 64 each have a positive input terminal and a negative input terminal, and the positive input terminals of the first comparator 63 and the second comparator 63 are used for receiving the feedback signal (SDA _ Rx _ Slave); the negative input end of the first comparator 63 is connected to a middle node of a series connection of a third resistor R3 and a fourth resistor R4, the third resistor R3 and the fourth resistor R4 are connected in series and then electrically connected between a power supply (VCC, D5V) and Ground (GND), so that the voltage divided by the third resistor R3 and the fourth resistor R4 is input to the negative input end of the first comparator 63; the negative input end of the second comparator 64 is connected to the middle node of the sixth resistor R6 and the seventh resistor R7 after being connected in series, and the sixth resistor R6 and the seventh resistor R7 are connected in series and then electrically connected between the power supply (VCC, D5V) and the Ground (GND), so that the voltage divided by the sixth resistor R6 and the seventh resistor R7 is input to the negative input end of the second comparator 64; wherein an output terminal of the first comparator 63 outputs the first signal 61, and an output terminal of the second comparator 64 outputs the second signal 62.
Illustratively, the voltage divided by the third resistor R3 and the fourth resistor R4 is VH, and is calculated according to the voltage dividing resistors: voltage value of VH
VCC is working voltage, the effective value is 5V, and the minimum effective value of VH obtained by calculation is 4.3V; the voltage after voltage division by the sixth resistor R6 and the seventh resistor R7 is VL, and is calculated according to the voltage division resistors to obtain: voltage value of VL of
Here, VCC is an operating voltage, and the effective value is 5V, and the minimum effective value of VL is 3.5V by calculation.
When the logic high level of the feedback signal (SDA _ Rx _ Slave) output from the Slave device 2 to the master device 1 is between 4.7V and 5V, the communication on the I2C bus is maintained to be normal. When the chip performance of the Slave device 2 is degraded, which causes the logic high level of the feedback signal (SDA _ Rx _ Slave) output to the master device 1 to be degraded, the minimum value of the logic high level of the feedback signal that the master device 1 can receive is VCC × 0.7 — 3.5V, so that when the voltage value of the feedback signal (SDA _ Rx _ Slave) is lower than the VH minimum effective value of the negative input terminal of the first comparator 63 is 4.3V, the output terminal of the first comparator 63 outputs an incorrect level, and at this time, the output terminal of the first comparator 63 outputs a low level signal to the data correction unit 70; and since the VL minimum effective value of the negative input terminal of the second comparator 64 is 3.5V, when the voltage value of the feedback signal (SDA _ Rx _ Slave) output from the Slave device 2 to the master device 1 is greater than the VL minimum effective value of the negative input terminal of the second comparator 64 is 3.5V, the waveform output from the output terminal of the second comparator 64 will be consistent with the logic high level of the feedback signal (SDA _ Rx _ Slave) output from the Slave device 2 to the master device 1, and at this time, the output terminal of the second comparator 64 will output a high-level signal to the data correction unit 70.
With continued reference to fig. 4, the feedback signal (SDA _ Rx _ Slave) output from the Slave device 2 to the master device 1 is also connected to the transmission signal (SDA _ Slave _ Tx) on the transmission link of the bus driving unit 50 for comparison with the reference voltage.
The level monitoring unit 60 further includes a first resistor R1, a second resistor R2, and a fifth resistor R5; a first end of the first resistor R1 is connected with a power supply, and a second end of the first resistor R1 is electrically connected with a data line for transmitting the feedback signal; a first terminal of the second resistor R2 is connected to a power supply, and a second terminal of the second resistor R2 is electrically connected to an output terminal of the first comparator 63 for outputting the first signal; a first terminal of the fifth resistor R5 is connected to a power supply, and a second terminal of the fifth resistor R5 is electrically connected to an output terminal of the second comparator 64 for outputting the second signal. The first resistor R1, the second resistor R2 and the fifth resistor R5 are pull-up resistors, and data line transmission on the I2C bus is in an open collector or open drain structure, so that only 0 can be output and 1 cannot be output, and therefore, the power supply needs to be connected through the pull-up resistors, so that when the data line on the I2C bus outputs a low level, the pull-up resistors are always in a working state.
According to the logic level range of the feedback signal (SDA _ Rx _ Slave) output from the Slave device 2 to the master device 1, the I2C bus is divided into three ranges, namely a normal area (the voltage range is 4.3V-5V), an abnormal early warning area (the voltage range is 3.5V-4.3V) and a failure area (the voltage range is 0-3.5V). In these three ranges, the output levels of the first comparator 63 and the second comparator 64 have corresponding variations, and the results are shown in the following table. Since the output terminal of the first comparator 63 and the output terminal of the second comparator 64 are electrically connected to the pull-up resistor R2 and the pull-up resistor R5, respectively, the output level thereof is 5V when the feedback signal is not input.
Table I, voltage range and judgment conclusion of I2C bus feedback signal
With continued reference to fig. 5, the data correction unit 70 comprises a logic OR gate 71, two inputs of the logic OR gate 71 respectively receive the first signal 61 and the second signal 62, and an output of the logic OR gate 71 outputs the corrected feedback signal (SDA _ Slave _ OR).
Illustratively, the outputs of the first comparator 63 and the second comparator 64, the first signal 61(Y _ A) and the second signal 62(Y _ B), are input to two inputs of a logic OR gate 71, according to the formula of "or", when the logic high level of the feedback signal (SDA _ Rx _ Slave) output from the Slave device 2 to the master device 1 is in the two ranges of 4.3V to 5V (in the normal region) and 3.5V to 4.3V (in the abnormality warning region), the output result of the output terminal of the first comparator 63 and the output result of the output terminal of the second comparator 64 can both restore the logic level of the feedback signal (SDA _ Rx _ Slave) output from the Slave device 2 to the master device 1 after performing an exclusive or operation, that is, the output high level voltage value is 5V, and after data correction is performed by the data correction unit 70, both the logic value and the level value of data entering the I2C master device are corrected to correct values.
Referring to fig. 6, the alarm processing unit 80 includes a logic exclusive or gate 81, two inputs of the logic exclusive or gate 81 respectively receive the first signal 61 and the second signal 62, and an output of the logic exclusive or gate 81 outputs the alarm signal.
Illustratively, the outputs of the first comparator 63 and the second comparator 64, the first signal 61(Y _ a) and the second signal 62(Y _ B), are input to two inputs of a logic xor gate 81 according to the xor formula
When the output level of the first comparator 63 is different from the output level of the second comparator 64, the alarm signal output by the output end of the logic exclusive or gate 81 has a logic "1" level, and the upper computer 9 can judge that the level of the data output by the I2C slave device is abnormal by monitoring the logic level of the alarm signal, so as to achieve the purpose of alarming.
Further, the values of the first signal 61 and the second signal 62 reflect the logic level and the voltage range of the feedback signal (SDA _ Rx _ Slave) sent from the Slave device 2 to the master device 1, where please refer to table one again, and the voltage range includes a normal area, an abnormal early warning area, and a failure area.
Further, the alarm signal triggers the upper computer 9 to alarm when the logic level value of the alarm signal is "1", and the alarm signal does not trigger the upper computer 9 to alarm when the logic level value of the alarm signal is "0".
By adopting the I2C bus control circuit provided by the embodiment of the invention, the level on the I2C bus can be monitored in real time, and when the level on the I2C bus is reduced due to the abnormality of the I2C chip, the current level output range can be corrected in time, the alarm processing unit 80 is triggered to send an alarm signal, a user is reminded to replace or maintain equipment, the error data acquisition caused by the performance reduction of the chip is avoided, and the safety and reliability of the whole circuit system are improved.
Fig. 7 and 8 are schematic diagrams illustrating simulation of data level voltage value abnormality of a slave device, respectively. As shown in fig. 7 and 8, the I2C bus control circuit at a frequency of 100KHz is simulated to send a 0-4V peak-to-peak square wave, the reference voltages of the first comparator 63 and the second comparator 64 are 4.3V (vh) and 3.5V (vl), respectively, the waveform of blue in the oscilloscope in fig. 7 is used to simulate abnormal level data output from the device 2, the waveform of yellow is a low level of 0V after passing through the first comparator 63, the waveform of red is a square wave waveform after passing through the second comparator 64, and the waveform of green is a square wave after being corrected by the data correction unit 70. The red waveform in the oscilloscope in fig. 8 is the waveform after passing through the alarm processing unit 90, and when the oscilloscope in fig. 8 appears the red waveform, the existence of the alarm with abnormal level is indicated.
The embodiment of the invention also provides a circuit system for a ship, which comprises the I2C bus control circuit in the embodiment.
As can be seen from the above, an I2C bus control circuit and a circuit system for a ship according to an embodiment of the present invention are provided, in which the I2C bus interface control circuit includes: the bus driving unit divides a data transmission link between the master device and the slave device into a sending link and a receiving link, monitors the level of a feedback signal sent from the slave device to the master device, and transmits the feedback signal sent from the slave device to the master device on the receiving link of the bus driving unit after data correction, so that wrong data acquisition caused by the reduction of the I2C bus level is avoided, and the safety and reliability of the whole circuit system are guaranteed.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, which is defined by the appended claims.
Claims (10)
1. An I2C bus control circuit, comprising:
a bus driving unit connected on an I2C bus between a master device and a slave device, the master device and the slave device communicating via the I2C bus, wherein the bus driving unit directly transmits a data signal output by the master device to the slave device via a data line of the I2C bus and directly transmits a clock signal output by the master device to the slave device via a clock line of the I2C bus;
a level monitoring unit electrically connected to the data line of the I2C bus to receive a feedback signal sent by the slave device to the master device and to output a first signal and a second signal based on the feedback signal, the first signal and the second signal reflecting the feedback signal and a voltage range thereof;
a data correction unit electrically connected with the bus driving unit and the level monitoring unit, respectively, to receive the first signal and the second signal, and to generate a corrected feedback signal based on the first signal and the second signal, and to transmit the corrected feedback signal to the master device via the bus driving unit.
2. The I2C bus control circuit of claim 1, wherein the bus driver unit boosts the corrected feedback signal and sends the boosted feedback signal to the master device.
3. The I2C bus control circuit of claim 2, wherein the control circuit further comprises an alarm processing unit electrically connected to the level monitoring unit to receive the first and second signals and generate an alarm signal based on the first and second signals to trigger a host computer to perform an alarm operation.
4. The I2C bus control circuit of any one of claims 1-3, wherein the level monitor unit includes first and second comparators each having positive and negative inputs, and the positive inputs of the first and second comparators are each for receiving the feedback signal;
the negative input end of the first comparator is connected to an intermediate node formed by connecting a third resistor and a fourth resistor in series, and the third resistor and the fourth resistor are connected between a power supply and the ground in series so as to input the voltage divided by the third resistor and the fourth resistor to the negative input end of the first comparator;
the negative input end of the second comparator is connected to an intermediate node formed by connecting a sixth resistor and a seventh resistor in series, and the sixth resistor and the seventh resistor are connected between a power supply and the ground in series so as to input the voltage divided by the sixth resistor and the seventh resistor to the negative input end of the second comparator;
wherein the output terminal of the first comparator outputs the first signal, and the output terminal of the second comparator outputs the second signal.
5. The I2C bus control circuit of claim 4,
the level monitoring unit further comprises a first resistor, a second resistor and a fifth resistor;
the first end of the first resistor is connected with a power supply, and the second end of the first resistor is electrically connected with a data line for transmitting the feedback signal;
a first end of the second resistor is connected with a power supply, and a second end of the second resistor is electrically connected with an output end of the first comparator for outputting the first signal;
and a first end of the fifth resistor is connected with a power supply, and a second end of the fifth resistor is electrically connected with an output end of the second comparator for outputting the second signal.
6. The I2C bus control circuit of claim 5,
the data correction unit comprises a logic or gate, two input ends of the logic or gate respectively receive the first signal and the second signal, and an output end of the logic or gate outputs the corrected feedback signal.
7. The I2C bus control circuit of claim 6, wherein the alarm processing unit includes a logic exclusive or gate, two inputs of the logic exclusive or gate receive the first signal and the second signal respectively, and an output of the logic exclusive or gate outputs the alarm signal.
8. The I2C bus control circuit of claim 7,
the values of the first signal and the second signal reflect the voltage range of the feedback signal, wherein the voltage range comprises a normal area, an abnormal early warning area and a failure area.
9. The I2C bus control circuit of claim 8, wherein the alarm signal triggers the upper computer to alarm if the logic level of the alarm signal takes a value of "1", and wherein the alarm signal does not trigger the upper computer to alarm if the logic level of the alarm signal takes a value of "0".
10. A circuit system for a marine vessel, characterized in that the circuit system comprises an I2C bus control circuit according to any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111338596.2A CN114020679B (en) | 2021-11-12 | 2021-11-12 | I2C bus control circuit and circuit system for ship |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111338596.2A CN114020679B (en) | 2021-11-12 | 2021-11-12 | I2C bus control circuit and circuit system for ship |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114020679A true CN114020679A (en) | 2022-02-08 |
| CN114020679B CN114020679B (en) | 2023-11-07 |
Family
ID=80063950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111338596.2A Active CN114020679B (en) | 2021-11-12 | 2021-11-12 | I2C bus control circuit and circuit system for ship |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114020679B (en) |
Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003141061A (en) * | 2001-11-01 | 2003-05-16 | Nec Corp | I2c bus control method and i2c bus system |
| CN1574615A (en) * | 2003-06-03 | 2005-02-02 | 三星电子株式会社 | Feedback control system and method |
| US20050165989A1 (en) * | 2004-01-26 | 2005-07-28 | Yong-Jae Kim | I2C communication system and method enabling bi-directional communications |
| EP1669882A2 (en) * | 2004-12-06 | 2006-06-14 | Vaillant GmbH | Method for the extended use of an IIC bus signal line |
| KR20080057466A (en) * | 2006-12-20 | 2008-06-25 | 삼성중공업 주식회사 | I2c communication system embodied software |
| US20130067130A1 (en) * | 2010-05-21 | 2013-03-14 | Nec Corporation | Bus control apparatus and bus control method |
| US20130132626A1 (en) * | 2011-11-18 | 2013-05-23 | Fairchild Semiconductor Corporation | Pin selectable i2c slave addresses |
| US20140189177A1 (en) * | 2013-01-03 | 2014-07-03 | International Business Machines Corporation | High speed overlay of idle i2c bus bandwidth |
| JP2015184935A (en) * | 2014-03-25 | 2015-10-22 | 日本電気株式会社 | I2c bus arbitration system and arbitration method |
| CN106598891A (en) * | 2015-10-15 | 2017-04-26 | 飞思卡尔半导体公司 | Alarm signal of slave device in integrated circuit (I2C) bus system |
| CN107562668A (en) * | 2017-08-31 | 2018-01-09 | 广东欧珀移动通信有限公司 | Bus deadlock recovery system and method |
| US20180091068A1 (en) * | 2016-09-28 | 2018-03-29 | Renesas Electronics Corporation | Input buffer, semiconductor device and engine control unit |
| CN109976489A (en) * | 2019-03-28 | 2019-07-05 | 烽火通信科技股份有限公司 | Automatically reset realization method and system under a kind of iic bus abnormal conditions |
| US20200004708A1 (en) * | 2018-06-28 | 2020-01-02 | Hongfujin Precision Electronics (Tianjin) Co.,Ltd. | I2c data communication system and method |
| KR20200129333A (en) * | 2019-05-08 | 2020-11-18 | 주식회사 지니틱스 | Method for assigning different addresses on a plurality of slave devices using I2C communication protocol and a device for the same |
| US20210064567A1 (en) * | 2019-08-28 | 2021-03-04 | STMicroelectronics (Grand Ouest) SAS | I2c communication |
| CN112463707A (en) * | 2020-12-11 | 2021-03-09 | 苏州浪潮智能科技有限公司 | I2C link management system and method |
-
2021
- 2021-11-12 CN CN202111338596.2A patent/CN114020679B/en active Active
Patent Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003141061A (en) * | 2001-11-01 | 2003-05-16 | Nec Corp | I2c bus control method and i2c bus system |
| CN1574615A (en) * | 2003-06-03 | 2005-02-02 | 三星电子株式会社 | Feedback control system and method |
| US20050165989A1 (en) * | 2004-01-26 | 2005-07-28 | Yong-Jae Kim | I2C communication system and method enabling bi-directional communications |
| EP1669882A2 (en) * | 2004-12-06 | 2006-06-14 | Vaillant GmbH | Method for the extended use of an IIC bus signal line |
| KR20080057466A (en) * | 2006-12-20 | 2008-06-25 | 삼성중공업 주식회사 | I2c communication system embodied software |
| US20130067130A1 (en) * | 2010-05-21 | 2013-03-14 | Nec Corporation | Bus control apparatus and bus control method |
| US20130132626A1 (en) * | 2011-11-18 | 2013-05-23 | Fairchild Semiconductor Corporation | Pin selectable i2c slave addresses |
| US20140189177A1 (en) * | 2013-01-03 | 2014-07-03 | International Business Machines Corporation | High speed overlay of idle i2c bus bandwidth |
| JP2015184935A (en) * | 2014-03-25 | 2015-10-22 | 日本電気株式会社 | I2c bus arbitration system and arbitration method |
| CN106598891A (en) * | 2015-10-15 | 2017-04-26 | 飞思卡尔半导体公司 | Alarm signal of slave device in integrated circuit (I2C) bus system |
| US20180091068A1 (en) * | 2016-09-28 | 2018-03-29 | Renesas Electronics Corporation | Input buffer, semiconductor device and engine control unit |
| CN107562668A (en) * | 2017-08-31 | 2018-01-09 | 广东欧珀移动通信有限公司 | Bus deadlock recovery system and method |
| US20200004708A1 (en) * | 2018-06-28 | 2020-01-02 | Hongfujin Precision Electronics (Tianjin) Co.,Ltd. | I2c data communication system and method |
| CN109976489A (en) * | 2019-03-28 | 2019-07-05 | 烽火通信科技股份有限公司 | Automatically reset realization method and system under a kind of iic bus abnormal conditions |
| KR20200129333A (en) * | 2019-05-08 | 2020-11-18 | 주식회사 지니틱스 | Method for assigning different addresses on a plurality of slave devices using I2C communication protocol and a device for the same |
| US20210064567A1 (en) * | 2019-08-28 | 2021-03-04 | STMicroelectronics (Grand Ouest) SAS | I2c communication |
| CN112463707A (en) * | 2020-12-11 | 2021-03-09 | 苏州浪潮智能科技有限公司 | I2C link management system and method |
Non-Patent Citations (1)
| Title |
|---|
| 王湘泳;李铭祥;葛建民;韩建国;丁宗文;: "I~2C总线控制的2.4~2.5GHz频率源的设计", 上海大学学报(自然科学版), no. 03, pages 234 - 238 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114020679B (en) | 2023-11-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8355837B2 (en) | System and method for testing the integrity of a vehicle testing/diagnostic system | |
| US11372796B2 (en) | Bus subscriber and method for operating a bus subscriber | |
| TWI449936B (en) | Testing device for main board | |
| US9783138B2 (en) | Vehicle control device | |
| US10628356B2 (en) | Transmission apparatus and transmission method | |
| CN110246468B (en) | Amplitude of oscillation adjustment drive arrangement | |
| EP2823404A1 (en) | Collision detection in eia-485 bus systems | |
| US11095475B2 (en) | Communication failure detection device | |
| CN110351065B (en) | Bidirectional communication using edge timing in signals | |
| CN114020679B (en) | I2C bus control circuit and circuit system for ship | |
| JP2006139634A (en) | Equipment management device, communication channel diagnosis device, and equipment management method | |
| CN110505200B (en) | Multi-protocol daisy chain interface conversion chip | |
| KR101084060B1 (en) | The data-transmittable non-polarity RS-485 communication device of BMS controller by automatic polarity discrimination | |
| CN115309683A (en) | Serial port self-adaptive switching circuit and communication equipment | |
| CN112491678A (en) | Digital level transmission circuit and method | |
| JP5669419B2 (en) | Image forming apparatus | |
| CN117215983B (en) | Circuit structure and method for avoiding error starting and stopping conditions of I2C interface | |
| CN211043633U (en) | L VDS transmission open circuit detection circuit | |
| CN211580131U (en) | Testing device for SFP + interface of switch | |
| US10887074B1 (en) | Full duplex communication using edge timing in a signal | |
| CN115276923B (en) | Redundant communication circuit and fault determination method | |
| CN112291128B (en) | Bus-based communication system, system on chip and method therefor | |
| CN220085382U (en) | Artificial intelligence acceleration card and server | |
| CN113615089A (en) | Switching device for converting differential input signals and system having a switching device | |
| CN204740839U (en) | Detecting system of display and display tool that has detection function |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 201108 Shanghai city Minhang District Huaning Road No. 3111 Applicant after: The 711 Research Institute of China Shipbuilding Corp. Address before: 201108 Shanghai city Minhang District Huaning Road No. 3111 Applicant before: Shanghai Marine Diesel Engine Research Institute |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |