CN113973061A - Circuit time delay prediction method and device, terminal equipment and readable storage medium - Google Patents
Circuit time delay prediction method and device, terminal equipment and readable storage medium Download PDFInfo
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Abstract
The application discloses a circuit delay prediction method, a circuit delay prediction device, terminal equipment and a readable storage medium. The method comprises the following steps: acquiring an ith RC network corresponding to an ith net of a circuit, wherein I is more than or equal to 1 and less than or equal to I, and I is the total number of nets in the circuit; determining an ith graph connection matrix and an ith eigenvector matrix based on the ith RC network; and predicting the time delay of the ith RC network by using the ith graph connection matrix and the ith eigenvector matrix. The graph connection matrix comprises the relation among all paths in the wiring structure to be predicted, the feature vector matrix comprises common attributes of all nodes in the wiring structure to be predicted, accurate prediction of the wiring structure to be predicted can be achieved based on the graph connection matrix and the feature vector matrix, and the prediction speed is high.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a circuit delay prediction method, an apparatus, a terminal device, and a readable storage medium.
Background
In the IC design flow, static timing analysis is required in the layout stage, that is, in the optimization in the layout stage, guidance needs to be performed by timing estimation before routing to adjust paths that do not meet timing convergence conditions. However, at this stage, since wiring has not been performed yet, accurate timing estimation is difficult.
Currently, there are two strategies for resolving timing uncertainties due to insufficient routing information. One approach is to take an overly pessimistic pre-wiring prediction to ensure that no timing conflicts occur after wiring. This pessimism can lead to over-design, wasting resources, area, and optimization time. Another approach is to iterate back to the cell location when the wiring fails to achieve the desired timing power dissipation. However, multiple iterations do not guarantee the success of the iteration and will greatly increase the design turn around time.
Disclosure of Invention
In view of the above problems, the present application provides a circuit delay prediction method, apparatus, terminal device and readable storage medium, which shorten the circuit delay prediction time.
The embodiment of the application provides a circuit delay prediction method, which comprises the following steps:
acquiring an ith RC network corresponding to an ith net of a circuit, wherein I is more than or equal to 1 and less than or equal to I, and I is the total number of nets in the circuit;
determining an ith graph connection matrix and an ith eigenvector matrix based on the ith RC network;
and predicting the time delay of the ith RC network by using the ith graph connection matrix and the ith eigenvector matrix.
The circuit delay prediction method according to the embodiment of the present application, where the determining of the ith graph connection matrix based on the ith RC network includes:
adding labels to each node in the ith RC network;
determining a signal output node from the respective nodes based on a signal flow direction in the ith RC network;
taking a node receiving the output signal of the jth signal output node as a related signal input node of the jth signal output node, wherein J is more than or equal to 1 and less than or equal to J, and J is the total number of signal output nodes in the ith RC network;
the ith graph connection matrix is determined based on the labels of the respective nodes and the associated signal input nodes of the respective signal output nodes.
The circuit delay prediction method according to the embodiment of the present application, which determines the ith eigenvector matrix based on the ith RC network, includes:
determining, with an EDA tool, slew rates of respective pin nodes in the ith RC network;
determining a pin node related to a kth non-pin node, and assigning a slew rate of the kth non-pin node based on the slew rate of the related pin node, wherein the pin node related to the kth non-pin node is a pin node belonging to the same path as the kth non-pin node, K is greater than or equal to 1 and less than or equal to K, and K is the total number of the non-pin nodes in the ith RC network;
determining capacitance value parameters of each node based on the relevant capacitance of each node, wherein the relevant capacitance of each pin node comprises a pin capacitance and a connecting line capacitance, and the relevant capacitance of each non-pin node comprises a connecting line capacitance;
determining a resistance value parameter of each node based on the connection resistance of each node;
and determining the ith eigenvector matrix based on the slew rate of each node, the capacitance value parameter of each node and the resistance value parameter of each node.
The circuit delay prediction method according to the embodiment of the present application, assigning a slew rate of a kth non-pin node based on the slew rate of the associated pin node, includes:
assigning a slew rate of the kth non-pin node using the following rules:
the slew rate of the kth non-pin node is greater than or equal to the slew rate of a first related pin node and less than or equal to the slew rate of a second related pin node;
the closer the distance between the kth non-pin node and the first associated pin node, the closer the slew rate of the kth non-pin node is to the slew rate of the first associated pin node.
The method for predicting circuit delay according to the embodiment of the present application, predicting delay of the ith RC network by using the ith graph connection matrix and the ith eigenvector matrix, includes:
inputting the ith graph connection matrix and the ith feature vector matrix into a graph neural network which is trained in advance;
and predicting the time delay of the ith RC network by using the graph neural network.
The circuit delay prediction method according to the embodiment of the present application, predicting the delay of the ith RC network by using the graph neural network, includes:
aggregating the eigenvectors of each node and the eigenvectors of the adjacent nodes based on the ith graph connection matrix and the ith eigenvector matrix to obtain respective first aggregated eigenvectors;
encoding each first aggregation feature vector by using a first full-link layer and a first activation function to obtain each first dimension-extended feature vector;
aggregating the first dimension-expanding characteristic vector of each node and the first dimension-expanding characteristic vectors of adjacent nodes to obtain second aggregated characteristic vectors;
coding each second aggregation characteristic vector by using a second full-connection layer and a second activation function to obtain each second dimension-expanding characteristic vector;
and performing regression processing on each second dimension-extending feature vector to predict the time delay of the ith RC network.
The circuit delay prediction method according to the embodiment of the present application further includes:
acquiring a plurality of RC networks in advance, and determining a graph connection matrix and a characteristic vector matrix of each RC network;
determining the actual time delay of each RC network, and taking the actual time delay of each RC network as a label of each graph connection matrix and each characteristic vector matrix;
and training the graph neural network by utilizing each graph connection matrix with the label and the characteristic vector matrix.
The embodiment of the present application further provides a circuit delay prediction apparatus, where the apparatus includes:
the acquisition module is used for acquiring the ith RC network corresponding to the ith net of the circuit, I is more than or equal to 1 and less than or equal to I, and I is the total number of the nets in the circuit;
a determining module, configured to determine an ith graph connection matrix and an ith eigenvector matrix based on the ith RC network;
and the predicting module is used for predicting the time delay of the ith RC network by using the ith graph connection matrix and the ith eigenvector matrix.
The embodiment of the present application further provides a terminal device, which includes a memory and a processor, where the memory stores a computer program, and the circuit delay prediction method in the embodiment of the present application is executed when the computer program runs on the processor.
The embodiment of the present application further provides a readable storage medium, which stores a computer program, and when the computer program runs on a processor, the computer program executes the circuit delay prediction method according to the embodiment of the present application.
By acquiring the ith RC network corresponding to the ith net of the circuit, I is more than or equal to 1 and less than or equal to I, wherein I is the total number of nets in the circuit; determining an ith graph connection matrix and an ith eigenvector matrix based on the ith RC network; and predicting the time delay of the ith RC network by using the ith graph connection matrix and the ith eigenvector matrix. The graph connection matrix comprises the relation among all paths in the wiring structure to be predicted, the feature vector matrix comprises common attributes of all nodes in the wiring structure to be predicted, accurate prediction of the wiring structure to be predicted can be achieved based on the graph connection matrix and the feature vector matrix, and the prediction speed is high.
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In order to more clearly illustrate the technical solution of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention. Like components are numbered similarly in the various figures.
Fig. 1 shows a schematic structural diagram of a circuit network including a plurality of cells proposed in an embodiment of the present application;
fig. 2 is a schematic flow chart illustrating a circuit delay prediction method proposed in an embodiment of the present application;
fig. 3 shows a schematic structural diagram of an RC network corresponding to a net in the embodiment of the present application;
fig. 4 shows a schematic structural diagram of a processed RC network proposed in the embodiment of the present application;
FIG. 5 is a schematic flow chart of a training graph neural network proposed in an embodiment of the present application;
fig. 6 shows a schematic structural diagram of a circuit delay prediction apparatus proposed in the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present invention, are only intended to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
It should be noted that, the circuit network in this application includes a plurality of units, each unit includes a plurality of pins, and the units are connected to each other through the pins. Illustratively, referring to fig. 1, the network includes four net networks, where a net network between pin 1 of the first unit and pin 1 of the third unit includes two pin nodes (pin 1 of the first unit and pin 1 of the third unit), and does not include a non-pin node, and if a signal flows from pin 1 of the first unit to pin 1 of the third unit, pin 1 of the first unit is a driving pin, and pin 1 of the third unit is a target pin; the net network between pin 2 of the first unit and pin 2 of the third unit includes two pin nodes (pin 2 of the first unit and pin 2 of the third unit), and does not include a non-pin node, and if a signal flows from pin 2 of the first unit to pin 2 of the third unit, pin 2 of the first unit is a driving pin, and pin 2 of the third unit is a target pin; the net network between pin 3 of the first unit and pin 1 of the fourth unit comprises eight pin nodes (pin 3 and pin 4 of the first unit, pin 1 and pin 2 of the fourth unit, pin 1 and pin 2 of the second unit, pin 3 and pin 4 of the third unit), and six non-pin nodes (a, b, c, d, e, and f), wherein when the pin 3 of the first unit and the pin 1 of the fourth unit are main paths and a signal flows from the pin 3 of the first unit to the pin 1 of the fourth unit, the pin 3 of the first unit is a driving pin, the pin 1 of the fourth unit is a target pin, and the rest of the eight pin nodes are related pins; the net network between pin 3 of the second unit and pin 3 of the fourth unit includes two pin nodes (pin 3 of the second unit and pin 3 of the third unit), and does not include a non-pin node, and if a signal flows from pin 3 of the second unit to pin 3 of the fourth unit, pin 3 of the second unit is a drive pin, and pin 3 of the fourth unit is a target pin; the net network between pin 4 of the second unit and pin 4 of the fourth unit includes two pin nodes (pin 4 of the second unit and pin 4 of the third unit), and does not include a non-pin node, and if a signal flows from pin 4 of the second unit to pin 4 of the fourth unit, pin 4 of the second unit is a drive pin, and pin 4 of the fourth unit is a target pin.
The method comprises the steps of determining a graph connection matrix based on an ideal RC (resistance and Cap) network structure of each net among units (cells) in a wiring structure to be predicted, determining a characteristic vector matrix based on common attributes (such as capacitance, resistance and slew rate) of each node in the RC (resistance and Cap) network structure, and predicting the network delay of the wiring structure to be predicted after wiring according to the graph connection matrix and the characteristic vector matrix by using a graph neural network. And then, when the predicted network delay meets the preset condition, the wiring structure to be predicted is used as the wiring of the circuit, when the predicted network delay does not meet the preset condition, the wiring structure to be predicted is re-planned and adjusted, and a new wiring structure to be predicted is re-predicted until the predicted network delay meets the wiring position of the preset condition.
It can be understood that the graph connection matrix of the present application includes the relationship between each path in the wiring structure to be predicted, the feature vector matrix includes the common attributes of each node in the wiring structure to be predicted, accurate prediction of the wiring structure to be predicted can be achieved based on the graph connection matrix and the feature vector matrix, and the prediction speed is faster.
The present application will be further explained below by means of specific examples.
Example 1
Referring to fig. 2, an embodiment of the present application provides a circuit delay prediction method, which includes the following steps:
step S100, an ith RC network corresponding to the ith net of the circuit is obtained, I is more than or equal to 1 and less than or equal to I, and I is the total number of the nets in the circuit.
Illustratively, referring to fig. 3, a RC network corresponding to net is provided, wherein a path from a Driving pin node (Driving pin) to a target pin node (target pin) can be used as a main path, context pin 0, context pin 1, context pin 2, context pin 3, and context pin 4 are related pin nodes, node 0, node 1, and node 2 are non-pin nodes, each node includes a capacitance attribute, a resistance attribute, and a slew rate attribute, the capacitance value parameter corresponding to the capacitance attribute for the pin node is equal to the sum of the pin capacitance and the link capacitance, i.e., C ═ Cwire + Cpin, Cwire is the link capacitance, Cpin is the pin capacitance, the resistance value parameter corresponding to the resistance property for the pin node is equal to a value obtained by dividing the sum of all wiring resistance values related to the pin node by two (for example, the resistance value parameter R of the Driving pin node).DrivingR0/2), the slew rate corresponding to the slew rate attribute of the pin node may be determined using an EDA tool, the capacitance value parameter corresponding to the capacitance attribute of the non-pin node is equal to the link capacitance, i.e., C ═ Cwire, the resistance value parameter corresponding to the resistance attribute of the non-pin node is equal to a value obtained by dividing the sum of all link resistance values associated with the non-pin node by two (e.g., the resistance value parameter R of the non-pin node (node 0)node0(R0+ R1+ R2+ R3)/2), the slew rate corresponding to the slew rate attribute of the non-pin node may be assigned according to the slew rate of the pin node.
Step S200, determining an ith graph connection matrix and an ith eigenvector matrix based on the ith RC network.
In this embodiment, the ith graph connection matrix may be determined based on the ith RC network.
For example, referring to fig. 4, labels are added to nodes in the ith RC network, and each node may be marked according to a certain marking sequence as long as the marking sequence is guaranteed to be consistent all the time. In this embodiment, the Driving pin node (Driving pin) is marked, and the labels of the nodes are respectively marked as 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9.
Further, since the signal in each RC network flows from the Driving pin node (Driving pin) to each related pin node and the target pin node (target pin), respectively, a signal output node can be determined from all the nodes based on the signal flow in the ith RC network, and in fig. 4, the total number of the signal output nodes is 4, and the nodes are corresponding to the tag 0, the tag 2, the tag 4 and the tag 5, respectively.
Furthermore, a node receiving the output signal of the jth signal output node is used as a related signal input node of the jth signal output node, J is more than or equal to 1 and less than or equal to J, and J is the total number of the signal output nodes in the ith RC network. Taking the example shown in fig. 4 as an example, when J is 1, the first signal output node is a node corresponding to the tag 0, the node receiving the node output signal corresponding to the tag 0 is a node corresponding to the tag 2, when J is 2, the second signal output node is a node corresponding to the tag 2, the node receiving the node output signal corresponding to the tag 2 is a node corresponding to the tags 1 and 3, when J is 3, the third signal output node is a node corresponding to the tag 5, the node receiving the node output signal corresponding to the tag 5 is a node corresponding to the tags 4 and 6, when J is 4, the fourth signal output node is a node corresponding to the tag 4, and the node receiving the node output signal corresponding to the tag 4 is a node corresponding to the tags 8 and 9.
Further, an ith graph connection matrix is determined based on the labels of the respective nodes and the associated signal input nodes of the respective signal output nodes. Illustratively, the graph connection matrix corresponding to fig. 4 may be represented in the following form:
S_indeX：[0，2，2，2，5，5，5，4，4]
T_indeX：[2，1，3，5，4，6，7，8，9]
in this embodiment, the ith eigenvector matrix may be determined based on the ith RC network, and the ith eigenvector matrix mainly consists of the slew rate of each node, the capacitance value parameter of each node, and the resistance value parameter of each node.
For example, the slew rate of each pin node in the ith RC network may be determined by using an EDA tool, and if the node corresponding to tag 0, tag 1, tag 3, tag 6, tag 7, tag 8, and tag 9 is a pin node, taking the example shown in fig. 4 as an example, the slew rate of the node corresponding to tag 0, tag 1, tag 3, tag 6, tag 7, tag 8, and tag 9 may be determined by using the EDA tool. However, the EDA tool cannot determine the slew rate of the non-pin node, and therefore, in this embodiment, the slew rate of the non-pin node can be determined by using the following method:
and determining a pin node related to the kth non-pin node, and assigning a slew rate of the kth non-pin node based on the slew rate of the related pin node. It should be noted that, in this embodiment, the pin node related to the kth non-pin node is a pin node belonging to the same path as the kth non-pin node, K is greater than or equal to 1 and less than or equal to K, and K is the total number of non-pin nodes in the ith RC network.
Note that, if the Delay (Elmore Delay) of the Driving pin node (Driving pin) of the main path between the Driving pin node (Driving pin) and the target pin node (target pin) is DdriSlew rate of SdriThe Delay (Elmore Delay) of the node corresponding to the label 2 is D0Slew rate of S0The Delay (Elmore Delay) of the node corresponding to the label 5 is D1Slew rate of S1The slew rate of the target pin node (target pin) is StarAnd then:
S0＝Sdri+(Star-Sdri)(Ddri–D1)/Ddri
S1＝Sdri+(Star-Sdri)(Ddri–D0)/Ddri
wherein S is0And S1Unknown, the remaining parameters are known, if Sdri＝10，Star＝20，Ddri＝1ns，D0＝0.5ns，D1When the value is 0.2ns, the slew rate S of the node corresponding to the tag 2 is set to be 0.2ns010+ (20-10) (1-0.5)/1 ═ 15, slew rate S of node corresponding to tag 51＝10+(20–10)(1–0.2)/1＝18。
Therefore, when assigning the slew rate of the non-pin node, the slew rate of the non-pin node can be assigned based on the following rules:
the slew rate of the kth non-pin node is greater than or equal to the slew rate of the first related pin node and less than or equal to the slew rate of the second related pin node; the closer the distance between the kth non-pin node and the first associated pin node, the closer the slew rate of the kth non-pin node is to the slew rate of the first associated pin node.
Taking fig. 4 as an example, when K is 3, the first non-pin node is a node corresponding to the tag 2, the second non-pin node is a node corresponding to the tag 5, the third non-pin node is a node corresponding to the tag 4, when determining the slew rates of the node corresponding to the tag 5 and the node corresponding to the tag 2, the pin nodes (Driving pin) to target pin node (target pin)) on the main path (path between Driving pin node (Driving pin) and target pin node (target pin)) are first used as the relevant pin nodes of the node corresponding to the tag 5 and the node corresponding to the tag 2, if the slew rate of the node corresponding to the tag 0 (Driving pin)) is 10 and the slew rate of the node corresponding to the tag 7 (target pin)) is 20, the slew rate of the node corresponding to the tag 2 and the node corresponding to the tag 5 is greater than or equal to 10, and is less than or equal to 20, and because the node corresponding to the tag 2 is closer to the node corresponding to the tag 0, the slew rate of the node corresponding to the tag 2 is closer to 10, and the slew rate of the node corresponding to the tag 5 is farther from 10 and closer to 20 compared with the slew rate of the node corresponding to the tag 2, so that the slew rate of the node corresponding to the tag 2 can be assigned as 15, and the slew rate of the node corresponding to the tag 5 can be assigned as 18.
Further, the capacitance value parameter of each node may be determined based on the associated capacitance of each node, the associated capacitance of the pin node includes a pin capacitance and a link capacitance, the capacitance value parameter of the pin node is equal to the sum of the pin capacitance and the link capacitance, the associated capacitance of the non-pin node includes the link capacitance, and the capacitance value parameter of the non-pin node is equal to the link capacitance.
Further, a resistance value parameter of each node is determined based on the link resistance of each node, and the resistance value parameter of each node is equal to a value obtained by dividing the sum of all link resistances corresponding to the node by 2.
Exemplarily, taking fig. 4 as an example, the ith eigenvector matrix is:
the dimension of the ith feature vector matrix is 3 × 10, the 3 corresponds to the attribute total number of the nodes, the 10 corresponds to the total number of the nodes, each column of the matrix is a feature vector of one node, the feature vectors are placed in the matrix from left to right according to the sequence of node labels from small to large, and it can be understood that the placement sequence of the feature vectors can be other sequences, for example, from large to small, as long as the placement sequence is kept unique. The number of rows and columns is variable, with the number of columns varying with the number of nodes, and the number of rows being related to the total number of preselected node attributes.
And step S300, predicting the time delay of the ith RC network by using the ith graph connection matrix and the ith eigenvector matrix.
Any type of trained model can be used to predict the delay of the ith RC Network, such as Artificial Neural Network (ANN), Random Forest (RF).
In the embodiment, the characteristics of the RC network are considered, and the prediction accuracy can be ensured by using the neural network of the graph to predict the time delay. The ith graph connection matrix and the ith feature vector matrix can be input into a graph neural network which is trained in advance; and predicting the time delay of the ith RC network by using a graph neural network. The method for predicting the time delay of the ith RC network by using the graph neural network mainly comprises three steps of first embedding (embedding), second embedding and regression, wherein each embedding comprises two steps of aggregation and coding, and the final predicted time delay is obtained by regression.
For example, the feature vector of each node and the feature vectors of neighboring nodes may be aggregated based on the ith graph connection matrix and the ith feature vector matrix to obtain respective first aggregated feature vectors, i.e. the aggregation process in the first embedding, and the corresponding calculation formula is:
wherein, Agg1jThe first aggregated feature vector for the jth node,
is the feature vector of the jth node,
is the feature vector of the upstream node, su (v) is the feature vector set of the downstream node,
is the downstream node feature vector of the jth node, wprAnd wsuAre training weights determined by pre-training. Taking the node corresponding to the label 2 in fig. 4 as an example, when the first aggregated feature vector of the node corresponding to the label 2 is calculated,
i.e. the feature vector of the node corresponding to tag 2,
that is, the node feature vector corresponding to label 0, and su (v) is the feature vector set of the nodes corresponding to labels 1, 3, and 5. If the currently calculated node has no upstream node or downstream node, the corresponding term in the above equation is 0.
Further, each first aggregation feature vector is encoded by using the first fully-connected layer and the first activation function to obtain each first dimension-extended feature vector, that is, the encoding process in the first embedding is performed, and the process encodes each first aggregation feature vector of 3 × 1 by using the first fully-connected layer and the first activation function to obtain a corresponding 8 × 1 first dimension-extended feature vector, where it should be noted that the first dimension-extended feature vector may also be in other dimensions, and may be in principle greater than 3 dimensions.
Further, aggregating the first dimension-extended feature vector of each node and the first dimension-extended feature vectors of neighboring nodes to obtain respective second aggregated feature vectors, i.e. an aggregation process in the second embedding, and the corresponding calculation formula is:
wherein, Agg2jA second aggregate feature vector for the jth node,
the first dimension-extended feature vector for the jth node,
is a first dimension-extended feature vector of an upstream node, su (v) is a first dimension-extended feature vector set of a downstream node,
namely the first dimension-extending feature vector of the downstream node of the jth node.
Further, each second aggregation feature vector is encoded by using a second full-connected layer and a second activation function to obtain each second dimension-extended feature vector, that is, an encoding process in the second embedding, in the process, each second aggregation feature vector of 8 × 1 is encoded by using the second full-connected layer and the second activation function to obtain a corresponding 16 × 1 second dimension-extended feature vector, it should be noted that the second dimension-extended feature vector may also be other dimensions, and it is only necessary to be larger than the dimension of the first aggregation feature vector in principle.
Further, performing regression processing on each second dimension-extended feature vector to predict the time delay of the ith RC network, where a formula corresponding to the regression processing is:
Agg3jfor the regression results, w is the weight determined by pre-training the graph neural network.
And finally, processing the regression result through a full communication layer of the graph neural network to obtain a 1-dimensional vector, and obtaining the final prediction delay through the 1-dimensional vector.
In this embodiment, the graph connection matrix includes a relationship between paths in the wiring structure to be predicted, the feature vector matrix includes common attributes of nodes in the wiring structure to be predicted, the graph neural network can accurately predict the wiring structure to be predicted based on the graph connection matrix and the feature vector matrix, and the prediction speed is faster.
Example 2
Referring to fig. 5, in the present embodiment, the proposed circuit delay prediction method further includes the following steps:
step S10, a plurality of RC networks are obtained in advance, and a graph connection matrix and a feature vector matrix of each RC network are determined.
The graph connection matrix and the feature vector matrix of each RC network may be determined by the method in the above embodiment.
And step S20, determining the actual time delay of each RC network, and taking the actual time delay of each RC network as the label of each graph connection matrix and each feature vector matrix.
And step S30, training the graph neural network by utilizing each graph connection matrix with the label and the feature vector matrix.
In the embodiment, the optimal value of the relevant weight in each formula in the graph neural network is determined by pre-training the graph neural network, so that the time delay precision of the graph neural network pre-measurement circuit network is ensured.
Example 3
Referring to fig. 6, in an embodiment of the present application, a circuit delay prediction apparatus 10 includes: an acquisition module 11, a determination module 12 and a prediction module 13.
An obtaining module 11, configured to obtain an ith RC network corresponding to an ith net of a circuit, where I is greater than or equal to 1 and less than or equal to I, and I is a total number of nets in the circuit; a determining module 12, configured to determine an ith graph connection matrix and an ith eigenvector matrix based on the ith RC network; and the predicting module 13 is configured to predict the delay of the ith RC network by using the ith map connection matrix and the ith eigenvector matrix.
The circuit delay prediction apparatus 10 disclosed in this embodiment is configured to execute the circuit delay prediction method described in the foregoing embodiment through the cooperative use of the obtaining module 11, the determining module 12, and the predicting module 13, and the implementation and the beneficial effects related to the foregoing embodiment are also applicable in this embodiment, and are not described herein again.
Example 4
The embodiment of the present application further provides a terminal device, which includes a memory and a processor, where the memory stores a computer program, and the computer program executes the circuit delay prediction method according to the above embodiment of the present application when running on the processor.
Example 5
Embodiments of the present application also provide a readable storage medium, which stores a computer program, and when the computer program runs on a processor, the computer program performs the circuit delay prediction method according to the above embodiments of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, each functional module or unit in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a readable storage medium. Based on such understanding, the technical solution of the present invention or a part of the technical solution that contributes to the prior art in essence can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned readable storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention.
Claims (10)
1. A method for circuit delay prediction, the method comprising:
acquiring an ith RC network corresponding to an ith net of a circuit, wherein I is more than or equal to 1 and less than or equal to I, and I is the total number of nets in the circuit;
determining an ith graph connection matrix and an ith eigenvector matrix based on the ith RC network;
and predicting the time delay of the ith RC network by using the ith graph connection matrix and the ith eigenvector matrix.
2. The circuit delay prediction method of claim 1, wherein the determining an ith graph connection matrix based on the ith RC network comprises:
adding labels to each node in the ith RC network;
determining a signal output node from the respective nodes based on a signal flow direction in the ith RC network;
taking a node receiving the output signal of the jth signal output node as a related signal input node of the jth signal output node, wherein J is more than or equal to 1 and less than or equal to J, and J is the total number of signal output nodes in the ith RC network;
the ith graph connection matrix is determined based on the labels of the respective nodes and the associated signal input nodes of the respective signal output nodes.
3. The circuit delay prediction method of claim 1, wherein determining an ith eigenvector matrix based on the ith RC network comprises:
determining, with an EDA tool, slew rates of respective pin nodes in the ith RC network;
determining a pin node related to a kth non-pin node, and assigning a slew rate of the kth non-pin node based on the slew rate of the related pin node, wherein the pin node related to the kth non-pin node is a pin node belonging to the same path as the kth non-pin node, K is greater than or equal to 1 and less than or equal to K, and K is the total number of the non-pin nodes in the ith RC network;
determining capacitance value parameters of each node based on the relevant capacitance of each node, wherein the relevant capacitance of each pin node comprises a pin capacitance and a connecting line capacitance, and the relevant capacitance of each non-pin node comprises a connecting line capacitance;
determining a resistance value parameter of each node based on the connection resistance of each node;
and determining the ith eigenvector matrix based on the slew rate of each node, the capacitance value parameter of each node and the resistance value parameter of each node.
4. The method of claim 3, wherein assigning the slew rate of the kth non-pin node based on the slew rate of the associated pin node comprises:
assigning a slew rate of the kth non-pin node using the following rules:
the slew rate of the kth non-pin node is greater than or equal to the slew rate of a first related pin node and less than or equal to the slew rate of a second related pin node;
the closer the distance between the kth non-pin node and the first associated pin node, the closer the slew rate of the kth non-pin node is to the slew rate of the first associated pin node.
5. The circuit delay prediction method of any of claims 1 to 4, wherein the predicting the delay of the ith RC network by using the ith graph connection matrix and the ith eigenvector matrix comprises:
inputting the ith graph connection matrix and the ith feature vector matrix into a graph neural network which is trained in advance;
and predicting the time delay of the ith RC network by using the graph neural network.
6. The circuit delay prediction method of claim 5, wherein the predicting the delay of the ith RC network by using the graph neural network comprises:
aggregating the eigenvectors of each node and the eigenvectors of the adjacent nodes based on the ith graph connection matrix and the ith eigenvector matrix to obtain respective first aggregated eigenvectors;
encoding each first aggregation feature vector by using a first full-link layer and a first activation function to obtain each first dimension-extended feature vector;
aggregating the first dimension-expanding characteristic vector of each node and the first dimension-expanding characteristic vectors of adjacent nodes to obtain second aggregated characteristic vectors;
coding each second aggregation characteristic vector by using a second full-connection layer and a second activation function to obtain each second dimension-expanding characteristic vector;
and performing regression processing on each second dimension-extending feature vector to predict the time delay of the ith RC network.
7. The circuit delay prediction method of claim 5, further comprising:
acquiring a plurality of RC networks in advance, and determining a graph connection matrix and a characteristic vector matrix of each RC network;
determining the actual time delay of each RC network, and taking the actual time delay of each RC network as a label of each graph connection matrix and each characteristic vector matrix;
and training the graph neural network by utilizing each graph connection matrix with the label and the characteristic vector matrix.
8. A circuit delay prediction apparatus, comprising:
the acquisition module is used for acquiring the ith RC network corresponding to the ith net of the circuit, I is more than or equal to 1 and less than or equal to I, and I is the total number of the nets in the circuit;
a determining module, configured to determine an ith graph connection matrix and an ith eigenvector matrix based on the ith RC network;
and the predicting module is used for predicting the time delay of the ith RC network by using the ith graph connection matrix and the ith eigenvector matrix.
9. A terminal device comprising a memory and a processor, the memory storing a computer program which, when run on the processor, performs the circuit delay prediction method of any one of claims 1 to 7.
10. A readable storage medium, characterized in that it stores a computer program which, when run on a processor, performs the circuit latency prediction method of any one of claims 1 to 7.
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