CN112464609A - Method and device for optimizing relative position layout of integrated circuit and storage medium - Google Patents
Method and device for optimizing relative position layout of integrated circuit and storage medium Download PDFInfo
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Abstract
The invention provides a method and a device for optimizing relative position layout of an integrated circuit and a storage medium, belonging to the field of integrated circuit design. The invention mainly comprises the following steps: performing alternative grouping on the standard cells in at least one data flow direction according to the register width, the data transmission stage number and the data return proportion of the standard cells in at least one data flow direction in the integrated circuit to obtain an alternative relative layout standard cell group; and obtaining the relative layout standard cell group according to the time sequence violation parameters in the alternative relative layout standard cell group, the Manhattan distance between all the mutually-connected standard cells and the total connecting line number. The invention can find out the standard units suitable for relative layout in the integrated circuit by screening, and is convenient for carrying out local layout optimization in a mode of arranging relative positions, so that the whole area and power consumption of the integrated circuit are optimized, and the design convergence process of the integrated circuit is accelerated.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a method and a device for optimizing the relative position layout of an integrated circuit and a storage medium.
Background
In most cases, the placement position and placement manner of a large module or IP are emphasized in the integrated circuit design process, and some small local optimizations are difficult to be made in detail, for example, a module is a unit of a common design plan, a module may contain dozens of millions of logic circuits, and it is difficult to further and finely plan the arrangement manner of some circuits. However, for reasons of data transmission speed or power consumption, it is desirable to precisely control the arrangement position or arrangement manner of some logic standard cells.
The prior art realizes the precise control of the arrangement position or arrangement mode of the standard units through three modes. The first is to directly specify the physical positions of the logic standard cells to achieve very precise arrangement, but the positions are difficult to change once the arrangement is good for a long time; the second way is to arrange randomly around a relatively fixed location, i.e. knowing that an IP must be placed in a particular location, we can have the logic devices communicating with that IP arranged as close as possible to that IP. Due to the relative fixed position mark. So that the arrangement can solve most of the communication problems with this IP. But when a group of logic devices is close to an IP, it will affect the communication of the group of logic devices with other logic devices or other IPs. A third way is to use relative positions for alignment, i.e. to specify that the relative physical positions of some of the standard cells form a group of standard cells, which are moved as a whole in the group during alignment, without disturbing the relative positions of the individual standard cells in the group.
The third arrangement is in practical design in great demand, but most standard cells are not suitable for grouping. It is necessary to find those standard cells from the integrated circuit that are suitable for relative placement for local optimization.
Disclosure of Invention
The invention provides a method and a device for optimizing the layout of relative positions of an integrated circuit and a storage medium, which are used for conveniently carrying out local layout optimization on standard units which are suitable for carrying out relative layout in the integrated circuit by screening.
In order to achieve the above object, the present invention adopts a technical solution of providing an optimization method for a relative position layout of an integrated circuit, comprising the steps of:
performing alternative grouping on the standard cells in at least one data flow direction according to the register width, the data transmission stage number and the data return proportion of the standard cells in at least one data flow direction in the integrated circuit to obtain an alternative relative layout standard cell group; and obtaining the relative layout standard cell group according to the time sequence violation parameters in the alternative relative layout standard cell group, the Manhattan distance between all the mutually-connected standard cells and the total connecting line number.
Another technical solution of the present invention is to provide an apparatus for optimizing a relative position layout of an integrated circuit, including: a module for performing alternative grouping on the standard cells in at least one data flow direction according to the register width, the data transfer stage number and the data return ratio of the standard cells in at least one data flow direction in the integrated circuit to obtain an alternative relative layout standard cell group; and means for obtaining a set of opposable placement criteria based on the timing violation parameters within the set of alternative relative placement criteria, the manhattan distances between all of the interrelated criteria, and the number of total connections.
In another aspect of the present invention, a computer-readable storage medium is provided, wherein computer instructions are operable to perform the method for optimizing relative position layout of integrated circuits described above.
The invention has the advantages that the standard units suitable for relative layout in the integrated circuit are screened and found, so that local layout optimization is conveniently carried out in a mode of arranging the relative positions of the standard units, the integral area and power consumption of the integrated circuit are optimized, and the design convergence process of the integrated circuit is accelerated.
Drawings
FIG. 1 is a flow chart illustrating a method for optimizing relative position layout of an integrated circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an embodiment of a method for optimizing relative position layout of an integrated circuit according to the present invention;
FIG. 3 is a schematic diagram of an embodiment of an apparatus for optimizing a relative position layout of an integrated circuit according to the present invention;
FIG. 4 is a schematic diagram of an apparatus for optimizing relative positioning of integrated circuits according to an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, and the scope of the present invention can be more clearly defined.
It should be noted that, herein, relationships such as first and second, etc., are intended to distinguish one entity or operation from another entity or operation without necessarily requiring or implying any actual such relationship or order between such actual operations. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include elements inherent in the list. The term "comprising", without further limitation, means that the element so defined is not excluded from the group of processes, methods, articles, or devices that include the element.
Fig. 1 is a flow chart showing an embodiment of a method for optimizing relative position placement of integrated circuits according to the present invention.
In the specific embodiment shown in fig. 1, the method for optimizing the relative position arrangement of integrated circuits of the present invention includes a process S101 and a process S102.
Process S101 in fig. 1 represents that the standard cells in at least one data stream are grouped according to the data stream direction to obtain an alternative relative layout standard cell group according to the register width, the data transfer stage number, and the data return ratio of the standard cells in at least one data stream direction in the integrated circuit.
Most standard units in the integrated circuit are not suitable for grouping to perform relative position arrangement optimization, screening is performed according to the register width, the data transmission series and the data return ratio, and standard units meeting screening conditions are subjected to alternative grouping, so that the standard units which are suitable for grouping and are optimized by adopting the relative position arrangement are further judged and screened.
In a specific example of the present application, the process of performing candidate grouping on the standard cells in the at least one data flow direction according to the register width, the data transfer stage number, and the data return ratio of the standard cells in the at least one data flow direction in the integrated circuit according to the data flow direction to obtain the candidate relative layout standard cell group includes performing candidate grouping on the standard cells in the at least one data flow direction according to the data flow direction, and obtaining a candidate relative layout standard cell group by using the standard cells in the data flow direction to further determine whether the combination manner of the candidate relative layout standard cell group is appropriate to perform further screening, so as to obtain the candidate relative layout standard cell group.
In a specific example of the present application, the process of performing candidate grouping on the standard cells in the at least one data flow direction according to the register width, the data transfer stage number, and the data return ratio of the standard cells in the at least one data flow direction in the integrated circuit according to the data flow direction to obtain the candidate relative layout standard cell group includes performing candidate grouping on the standard cells in the at least one data flow direction according to the data flow direction, and obtaining a plurality of candidate relative layout standard cell groups by using the standard cells in the one data flow direction to further determine whether the combination manner of the plurality of candidate relative layout standard cell groups is appropriate or not, so as to obtain the candidate relative layout standard cell group.
In a specific example of the present application, the process of performing candidate grouping on the standard cells in the at least one data flow direction according to the register width, the data transfer stage number, and the data return ratio of the standard cells in the at least one data flow direction in the integrated circuit according to the data flow direction to obtain the candidate relative layout standard cell group includes performing candidate grouping on the standard cells in the at least one data flow direction according to the data flow direction, and obtaining one candidate relative layout standard cell group by using the plurality of standard cells in the data flow direction, so as to further determine whether the combination manner of the candidate relative layout standard cell group is appropriate to perform screening, so as to obtain the candidate relative layout standard cell group.
In a specific embodiment of the present application, the process of performing the alternative grouping on the standard cells in the at least one data flow direction according to the register width, the data transfer stage number, and the data return ratio of the standard cells in the at least one data flow direction in the integrated circuit according to the data flow direction to obtain the candidate relative layout standard cell group includes obtaining the candidate relative layout standard cell group by using the standard cells in the data flow direction in which the register width of the starting standard cell is greater than the preset first width threshold and the register width of the non-starting standard cell is greater than the preset second width threshold, so as to further determine and screen whether the combination manner of the candidate relative layout standard cell group is appropriate, and obtain the candidate relative layout standard cell group.
Whether a group of standard cells can have a relatively fixed discharge pattern, an important criterion is the bit width of the standard cells. If several standard cells, such as a, B, C, D, on a data stream are all 1 bit data, it is not necessary to use the so-called relative arrangement, and their traces occupy the trace resources of one line. There is no possibility of the traces crossing each other. This is especially true when the bit widths of a, B, C, D are wide. For example, if A has a bit width of 32bits, it means that 32 registers are required to constitute A. If the positions of the 32 registers are not well planned, the output of the 32 registers may also be 32bits when being sent to B (or the width of B after operation may be larger or smaller than 32 bits). These lines will then cross each other, increasing the difficulty of routing.
In a specific example of the present application, the process of performing the alternative grouping on the standard cells in the at least one data flow direction according to the register width, the data transfer stage number, and the data return ratio of the standard cells in the at least one data flow direction in the integrated circuit according to the data flow direction to obtain the alternative relative layout standard cell group includes obtaining the alternative relative layout standard cell group by using the standard cells in the at least one data flow direction, where the register width of the initial standard cell is greater than the preset first width threshold and the non-initial standard cell is greater than the preset threshold corresponding to the preset data transfer stage, so as to further determine and screen whether the combination mode of the alternative relative layout standard cell group is appropriate, and obtain the relative layout standard cell group.
Preferably, in at least one data flow direction, the register width of the starting standard cell is greater than a preset first width threshold, and the non-starting standard cell is greater than a preset threshold corresponding to a preset data transfer stage, so as to obtain an alternative relative layout standard cell group, so as to further judge and screen whether the combination mode of the alternative relative layout standard cell group is appropriate, and obtain a relative layout standard cell group.
For example, in at least one data flow direction, the width of the register of the initial standard cell is greater than 8bit, the width of the register of the second-level standard cell is greater than 8bit, and the width of the register of the third-level brick unit is greater than 6bit, so that the standard cell group with the alternative relative layout is obtained, and whether the combination mode of the standard cell group with the alternative relative layout is proper or not is further judged and screened, so that the standard cell group with the relative layout is obtained.
In a specific embodiment of the present application, the process of performing the alternative grouping on the standard cells in the at least one data flow direction according to the register width, the data transfer stage number, and the data return ratio of the standard cells in the at least one data flow direction in the integrated circuit according to the data flow direction includes obtaining the candidate relative layout standard cell group by using the standard cells in the at least one data flow direction in which the stage number of data transfer is greater than the preset stage number threshold, where the more the data transfer techniques are, the better the profit obtained by combining the standard cells in the corresponding data flow direction is.
Preferably, in at least one data flow direction, the standard cells in the data flow direction with the data transfer number of stages greater than 3 are used to obtain an alternative relative layout standard cell group, so as to further judge and screen whether the combination mode of the alternative relative layout standard cell group is appropriate, and obtain a relative layout standard cell group.
In a specific embodiment of the application, the step of performing the alternative grouping on the standard cells in the at least one data flow direction according to the register width, the data transfer stage number, and the data return ratio of the standard cells in the at least one data flow direction in the integrated circuit according to the data flow direction to obtain the candidate relative layout standard cell group includes obtaining the candidate relative layout standard cell group by using the standard cells in the at least one data flow direction in which the data return ratio is greater than the preset ratio threshold.
The proportion of the backtransmission is also a parameter and can be set by a user, wherein the data can only be transmitted backwards through a few lines in the transmission process (for example, A has 32bits to be transmitted to B, 30 bits are transmitted from B to C, and 2bits can be transmitted back to A again from B). The embodiment can facilitate further judgment and screening on whether the combination mode of the alternative relative layout standard cell groups is appropriate or not, so as to obtain the relative layout standard cell groups.
In a specific example of the present application, the process of performing the alternative grouping on the standard cells in the at least one data flow direction according to the register width, the data transfer stage number, and the data return ratio of the standard cells in the at least one data flow direction in the integrated circuit according to the data flow direction to obtain the alternative relative layout standard cell group includes obtaining the alternative relative layout standard cell group by using the standard cells in the at least one data flow direction, in which the register width of the initial standard cell is greater than the preset first width threshold, the standard cells in the data flow direction in which the register width of the non-initial standard cell is greater than the preset second width threshold, the standard cells in the data flow direction in which the data transfer stage number is greater than the preset stage number threshold, and the standard cells in the data flow direction in which the data return ratio is greater than the preset. According to the preset register width threshold, the data transmission threshold and the data return ratio threshold, all standard cells which are possibly suitable for optimization by adopting a relative position layout optimization method in the whole integrated circuit can be searched and obtained in a path searching mode, so that whether the combination mode of the alternative relative layout standard cell groups is appropriate or not is further judged and screened, and the relative layout standard cell group is obtained.
Process S102 of FIG. 1 represents deriving a set of relatively placeable standard cells based on the timing violation parameters within the set of alternative relatively placeable standard cells, the Manhattan distance between all of the interrelated standard cells, and the number of total wires. The standard units suitable for relative layout in the integrated circuit can be judged and screened out from the alternative relative layout standard unit group, local layout optimization is conveniently carried out in a mode of arranging the used relative positions of the standard units, the integral area and power consumption of the integrated circuit are optimized, and the design convergence process of the integrated circuit is accelerated.
In a specific embodiment of the present application, the obtaining of the relatively arrangeable standard cell group according to the timing violation parameter in the candidate relatively arrangeable standard cell group, the manhattan distances between all the mutually related standard cells, and the total connection number includes summing up the manhattan distances between the mutually related standard cells to obtain a sum of distances between the standard cells; and determining the corresponding alternative relative layout standard cell groups with the preset number, in which the time sequence violation parameter in the alternative relative layout standard cell group is smaller than a preset time sequence parameter threshold value and the ratio of the distance between the standard cells to the total connecting line number is minimum, as the relative layout standard cell groups, wherein the preset number can be determined according to the specific requirements of users.
In a specific example of the present application, the process of obtaining a sum of distances between standard cells by summing the manhattan distances between the associated standard cell points includes collecting all the standard cells in the candidate relative layout standard cell group, determining a current position of each standard cell, calculating the manhattan distances between all the associated standard cell points, and summing all the distances to obtain L; summing and calculating to obtain the number N of the total connecting lines according to the number of fan-in and fan-out of each standard unit; and obtaining a total time sequence violation parameter S according to the current establishment time margin and the current maintenance time margin of each node. And taking out the candidate relative layout standard cell group with the minimum L/N timing violation parameter S smaller than a threshold value for relative layout planning.
Preferably, the present invention extracts the candidate relative layout standard cell group with the minimum L/N timing violation parameter S smaller than 10ns for the relative layout planning, or extracts the candidate relative layout standard cell group with the minimum L/N timing violation parameter S equal to 0 for the relative layout planning.
Therefore, standard cells suitable for relative layout in the integrated circuit can be judged and screened out from the alternative relative layout standard cell group, local layout optimization is conveniently carried out in a mode of arranging the used relative positions of the standard cells, the integral area and power consumption of the integrated circuit are optimized, and the design convergence process of the integrated circuit is accelerated.
Fig. 2 is a flow chart illustrating an embodiment of a method for optimizing relative placement of integrated circuits according to the present invention.
In the embodiment shown in FIG. 2, process S203 represents fixing the relative positions of the standard cells in the relative set of layout standard cells to obtain an entirety of a set of relatively placeable standard cells, and adjusting the layout between the entirety of relatively placeable standard cells and other standard cells in the integrated circuit using an EDA tool.
The standard cell group capable of being relatively arranged is locally arranged as a whole, so that a designer can be helped to put many small combinations into the design of the whole integrated circuit in a more compact mode, the area and the power consumption of the whole integrated circuit are optimized, and the design convergence process of the integrated circuit is accelerated.
Fig. 3 is a schematic diagram showing an embodiment of an apparatus for optimizing relative position arrangement of integrated circuits according to the present invention.
In the specific embodiment shown in fig. 3, the device for optimizing the relative position arrangement of integrated circuits of the present invention includes a module 301 and a module 302.
Most standard units in the integrated circuit are not suitable for grouping to perform relative position arrangement optimization, and the module 301 performs screening according to the register width, the data transmission progression and the data return ratio therein, and performs alternative grouping on the standard units meeting the screening condition, so as to further judge and screen out the standard units suitable for grouping and adopt the relative position arrangement optimization.
In an embodiment of the present application, the module 301 may obtain the candidate relative layout standard cell group by using at least one standard cell in the data flow direction, where the register width of the starting standard cell is greater than the preset first width threshold, and the register width of the non-starting standard cell is greater than the preset second width threshold, so as to further determine whether the combination manner of the candidate relative layout standard cell groups is appropriate, and obtain the candidate relative layout standard cell group.
In an embodiment of the present application, the module 301 may obtain the candidate relative layout standard cell group by using at least one standard cell in the data flow direction, where the number of data transmission stages is greater than the preset number threshold, so as to further determine whether the combination manner of the candidate relative layout standard cell group is appropriate, and obtain the candidate relative layout standard cell group.
In an embodiment of the present application, the module 301 may obtain the candidate relative layout standard cell group by using at least one standard cell in the data flow direction, where the data return ratio is greater than the preset ratio threshold, so as to further determine whether the combination manner of the candidate relative layout standard cell group is appropriate, and obtain the candidate relative layout standard cell group.
In a specific example of the present application, the module 301 may obtain the candidate relative layout standard cell group by using at least one standard cell in a data flow direction, where a register width of the initial standard cell is greater than a preset first width threshold, a register width of the non-initial standard cell is greater than a preset second width threshold, and a data flow direction of a data transfer whose number of stages is greater than a preset number of stages threshold, and a data flow direction of a data return proportion greater than a preset proportion threshold. According to the preset register width threshold, the data transmission threshold and the data return ratio threshold, all standard cells which are possibly suitable for optimization by adopting a relative position layout optimization method in the whole integrated circuit can be searched and obtained in a path searching mode, so that whether the combination mode of the alternative relative layout standard cell groups is appropriate or not is further judged and screened, and the relative layout standard cell group is obtained.
In one embodiment of the present application, module 302 may sum the inter-standard cell distances according to the manhattan distances between the inter-related standard cells; and determining the corresponding alternative relative layout standard cell groups with the preset number and the minimum ratio of the distance between the standard cells to the total connecting line number as relative layout standard cell groups, wherein the time sequence violation parameters in the alternative relative layout standard cell groups are smaller than a preset time sequence parameter threshold, and the relative layout standard cell groups with the preset number and the minimum ratio of the distance between the standard cells to the total connecting line number are convenient to carry out local layout optimization in a mode of arranging relative positions, so that the whole area and power consumption of the integrated circuit are optimized, and the design convergence process of the integrated circuit is accelerated.
Fig. 4 shows a specific embodiment of the present application.
In the embodiment shown in fig. 4, the module 403 is a module for fixing the relative positions of the standard cells in the relative layout standard cell group to obtain a whole relatively-placeable standard cell group, and using an EDA tool to adjust the layout between the whole relatively-placeable standard cell group and other standard cells in the integrated circuit, and partially placing the relatively-placeable standard cell group as a whole, which helps a designer to place many small combinations into our entire integrated circuit design in a more compact manner to optimize the area and power consumption of the integrated circuit as a whole, and accelerate the convergence process of the design.
In one embodiment of the present application, the modules of the integrated circuit relative position arrangement optimization apparatus may be directly in hardware, in a software module executed by a processor, or in a combination of the two.
A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.
The Processor may be a Central Processing Unit (CPU), other general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), other Programmable logic devices, discrete Gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In a particular embodiment of the present application, a computer-readable storage medium stores computer instructions operable to perform a method for integrated circuit relative position placement optimization as described in any of the embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed method and system may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, for example, the division of the units is only one division of logical functions, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some interfaces, and may be in a typical, mechanical or other form.
The units described as separate but not illustrated may or may not be physically separate, and components displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and all equivalent structural changes made by using the contents of the specification and the drawings, which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.
Claims (10)
1. A method for optimizing the relative position layout of integrated circuit includes such steps as providing a first position layout,
performing alternative grouping on the standard cells in at least one data flow direction according to the register width, the data transmission stage number and the data return proportion of the standard cells in at least one data flow direction in the integrated circuit to obtain an alternative relative layout standard cell group; and the number of the first and second groups,
and obtaining the standard cell group capable of being relatively arranged according to the time sequence violation parameters in the candidate standard cell group capable of being relatively arranged, the Manhattan distances among all the standard cells which are mutually connected and the total connecting line number.
2. The method of optimizing relative placement of integrated circuits as recited in claim 1, further comprising,
and fixing the relative position of each standard cell in the standard cell group capable of being relatively arranged to obtain a whole standard cell group capable of being relatively arranged, and adjusting the arrangement between the whole standard cell group capable of being relatively arranged and other standard cells in the integrated circuit by using an EDA tool.
3. The method according to claim 1, wherein the step of performing the alternative grouping of the standard cells in at least one data stream according to the data stream direction according to the register width, the data transfer order and the data return ratio of the standard cells in the at least one data stream direction to obtain the alternative relative placement standard cell group comprises,
and obtaining the candidate relative layout standard cell group by using the standard cells in the data flow direction in which the register width of the initial standard cell is greater than a preset first width threshold value and the register width of the non-initial standard cell is greater than a preset second width threshold value in the at least one data flow direction.
4. The method according to claim 1, wherein the step of performing the alternative grouping of the standard cells in at least one data stream according to the data stream direction according to the register width, the data transfer order and the data return ratio of the standard cells in the at least one data stream direction to obtain the alternative relative placement standard cell group comprises,
and obtaining the candidate relative layout standard cell group by using the standard cell in the data flow direction, in which the number of stages of data transmission is greater than a preset number-of-stages threshold value, in the at least one data flow direction.
5. The method according to claim 1, wherein the step of performing the alternative grouping of the standard cells in at least one data stream according to the data stream direction according to the register width, the data transfer order and the data return ratio of the standard cells in the at least one data stream direction to obtain the alternative relative placement standard cell group comprises,
and obtaining the candidate relative layout standard cell group by using the standard cell in the data flow direction with the data return proportion larger than a preset proportion threshold value in the at least one data flow direction.
6. The method of claim 1, wherein obtaining the set of relatively placeable standard cells based on the timing violation parameters within the set of alternative relatively placeable standard cells, the Manhattan distances between all of the interrelated standard cells, and the total number of wires comprises,
summing the distance sum among the standard units according to the Manhattan distance among the mutually-connected standard units;
and determining a predetermined number of corresponding candidate relative layout standard cell groups with a minimum ratio of the inter-standard cell distance to the total connection number as a relative layout standard cell group, wherein the timing violation parameter in the candidate relative layout standard cell group is smaller than a predetermined timing parameter threshold.
7. The method of claim 6, wherein obtaining the set of relatively placeable standard cells based on the timing violation parameters within the set of alternative relatively placeable standard cells, the Manhattan distances between all of the interrelated standard cells, and the total number of wires comprises,
and sorting the candidate relative layout standard cell groups according to the distance between the standard cells and the ratio of the distance to the total connecting line number.
8. An apparatus for optimizing a relative position layout of an integrated circuit, comprising,
a module, configured to perform alternative grouping on the standard cells in at least one data flow direction according to the register width, the data transfer stage number, and the data return ratio of the standard cells in the at least one data flow direction in the integrated circuit, so as to obtain an alternative relative layout standard cell group;
and means for obtaining a set of opposable placement criteria based on the timing violation parameter in the set of candidate relative placement criteria, the manhattan distance between all of the interrelated criteria, and the number of total wires.
9. The relative position layout optimizing device for integrated circuits according to claim 8, further comprising,
and means for fixing the relative position of each standard cell in the set of relatively placeable standard cells to obtain a module of the set of relatively placeable standard cells as a whole, and using an EDA tool to adjust the placement between the set of relatively placeable standard cells as a whole and other standard cells in the integrated circuit.
10. A computer readable storage medium storing computer instructions, wherein the computer instructions are operable to perform the method of integrated circuit relative position layout optimization of any of claims 1-7.
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