CN113821347A - Memory resource multiplexing method, device, medium and equipment - Google Patents

Memory resource multiplexing method, device, medium and equipment Download PDF

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Publication number
CN113821347A
CN113821347A CN202111130925.4A CN202111130925A CN113821347A CN 113821347 A CN113821347 A CN 113821347A CN 202111130925 A CN202111130925 A CN 202111130925A CN 113821347 A CN113821347 A CN 113821347A
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China
Prior art keywords
subsystem
etb
ram
register
memory
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CN202111130925.4A
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Chinese (zh)
Inventor
纪彬
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Spreadtrum Communications Shanghai Co Ltd
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Spreadtrum Communications Shanghai Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
    • G06F21/12—Protecting executable software
    • G06F21/121—Restricting unauthorised execution of programs
    • G06F21/123—Restricting unauthorised execution of programs by using dedicated hardware, e.g. dongles, smart cards, cryptographic processors, global positioning systems [GPS] devices

Abstract

The invention provides a memory resource multiplexing method, a device, a medium and equipment, wherein the method comprises the following steps: determining whether a watchdog of the first subsystem triggers an automatic register saving mechanism, and controlling the SP subsystem to access an ETB RAM by using an ETB read-write operation interface when the SP subsystem runs when the automatic register saving mechanism is triggered; when the register automatic saving mechanism is not triggered, the SP subsystem is controlled to access the IRAM special for the SP subsystem when the SP subsystem runs. The method triggers the register automatic saving mechanism of the first subsystem, which means that the AP/CP is hung up, so the ETB RAM is not needed to be used for analyzing the AP/CP hanging up. Therefore, at this time, the SP subsystem can multiplex the ETB RAM, and thus even if the IRAM dedicated to the SP subsystem is not sufficient, the problem of insufficient on-chip storage of the SP subsystem can be solved by multiplexing the ETB RAM.

Description

Memory resource multiplexing method, device, medium and equipment
Technical Field
The present invention relates to the field of embedded technologies, and in particular, to a method, an apparatus, a medium, and a device for multiplexing memory resources.
Background
Embedded systems (embedded systems) are widely used in intelligent devices such as consumer electronics and mobile communication. The system integrates modules such as a Central Processing Unit (CPU), a storage module, an input module, an output module and the like into one chip, and meets the requirements of small size, low power consumption and specialized use scenes. An embedded system generally includes an Application Processor (AP) subsystem, a Communication Processor (CP) subsystem, and a System Processor (SP) subsystem. An application processing subsystem for processing application-related subsystems; a communication processing subsystem for processing communication related subsystems; and the system processing subsystem is used for processing subsystems related to the operating system.
The intelligent device has at least two subsystems when in operation. Taking a smart phone as an example, the operation of the smart phone may involve an AP subsystem, a CP subsystem and an SP subsystem. The program of the SP subsystem is run on a dedicated Internal Random Access Memory (IRAM), the IRAM is determined during ASIC design, and due to cost limitation, the design of the Random Access Memory (RAM) is usually small, which just meets the requirement of practical application. However, in practical applications, due to the new requirement expansion, situations of insufficient RAM are often encountered, for example, a typical dedicated IRAM for the SP subsystem at present has about 256KB, and after the whole SP subsystem is operated, the remaining space of the dedicated IRAM is less than 1 KB. If the SP subsystem needs to add new functions, when the remaining space of the dedicated IRAM is insufficient, only the added functions can be discarded, or the old functions can be cut off, and thus, the SP subsystem obviously has the problem of insufficient on-chip storage during operation.
Therefore, a solution is urgently needed to improve the problem that the on-chip storage resources of the system processing subsystem are not enough.
Disclosure of Invention
The invention aims to provide a memory resource multiplexing method, a memory resource multiplexing device, a memory resource multiplexing medium and a memory resource multiplexing chip, which are used for solving the problem that storage resources on an SP subsystem chip are insufficient.
In a first aspect, the present invention provides a method for multiplexing memory resources, where the method includes: firstly, determining whether a watchdog of a first subsystem triggers an automatic register saving mechanism, wherein the first subsystem can be at least one of an application processing AP subsystem and a CP communication processing subsystem; when the register automatic saving mechanism is triggered, when the system uses the SP subsystem to run, the SP subsystem is controlled to run, and the SP subsystem accesses an ETB Random Access Memory (RAM) by using a read-write operation interface of the ETB.
The memory resource multiplexing method provided by the invention has the beneficial effects that: since triggering the register auto-save mechanism of the first subsystem means that the AP/CP is hung up, the ETB RAM is not needed to analyze the AP/CP hanging up, so that the SP subsystem can multiplex the ETB RAM at the moment, and the problem of insufficient on-chip storage of the SP subsystem can be solved by multiplexing the ETB RAM even if IRAM special for the SP subsystem is not enough.
In one possible embodiment, when the register auto-save mechanism is not triggered, the SP subsystem is controlled to access its own dedicated IRAM when the SP subsystem is running, and when the register auto-save mechanism is not triggered, the ETB RAM is needed for analyzing the AP/CP hang-up, so the SP subsystem cannot access the ETB RAM.
In a possible embodiment, when the system application SP subsystem runs, controlling the SP subsystem to access the ETB RAM by using the read-write operation interface of the ETB includes: when the system application SP subsystem runs, the compiling result of the system is obtained; determining whether the residual space of the IRAM special for the user meets the operation requirement or not according to the compiling result; and when the running requirement is not met, controlling the SP subsystem to access the ETB RAM by using the read-write operation interface of the ETB. Therefore, by using the compiling result, when the IRAM special for the SP subsystem is not enough, the ETB RAM can be reused in time, so that the problem of insufficient on-chip storage of the SP subsystem is solved.
In one possible embodiment, determining whether a watchdog of a first subsystem triggers a register auto-save mechanism comprises:
and when the CPU in the first subsystem is hung, determining that the first subsystem triggers an automatic register saving mechanism through a watchdog of the CPU of the hung subsystem.
In one possible embodiment, the CPU hang-up in the first subsystem comprises: the CPU of the AP subsystem is hung up and the CPU of the CP subsystem is not hung up, or the CPU of the AP subsystem is hung up and the CPU of the SP subsystem is hung up, or the CPU of the AP subsystem is not hung up and the CPU of the CP subsystem is hung up.
In one possible embodiment, the ETB RAM is a partial memory area in the Always-on power domain Always on in the chip.
In a second aspect, an embodiment of the present application further provides a memory resource multiplexing device, where the device includes a module/unit that executes any one of the design methods of the second aspect. These modules/units may be implemented by hardware, or by hardware executing corresponding software.
In a third aspect, an embodiment of the present application provides a terminal device, which includes a processor and a memory. Wherein the memory is used to store one or more computer programs; the one or more computer programs stored in the memory, when executed by the processor, enable the terminal device to implement the method of any of the possible designs of the second aspect described above.
In a fourth aspect, this embodiment also provides a computer-readable storage medium, which includes a computer program and when the computer program runs on an electronic device, causes the electronic device to execute any one of the possible design methods of any one of the above aspects.
In a fifth aspect, the present application further provides a computer program product, which when run on a terminal, causes the electronic device to execute any one of the possible design methods of any one of the above aspects.
In a sixth aspect, an embodiment of the present application further provides a chip, which is coupled to the memory and configured to execute the computer program stored in the memory, so that the electronic device performs any one of the possible design methods of the foregoing aspects.
As for the advantageous effects of the above second to sixth aspects, reference may be made to the description in the above first aspect.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a chip design structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an ETB control module according to an embodiment of the present invention;
fig. 3 is a schematic flow chart of a memory resource multiplexing method according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a communication device according to an embodiment of the present invention;
fig. 5 is a schematic diagram of another communication device according to an embodiment of the present invention.
Detailed Description
Before describing the embodiments of the present invention in detail, some terms used in the embodiments of the present invention will be explained below to facilitate understanding by those skilled in the art.
1、CoreSight
CoreSight is an infrastructure that can debug, monitor, and optimize the performance of a complete system on chip (SoC) design, CoreSightTMThe trace macrocell provides comprehensive non-intrusive visibility in the SoC. By following the CoreSight architecture specification, partner-specific tracking macro units can be conveniently integrated into CoreSight systems.
2. Embedded Trace Macrocell (ETM)
ETM is ARMTMThe microprocessor provides real-time instruction tracing and data tracing. The tracking software tool uses the information generated by the ETM to reconstruct the execution of all or a portion of the program.
3. Embedded Trace Buffer (ETB)
CoreSight ETB is a tracking receiver that can provide on-chip storage for tracking data using a configurable size RAM.
4. The watchdog mechanism is a mechanism for monitoring the hang-up of the AP, and the timeout of watchdog triggers an interrupt to notify the SP to process.
5. Always On (AON) is an area of the chip that does not power down. AON ETB refers to a block of on-chip storage resources that do not power down.
Currently, ARMTMThe embedded system of (2) places an ETB RAM in a region without power loss for debugging, wherein the size of the ETB RAM is about 16KB to 32KB, and the ETB RAM is used for storing an ETM instruction stream to analyze the stability problem of CPU hang-up and the like. For example, when the AP is hung, the ETB RAM is used to store the register information of the site before the CPU is hung; when the CP is hung dead, the ETB RAM is used for storing the register information of the site before the CPU is hung dead. The ETB RAM is designed to be used as a special purpose for storing the ETM instruction stream, and is not designed to be used as another purpose.
To this end, the present invention incorporates an Application Specific Integrated Circuit (ASIC) design that reserves a path for the SP subsystem to access the ETB RAM on the AON in the chip design. The SP subsystem can multiplex ETB RAM, and when the SP subsystem is not used for saving the problem of debugging stability of the AP/CPETM instruction stream, the SP subsystem can use the ETB RAM to meet the needs of the SP subsystem. As shown in fig. 1, a chip design structure provided in the embodiment of the present invention includes an ETM101, an AON ETB102, and an SP IRAM 103. The ETM101 is used by the AP subsystem or the CP subsystem, and the SP IRAM103 is used by the SP subsystem. In addition, the SP subsystem is added with an ETB control module 104, and the ETB control module 104 can access the ETB RAM102 through a path 105 for accessing the ETB RAM.
As shown in fig. 2, ETB control module 104 can read and write data on ETB RAM according to the read and write operation interface of coresight ETB.
Based on the chip design structure, the invention provides a memory resource multiplexing method, which can be executed by the ETB control module 104, and specifically includes the following steps:
s301, determining whether the watchdog of the first subsystem triggers the register automatic saving mechanism.
The trigger register automatic saving mechanism is used for triggering automatic saving of ETM instruction streams of the site before the CPU of the first subsystem which is hung dead hangs. The first subsystem may be an AP subsystem, a CP subsystem, or both an AP subsystem and a CP subsystem.
In this step, when the CPU of the first subsystem is hung up, or the watchdog times out, or the SP detects that the CPU watchdog of the first subsystem times out, it is determined that the watchdog of the first subsystem triggers the automatic register saving mechanism to save the register information of the AP CPU. Wherein, CPU hang-up in the first subsystem includes: the CPU of the AP subsystem is hung up and the CPU of the CP subsystem is not hung up, or the CPU of the AP subsystem is hung up and the CPU of the CP subsystem is hung up, or the CPU of the AP subsystem is not hung up and the CPU of the CP subsystem is hung up.
S302, when the register automatic saving mechanism is triggered, the SP subsystem is controlled to access the ETB RAM by using the read-write operation interface of the ETB when the SP subsystem runs.
In this embodiment, an automatic register saving mechanism is considered to be used for saving the information of the register in the field before the CPU of the suspended subsystem is suspended. Since the AP/CP hang-up has occurred, the ETB RAM is no longer needed for analyzing the AP/CP hang-up. Therefore, at this time, the SP subsystem can multiplex the ETB RAM, and thus even if the IRAM dedicated to the SP subsystem is not sufficient, the problem of insufficient on-chip storage of the SP subsystem can be solved by multiplexing the ETB RAM.
In a possible embodiment, in the above S302, the ETB control module 104 may first obtain a compiling result of the system, determine whether the remaining space of the IRAM dedicated to the SP subsystem meets the operation requirement according to the compiling result, and if the running requirement is not met, control the SP subsystem to access the ETB RAM by using the read-write operation interface of the ETB; if the operation requirement is met, the control SP subsystem still accesses the IRAM special for the control SP subsystem. Therefore, when IRAM special for the SP subsystem is not enough, the ETB RAM can be reused in time to solve the problem of insufficient on-chip storage of the SP subsystem.
In another possible embodiment, when the register auto-saving mechanism is not triggered, the SP subsystem is controlled to access its own dedicated Internal Random Access Memory (IRAM) while the SP subsystem is running. That is, at this time, the ETB RAM needs to be used to analyze AP/CP hangup, so the SP subsystem cannot access the ETB RAM.
Hereinafter, the method is further described by taking the smart terminal as a mobile phone and the AP subsystem and the SP subsystem are available when the mobile phone is operated.
An Application Processor (AP) is 4 cores, and in a normal case, both an AP subsystem and an SP subsystem operate normally, and the SP subsystem monitors a watchdog of the AP subsystem. When the AP CPU is hung, the watchdog is overtime, or the SP detects that the AP CPU watchdog is overtime, so that the register automatic saving mechanism is triggered to save the register information of the AP CPU. At this time, the SP subsystem can access the ETB RAM by using the read-write operation interface of the ETB, so that when the residual space of the special IRAM is insufficient, the SP subsystem can be ensured to normally run without abandoning a newly added function or cutting off an old function.
In addition, the invention also provides a memory resource multiplexing method, which can be executed by the ETB control module 104, a functional macro is newly added in software, the functional macro is in an open state and can control the SP subsystem to access the ETB RAM, and the AP/CP can not access the ETB RAM; the functional macro is in a closed state, so that the SP subsystem can be controlled not to access the ETB RAM, and the AP/CP can access the ETB RAM. Therefore, the aim of multiplexing ETB RAM resources can be achieved by controlling the opening or closing of the functional macro.
It should be noted that the memory resource multiplexing method provided by the present invention can be applied to a product of an embedded system with an ARM CPU, or the chip is designed with an ETB RAM and an SP subsystem, so that the technical scheme can be developed, transplanted and used to achieve the effect of expanding the storage space that the SP subsystem can actually utilize, and the applicable objects can be a chip, a chip module, a terminal or a base station, etc.
The same concept as that of the above-mentioned embodiment, the embodiment of the present application further provides a communication device, and the communication device 400 is used for implementing the above-mentioned method. For example, the communication apparatus 400 may be a terminal device, or may be an apparatus in the terminal device, and the apparatus in the terminal device may be a chip system.
In one example, as shown in fig. 4, the communication apparatus 400 includes a determining unit 401, a resource scheduling unit 402; a determining unit 401 is configured to determine whether the watchdog of the first subsystem triggers the register auto-saving mechanism. A resource scheduling unit 402, configured to, when the register automatic saving mechanism is triggered, control the SP subsystem to access the ETB RAM using the read-write operation interface of the ETB when the system applies the SP subsystem to operate; when the register automatic saving mechanism is not triggered, the SP subsystem is controlled to access the IRAM special for the SP subsystem when the SP subsystem runs. In addition, when the determining unit 401 determines that the AP subsystem and the CP subsystem operate normally, the resource scheduling unit 402 schedules the SP subsystem to access its own dedicated IRAM. That is, at this time, the ETB RAM needs to be used to analyze AP/CP hangup, so the SP subsystem cannot access the ETB RAM.
For the specific implementation and beneficial effects of the above units, see the description in the method related to fig. 4 above.
The division of the modules in the embodiments of the present application is schematic, and only one logical function division is provided, and in actual implementation, there may be another division manner, and in addition, each functional module in each embodiment of the present application may be integrated in one processor, may also exist alone physically, or may also be integrated in one module by two or more modules. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
As shown in fig. 5, the communication device 500 includes at least one processor 510 and memory 520. The memory 520 stores therein a computer program. The memory 520 is coupled to the processor 510. The communication device 500 may refer to the above terminal, and the coupling in the embodiment of the present invention is a spaced coupling or communication connection between devices, units or modules, and may be in an electrical, mechanical or other form, which is used for information interaction between the devices, units or modules. As another implementation, the memory 520 may also be located outside of the communication device 500. The processor 510 may operate in conjunction with the memory 520. Processor 510 may invoke computer programs stored in memory 520. At least one of the at least one memory may be included in the processor.
In some embodiments, communications apparatus 500 may also include a communications interface 530 for communicating with other devices over a transmission medium, such that the apparatus used in communications apparatus 500 may communicate with other devices. Illustratively, the communication interface 530 may be a transceiver, circuit, bus, module, or other type of communication interface, which may be other terminals. Processor 510 utilizes communication interface 530 to send and receive information and is operative to implement the methods in the embodiments described above. Illustratively, communication interface 530 is configured to receive resource indicator information. Also exemplary, communication interface 530 is used to transmit data.
In the embodiments of the present application, the processor may be a general-purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in a processor.
In the embodiment of the present application, the memory may be a nonvolatile memory, such as a Hard Disk Drive (HDD) or a solid-state drive (SSD), and may also be a volatile memory, for example, a random-access memory (RAM). The memory is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory in the embodiments of the present application may also be a circuit or any other device capable of implementing a storage function for storing a computer program and/or data.
The invention also provides a computer-readable medium, on which a computer program is stored, which, when executed by a computer, implements the method of the above-described method embodiments.
The invention also provides a computer program product which, when executed by a computer, implements the method of the above method embodiments.
The invention also provides a chip or a chip module, which is coupled with the memory and is used for executing the computer program stored in the memory, so that the terminal executes the method of the method embodiment.
Through the above description of the embodiments, it is clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely used as an example, and in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions. For the specific working processes of the system, the apparatus and the unit described above, reference may be made to the corresponding processes in the foregoing method embodiments, and details are not described here again.
Each functional unit in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or make a contribution to the prior art, or all or part of the technical solutions may be implemented in the form of a software product stored in a storage medium and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) or a processor to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: flash memory, removable hard drive, read only memory, random access memory, magnetic or optical disk, and the like.
The above description is only a specific implementation of the embodiments of the present application, but the scope of the embodiments of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the embodiments of the present application should be covered by the scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A method for multiplexing memory resources, the method comprising:
determining whether a watchdog of a first subsystem triggers a register auto-save mechanism, the first subsystem may be at least one of an application processing AP subsystem and a CP communication processing subsystem;
when the register automatic saving mechanism is triggered, the SP subsystem is controlled to access the RAM of the ETB random access memory by using the read-write operation interface of the ETB when the system applies the SP subsystem to operate.
2. The method of claim 1, wherein when the system application SP subsystem is running, controlling the SP subsystem to access the ETB RAM using the read-write operation interface of the ETB comprises:
when the system application SP subsystem runs, acquiring a compiling result of the system;
determining whether the residual space of the IRAM special for the user meets the operation requirement or not according to the compiling result;
and when the running requirement is not met, controlling the SP subsystem to access the ETB RAM by using the read-write operation interface of the ETB.
3. The method of claim 1 or 2, wherein determining whether the watchdog of the first subsystem triggers the register auto-save mechanism comprises:
and when at least one CPU in the first subsystem is hung, determining that the first subsystem triggers an automatic register saving mechanism through a watchdog of the CPU of the hung subsystem.
4. The method of claim 1 or 2, wherein the ETB RAM is a partial memory area in the Always-on power domain Always on in a chip.
5. A memory resource multiplexing device, comprising:
a determining unit, configured to determine whether a watchdog of a first subsystem triggers an automatic register saving mechanism, where the first subsystem may be at least one of an application processing AP subsystem and a CP communication processing subsystem;
and the resource scheduling unit is used for controlling the SP subsystem to access the RAM of the ETB random access memory by utilizing the read-write operation interface of the ETB when the register automatic saving mechanism is triggered and the system application SP subsystem runs.
6. The apparatus of claim 5, wherein the resource scheduling unit is configured to, when the system application SP subsystem runs and the SP subsystem is controlled to access the ETB RAM by using a read-write operation interface of the ETB, specifically:
when the system application SP subsystem runs, acquiring a compiling result of the system;
determining whether the residual space of the IRAM special for the user meets the operation requirement or not according to the compiling result;
and when the running requirement is not met, controlling the SP subsystem to access the ETB RAM by using the read-write operation interface of the ETB.
7. The apparatus according to claim 5 or 6, wherein the determining unit, when determining whether the watchdog of the first subsystem triggers the register auto-save mechanism, is specifically configured to:
and when at least one CPU in the first subsystem is hung, determining that the first subsystem triggers an automatic register saving mechanism through a watchdog of the CPU of the hung subsystem.
8. The device of claim 5 or 6, wherein the ETB RAM is a partial storage area in an Always-on power domain Always on of a chip.
9. An electronic device, comprising: a processor and a memory for storing a computer program; the processor is configured to execute the computer program stored by the memory to cause the terminal to perform the method of any of claims 1 to 4.
10. A computer-readable storage medium, having stored thereon a computer program, characterized in that the computer program, when being executed by a processor, carries out the method of any one of claims 1 to 4.
CN202111130925.4A 2021-09-26 2021-09-26 Memory resource multiplexing method, device, medium and equipment Pending CN113821347A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080126651A1 (en) * 2006-09-12 2008-05-29 International Business Machines Corporation Early Notification of Error Via Software Interrupt and Shared Memory Write
CN112068980A (en) * 2020-09-18 2020-12-11 展讯通信（上海）有限公司 Method and device for sampling information before CPU hang-up, equipment and storage medium

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080126651A1 (en) * 2006-09-12 2008-05-29 International Business Machines Corporation Early Notification of Error Via Software Interrupt and Shared Memory Write
CN112068980A (en) * 2020-09-18 2020-12-11 展讯通信（上海）有限公司 Method and device for sampling information before CPU hang-up, equipment and storage medium

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