CN1136503C - Flash memory system - Google Patents
Flash memory system Download PDFInfo
- Publication number
- CN1136503C CN1136503C CNB961011149A CN96101114A CN1136503C CN 1136503 C CN1136503 C CN 1136503C CN B961011149 A CNB961011149 A CN B961011149A CN 96101114 A CN96101114 A CN 96101114A CN 1136503 C CN1136503 C CN 1136503C
- Authority
- CN
- China
- Prior art keywords
- flicker
- data
- flash memory
- storage chip
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention relates to flash memories (20 and 21) connected with a host computer (1) through a flash memory controller (2) which is provided with a pair of data buses (27 and 28) and a pair of buffer memories (22 and 23), wherein each of the data buses is connected with a relative flash memory and a relative buffer memory connected with the host computer. The data buses (22 and 23) are controlled so as to be operated at the same time, and thereby, the flash memories are visited at the same time in a parallel mode. Data in the host computer is transferred to the flash memories through the buffer memories and the data buses, and vice versa.
Description
Technical field
The present invention relates to a kind of flash memory system that uses flash card, this system has as the flash memory of memory storage and/or as the external memory with flash memory of medium.When it when the external memory, moving its hard disk unit in computer system or the diskette unit.
Background technology
A flash memory system comprises at least one support card, and one or more is installed in flicker storage chip on the described card and one and is installed in the flicker memory controller that is used to control described flicker storage chip operation on the described chip.The flicker storage chip is sometimes referred to as EEP-ROM, or EEPROM (Electrically Erasable Programmable Read Only Memo).
Fig. 3 shows the block diagram of existing flicker memory controller.Among Fig. 3, numeral 1 is a principal computer, the 2nd, and the flicker memory controller, the 3rd, by the memory buffer that realizes of S-RAM for example, the 4th, the flicker storage chip, the 6th, buffer-stored manager, the 7th, flicker storage format control circuit, the 8th, main bus traffic pilot, the 9th, the buffer-stored traffic pilot, the 10th, flicker storage sequencer, reaching 12 is ECC treatment circuits, deal with data mistake when the latter is used for transmitting between principal computer and flicker storage chip.
(1) flicker memory controller
Usually the flash card of knowing has an external memory with flash memory that is used as the flash memory of memory storage and is used as medium.Flash card, and/or external memory has the flicker memory controller that is used to control the flicker storage chip.
The flicker memory controller according to the principal computer order to/control from the write/read operation of flash memory.The flicker memory controller is the same with hard disk controller, transmits control by finishing data, and the Writing/Reading of flash memory is controlled.
The flicker memory controller has an external buffer memory, by it finish to/from the write/read operation of flash memory.
When data were write flash memory, control operation was as follows.At first, the deposit data that transmits from principal computer is in memory buffer.The data of then depositing in the buffer register are read out, and after finishing format analysis processing, data are sent to flash memory.So promptly finish the write operation (the data transmission to hard disk controller is finished by similar path) that writes flash memory.
(2) existing flicker memory controller
As shown in Figure 3, flash controller 2 is connected to external buffer memory 3 and flash memory 4, and described flicker memory controller 2 is connected to host computer 1 (for example it can be a personal computer).
Flicker memory controller 2 has main interface control circuit 5, buffer-stored manager 6, and flicker storage format control circuit 7.
Main interface control circuit 5 has main bus traffic pilot 8, and buffer-stored manager 6 has buffer-stored traffic pilot 9, and flicker storage format control circuit 7 has flicker storage sequencer 10 and the ECC treatment circuit 12 that is used to handle mistake.
Described main interface control circuit 5 transmission/receptions be used to transmit data to/from the control signal of principal computer 1, main bus traffic pilot 8 so that glimmer in the memory controller 2 moves on time-sharing basis, thereby 16 bit data bus in the principal computer 1 are converted to 8 bit data bus (being called main bus).
7 transmission/the receptions of described flicker storage format control circuit be used to transmit data to/from the control signal of flash memory.In such cases, 10 pairs of sequencers of flicker storage are write and/or the access process of reading flash memory 4 is controlled.The data that flicker storage format control circuit 7 in the flicker memory controller 2 is finished between the flash memory 4 with 8 bit data ends and 8 buses (being called secondary bus) transmit.
Described memory buffer 6 is switched main bus and secondary bus so that in these buses is connected to memory buffer 3 on time-sharing basis.
(3) operation of flicker memory controller
As mentioned above, as hard disk controller, flicker memory controller 2 has external buffer memory 3, thereby the data of finishing between principal computer and the flash memory by described memory buffer transmit.
According to rate of data signalling, data stream is divided into two kinds of situations.
First data stream is the stream in the main bus, and an end of this main bus is connected to principal computer, and therefore the rate of data signalling of first data stream is identical with principal computer.
Second data stream is the stream in the secondary bus, and an end of this secondary bus is connected to flash memory 4, and therefore the rate of data signalling of second data stream is identical with flash memory 4.
Because the transfer rate of flash memory is lower than principal computer, so the transfer rate in the secondary bus is lower than main bus.In addition, when write data in flash memory, bus is occupied so that send order and address and from the flash memory accepting state to flash memory, and when some bus tight situation that Writing/Reading/reception exists when deleting flash memory, so that notify the inner case of flash memory to the flicker memory controller.Because above operation, the rate of data signalling in the flash memory must be low.
Described memory buffer 3 is between two devices that have the transfer rate that differs from one another in caching.Because described memory buffer receives the numerous sectors of data from principal computer simultaneously, so throughput has increased significantly.
Yet existing flicker memory controller has following shortcoming.
(1) be used for receiving numerous sectors of data from principal computer simultaneously owing to existing flicker memory controller has an external buffer memory, its advantage is to increase throughput.If yet the capacity of memory buffer is little, above-mentioned effect is also little.
In addition, when principal computer sends write order, deposit in the memory buffer temporarily, follow read buffer memory again, so that the data of reading are sent to flash memory from the data of principal computer.Therefore need some times with the data write buffering memory with from the memory buffer sense data.
In addition, the time that data take memory buffer is the twice of access time, because of two cycles of need (write cycle time and read cycle).Therefore the time that flash memory is write must long enough.
(2) common, main bus traffic pilot 8 will be converted to the 8 bit parallel data of delivering to a bus from 16 bit parallel data of principal computer.
Therefore, the transfer rate of delivering to main bus should be the twice of principal computer.The operating rate of buffer-stored manager and flash memory write operation also should be the twice of principal computer.Require the error correction device in the flicker storage format controller to have priority of interrupt in addition, so that accesses buffer.
Therefore memory buffer is often visited, and by the error correction device, main interface control circuit (low level visit and high-order visit) is to the visits such as write operation of flash memory.These visits to memory buffer are carried out on time-sharing basis.
Because described time-sharing operation, the travelling speed of flicker memory controller must be than the fast several times of memory buffer.
For example, when memory buffer is its access time static RAM (SRAM) that is 100ns, must be slower than 500ns to access time of principal computer.Therefore the rate of people logging in to flash memory is low in the prior art.
(3) wish the device that has one to be used for the Writing/Reading data fast as us, we must not only have the flash memory of a high-speed cruising, and a memory buffer with high capacity, short access time high-speed cache also should be arranged.
Yet the high-speed cache of commercial high-speed cruising only has low capacity, and the expense height.In addition, because their power consumptions are big, therefore be not suitable for our purpose.
Summary of the invention
An object of the present invention is to provide the flash memory system of the new improvement of a shortcoming that can overcome existing flash memory system and restriction.
Another object of the present invention provides a flash memory system, and the latter can provide high-speed cruising speed for the data write-read in the flash memory, and improves and pass through characteristic.
According to an aspect of the present invention, a kind of flash memory system that is connected to principal computer comprises: a plurality of flicker storage chips; And flicker memory controller that is used to control data transmission between described storage chip and the described principal computer; Described flicker memory controller comprises: many data buss, every described bus is connected to relevant flash memory, be used for to/transmit data from described flicker storage chip, an address caching that is connected to described data bus by door, be used for providing address information to described flicker storage chip by described data bus, a plurality of memory buffer, each described memory buffer is connected to relevant data bus and described principal computer, be used for depositing to/the data that transmit from the flicker storage chip temporarily, one is used for controlling simultaneously described data bus and described memory buffer, so that visit the flicker storage sequencer of a plurality of flicker storage chips simultaneously with parallel form, a plurality of comparers, the status information and the predetermined reference information that are used for being provided by relevant flicker storage chip compare, and AND circuit, be used to provide the logic AND computing of described comparer output, thereby described AND circuit just provided one on the occasion of output signal after all flicker storage chips were all correctly operated in just thinking last time to operate.
According to another aspect of the present invention, a kind of flicker memory controller, being used to control the flicker storage chip and the data between the principal computer that link to each other with described controller transmits, described controller comprises: many data buss, every described bus links to each other with relevant flicker storage chip, be used for to/transmit data from described flash memory; A plurality of memory buffer, each described memory buffer links to each other with described principal computer with relevant data bus, is used for depositing provisionally to the/data that transmit from flash memory; And one be used for controlling simultaneously described data bus and described memory buffer, so that visit the flicker storage control circuit of a plurality of flicker storage chips simultaneously, comprise a plurality of comparers, the status information and the predetermined reference information that are used for being provided by relevant flicker storage chip compare, and AND circuit, be used to provide the logic AND computing of described comparer output, thereby described AND circuit just provided one on the occasion of output signal after all flicker storage chips were all correctly operated in just thinking last time to operate.
Description of drawings
Rely on the following description and drawings, above and other objects of the present invention, feature and attendant advantages can be better understood, and have in the accompanying drawing:
Figure 1A is the block diagram according to flash memory system of the present invention;
Figure 1B shows the structure according to flash memory system of the present invention;
Fig. 2 is the detailed diagram of a part among Figure 1A; And
Fig. 3 is the block diagram of existing flash memory system.
Embodiment
Figure 1A and Fig. 2 show the block diagram according to flash memory system of the present invention, and Figure 1B shows the structure according to flash memory system of the present invention.In these figure, numeral 1 is a principal computer, the 2nd, the flicker memory controller, the 7th, flicker storage format control circuit, the 10th, flicker storage sequencer, the 12nd, the ECC control circuit, the 20th, be used for the flicker storage chip of low level (than low order), the 21st, be used for a high position (higher significance bit) the flicker storage chip, abbreviate flash memory sometimes as at this instructions flicker storage chip.Flash memory is realized by an EEPROM (EEPROM (Electrically Erasable Programmable Read Only Memo)). Numeral 22 and 23 is memory buffer, the 25th, be used for the data bus of low level, the 26th, be used for high-order data bus, the 27th, be used for the data bus of low level, the 28th, be used for the high position data bus, the 30th, address caching, 31 and 32 is comparers, the 33rd, the AND circuit, the 35th, be used for the door of transfer address information, the 36th, be used to transmit the door of bid value, the 37th, be used to transmit the door of low data, the 38th, be used to transmit the door of high position data, the 39th, be used to gather the door of high-end trim, the 40th, be used to gather the door of low-end trim, the 43rd, be used for the conveyer line of address value, the 44th, be used for the conveyer line of bid value, 45 and 46 is the lines that are used for the acquisition state value, the 47th, be used for the line of comparison state, the 50th, decision circuit, the 51st, counter, the 52nd, sequencer RAM (random access memory), and 53 are little preface code translators.
Figure 1B shows the structure of existing flash memory system.Flash memory system has plastic support 100.Flicker memory controller 2, and flicker storage chip 20 and 21 is potted in the described support 100.Supporting 100 also has to be used for a plug-in unit 102 that links to each other with principal computer.Though embodiment has two flicker storage chips among Figure 1B, also may install more than three flicker storage chips.Support 100 and also have 50 and SRAM storeies 52 of a microprocessor unit (MPU), be used to control the operation of flicker memory controller 2 and flicker storage chip 20 and 21.It is the address of flicker storage chip that SRAM storer 52 is used for the address translation from principal computer.Because parts 50 and 52 are used always, irrelevant with the present invention simultaneously, so they do not show in Figure 1A.
In exemplary embodiments, the size of flash card is that length L is 85.6mm among Figure 1B, and width W is 46mm, reaching thickness T is 5mm, and the capacity of every flicker storage chip is 2 megabyte simultaneously, and each byte is 8, thereby every pair of chip provides 4,000,000 8 byte, or 2,000,000 16 word.
(1) structure of embodiment (Figure 1A)
Figure 1A is the block diagram according to flash memory system of the present invention.Among the embodiment, flicker storage chip 20 and 21 is NAND type flicker storage chips, and it is write, reads, deletes and/or the read states operation by the flicker memory controller controls.
Shown in Figure 1A, flicker memory controller 2 is connected to pair of outer flicker storage chip 20 and 21, and each deposits low data (than low order) and high position data (higher significance bit) to chip.Flicker memory controller 2 also is connected to principal computer 1.
Be used for the flicker storage chip 20 of low level and be used for high-order flicker storage chip 21 that numerous flicker memory elements (flicker storage sets) can be arranged, so that these flicker memory elements are write independently, read, deleted and/or the read states operation.At embodiment 9, each piece has 8 in the flash memory chip 20 and 21, and each flicker memory element has 1.Suppose that the word in the principal computer is 16, and in described flicker storage chip, be divided into a high position of 8 and 8 low level.
NAND type flicker storage chip does not have the address end, but 3 byte address information can be delivered to data terminal so that select a memory block in internal storage region.
Flicker memory controller 2 has a main interface control circuit 5 and a flicker storage format control circuit 7.
Flicker storage format control circuit 7 has 27, one high-order buses 28 of flicker storage 10, one low level buses of sequencer, memory buffer (being used for principal computer) 22 and 23, and an ECC processor 12.
Flicker memory controller 2 has a microprocessor MPU and a SRAM (not shown), is used to control the built-in function of flicker memory controller.
Described functions of components is as follows.
(1) main interface control circuit 5 receives control signal to principal computer 1 transmission with from the latter, and its class of operation is similar to hard disk unit commonly used.
(2) low level bus 27 least-significant byte in 16 parallel positions is sent to/from principal computer 1.
(3) high-order bus 28 most-significant byte in 16 parallel positions is sent to/from principal computer 1.
(4) being sent to principal computer or when principal computer is sent to flash memory system from flash memory system when data, memory buffer 22 will deliver to/and least-significant byte in 16 parallel positions of principal computer stores.The control circuit (not shown) that the operation of memory buffer 22 is glimmered in the storage format control circuit 7 is controlled.
(5) being sent to principal computer or when principal computer is sent to flash memory system from flash memory system when data, memory buffer 23 will deliver to/and most-significant byte in 16 parallel positions of principal computer 1 stores.The control circuit (not shown) that the operation of memory buffer 23 is glimmered in the storage format control circuit 7 is controlled.
(6) ECC processor 12 is used for being write and is handled (error correction sign indicating number) by the ECC of read data, comprises ECC coding and decoding.
(7) flicker storage sequencer 10 is controlled low data bus 27 and high position data bus 28 simultaneously, so that visit simultaneously is used for the flicker storage chip 20 of low level and is used for high-order flicker storage chip 21.
(2) operation of flash memory control
When in the flicker storage chip during write data, be sent to flicker memory controller 2 with the form concurrently of 16 positions by having 8 data bus 25 and having 8 data bus 26 from the data of principal computer 1.
The data of depositing in the memory buffer 22 are sent to the flicker storage chip 20 that is used for low data by the data bus 27 that is used for low level.The data of depositing in the memory buffer 23 are sent to the flicker storage chip 21 that is used for a high position by being used for high-order data bus 28.
When from flicker storage chip 20 and 21 sense datas, be transmitted in the reverse direction that the described in the above data of data transmit.In other words, deposit in memory buffer 22 from the data (8) that the flicker storage chip 20 that is used for low level is read by low data bus 27, and deposit in memory buffer 23 by high position data bus 28 from the data (8) that the flicker storage chip 21 that is used for a high position is read.A pair of data in the data bus 27 and 28 are transmitted simultaneously, just as transmitting 16 bit parallel data.The data of depositing in then in memory buffer 22 and 23 are sent to principal computer 1 by data bus 25 and 26.
As described above, a pair of flicker storage chip that respectively has 8 bit data is visited simultaneously, thereby 16 bit data are accessed with parallel form.
Control to described flicker storage chip 20 and 21 is finished by flicker storage sequencer 10.Control to memory buffer 22 and 23 is finished by the control circuit (not shown) in the flicker storage format control circuit 7.
(3) flicker storage format control circuit (Fig. 2)
Fig. 2 has at length shown the part of Figure 1A.Now flicker form control circuit is described according to Fig. 2.
Flicker storage format control circuit 7 further comprises an address caching 30, an AND circuit 33, comparer 31 and 32, a door 35 that is used for the transfer address value, a door 36 that is used to transmit bid value, a door 37 that is used to transmit low data, a door 38 that is used to transmit high position data, 39, one 40, one lines 43 that are used for address value of door that are used to gather low-end trim that are used to gather high-end trim, article one, the line 44 that is used for bid value, be used for the line 45 and 46 of acquisition state value, and be used for state is sent to the line 47 of comparer, or the like.
Described address caching 30 is connected to a MPU (microprocessor unit by the MPU bus, not shown), deposit in provisionally in the described address caching 30 thereby make, in memory buffer, described address information read out to one by one flicker storage chip 20 and 21 then from the address information of the flicker storage chip that described MPU sends.
The operation of Fig. 2 is now described.
The typical operation of flash memory system is " writing " flash memory, " reading " flash memory, " read states " of " deleting " flash memory and flash memory.After " writing " operation, carry out " read states " operation immediately, so that whether normal running is operated in inspection " writing ".
(1) " write ", " reading " or " deleting " order
The line 44 that is used for bid value will be sent to flash memory at the bid value that flicker storage sequencer 10 generates by door 36, so that a value in the sign bid value (" writing ", " reading ", or the like).Bid value line 44 has 8 parallel positions.Described order is used to visit flash memory.
The line 43 that is used for address value sends flash memory to by 35 address value with address buffer 30 outputs that is used for address value.This address value is used to visit flash memory.
When data transmit between principal computer and flash memory system, provide the flash memory address by MPU and SRAM (static RAM (SRAM)), this SRAM has the conversion table between principal computer address and the flash memory address.Temporarily leave in the address caching 30 from the address that SRAM reads, be read out then, and by door 37 and 38 and data bus 27 and 28 deliver to the flicker storage chip.
Described bid value and described address value are delivered to the data bus 27 that is used for low level by the door 37 that is used for low level, and deliver to the data bus 28 that is used for a high position by being used for high-order door 38.
Then, bid value on the data bus 27 and address value are sent to the flash memory 20 that is used for low level, and the bid value and the address value that reach on the data bus 28 are sent to the flash memory 21 that is used for a high position.In the present embodiment, bid value and address value transmit by public data bus.
It should be noted that in above-mentioned explanation, when flash memory system carries out " writing " operation, the flicker storage chip is at first delivered in the order that is used to indicate " writing " operation, be then used in the address value of indicating flicker storage chip address in the described operation and deliver to the flicker storage chip from address caching 30, relevant with the described address of delivering to flash memory then data are delivered to flash memory from the memory buffer 22 and 23 that links to each other with principal computer 1.When order was ordered for " reading ", data transmission direction was opposite with " writing " order.When order is ordered for " deleting ", do not transmit any data.
According to bid value on data bus 27 and 28 and address value, visit flash memory 20 and 21 simultaneously with parallel form.
(2) " read states " order
When finishing " writing " order, whether the flicker storage chip is provided with a sign, correctly finish to show this write operation.Use the read states order to read this sign.Whether the memory controller that therefore glimmers is carried out the read states order immediately after write order, correctly carry out so that check write order just now.
A pair of comparer 31 and 32 is used for the comparison state value, so that 10 identifications of flicker storage sequencer are to the visit result of flash memory 20 and 21.
The normal condition that generates in the flicker storage sequencer 10 is delivered to the first input end of comparer 31 and 32 by line 47.Be used to indicate that the normal condition of correct " writing " operation for example is " 000 ".
Another input end of comparer 31 is by data bus 27 and the state values of door 40 receptions that are used for low level from flash memory 20, and another input end of comparer 32 is by data bus 28 and the state values of door 39 receptions that are used for a high position from another flash memory 21.
Comparer 31 and 32 compares two state values respectively.When two state values overlap mutually, each comparer output high level signal 1, otherwise output low level signal 0.
AND circuit 33 produces the value of the logic product of two comparers 31 and 32 output quantities.Therefore when two comparers 31 and 32 were all exported high level signal, AND circuit 33 provided high level signal, and this signal is sent to decision circuit 50.The high level signal of AND circuit 33 output indicates that least-significant byte and most-significant byte have all correctly been write in the flash memory.
When AND circuit output quantity was in high level, decision circuit 50 recognized the visit of flash memory 20 and 21 all successful, and when described output quantity is in low level, then recognized the visit failure.
Decision circuit 50 further receives order CD from little preface code translator 53, and receives 1NPUT from flash memory.Order CD notice decision circuit is operated, and when two flash memorys all were in standby condition rather than busy condition, the signal of 1NPUT end was effective.Therefore just think AND circuit 33 output high level output quantities, when order CD was effective for the signal on effective and the 1NPUT, decision circuit 50 just provided the high level output quantity.
The output quantity of decision circuit 50 adds on the counter 51, so that according to the content of the output quantity toggle count device 51 of decision circuit 50.
(4) flicker storage sequencer
Necessity operation of flash memory system is delivered to sequencer RAM52 by MPU by the MPU bus, so flicker storage sequencer begins operation.
At initial segment, counter 51 contents are zero.The content of counter 51 is increment one by one, or switches to predetermined value according to the output quantity of decision circuit 50.The content of counter 51 is added to be had 4 bytes and takes advantage of on the sequencer RAM52 of 32 words, command signal that is used to operate the flicker storage chip of address output that the latter provides according to counter 51.Sequencer RAM52 deposits the sign indicating number that is used to visit flash memory, and the microcode of one 4 byte is deposited at the zero-address place that reaches sequencer RAM52, is used to start flash memory.
Therefore, when counter 51 was delivered to sequencer RAM52 with zero-address, the zero-address content of sequencer RAM52 was read out, and the microcode that being used to of so reading from the zero-address place simultaneously starts flash memory is sent to little preface code translator 53.
According to the microcode from sequencer RAM52, little preface code translator 53 produces different control signals, bid value supplies the relatively reference value of usefulness, or the like.
When counter 51 increments, in sequencer RAM52 and microcode code translator 53, finish similar operations.
Therefore, according to the content of counter 51, sequencer RAM52 provides according to the content of counter 51 and fixed microcode, and little preface code translator 53 provides each circuit operation desired signal in flicker memory controller and the flicker storage chip.
For the people that are familiar with the technology of the present invention, can do some modifications.Have some to be among them:
(1) the foregoing description uses NAND type flicker storage chip.It should be noted that the flicker storage chip of certain available another kind of type among the present invention.
(2) be used for low level and be not limited to 8 buses, and 16 buses or any figure place all can be used for flash memory with the bus that is used for a high position.In such cases, bus must be consistent with the form of flicker storage chip.
(3) the foregoing description provides 16 bit parallel buses with 8 low data buses and 8 high position data buses.Should be appreciated that available 4 every 8 data bus is formed 32 bit parallel buses certainly, and available 8 every 8 data bus is formed 64 bit parallel buses.
At last, enumerate functions more of the present invention.
(1) the flicker memory controller has a pair of data bus and a pair of memory buffer, and does not have the external buffer memory of available technology adopting.Therefore directly be sent to the flicker storage chip from 16 bit parallel data of principal computer and needn't be sent to external buffer and deposit gauge.
In addition, 16 bit data that need deliver to principal computer are also directly delivered to principal computer.Therefore do not need transform data, thereby finish the operation of Writing/Reading flash memory fast.
(2) deposit in the memory buffer of flicker in the memory controller provisionally from the data of principal computer.Therefore the existence of described memory buffer makes throughput must cross improvement.
(3) a pair of data bus in the flicker memory controller is visited the flicker storage chip simultaneously, thereby makes a pair of flicker storage chip simultaneously accessed.Therefore the operating speed to flash memory is improved.
(4) caching is finished by the internal buffer memory in the flicker memory controller.Therefore, with the prior art with external buffer memory relatively, access time of flash memory is shortened.Also have, the throughput of reading flash memory also is improved.
(5) the flicker memory controller has 16 bit parallel buses, therefore needn't adopt time-sharing operation as prior art.Therefore the speed of Writing/Reading flash memory is improved.
Can obviously find out from the above, find the flash memory system of new improvement.Certainly should be appreciated that the disclosed embodiments are indicative, are not limited to the scope of the invention.Therefore except that instructions, more should wherein indicate the scope of the invention with reference to appended claims.
Claims (8)
1. a flash memory system that is connected to principal computer comprises:
A plurality of flicker storage chips; With
One is used to control the flicker memory controller that data transmit between described storage chip and the described principal computer;
Described flicker memory controller comprises:
Many data buss, every described bus is connected to relevant flash memory, be used for to/transmit data from described flicker storage chip,
One is connected to the address caching of described data bus by door, be used for providing address information to described flicker storage chip by described data bus,
A plurality of memory buffer, each described memory buffer is connected to relevant data bus and described principal computer, is used for depositing to/the data that transmit from the flicker storage chip temporarily,
One is used for controlling simultaneously described data bus and described memory buffer, so that visit the flicker storage sequencer of a plurality of flicker storage chips simultaneously with parallel form,
A plurality of comparers, the status information and the predetermined reference information that are used for being provided by relevant flicker storage chip compare, and
An AND circuit is used to provide the logic AND computing of described comparer output, thereby described AND circuit just provided one on the occasion of output signal after all flicker storage chips were all correctly operated in just thinking last time to operate.
2. according to the flash memory system of claim 1, wherein said data bus, described flicker storage chip, the quantity of described memory buffer and described comparer is 2.
3. according to the flash memory system of claim 1, wherein the data in every described data bus have parallel form.
4. according to the flash memory system of claim 1, wherein every described data bus not only transmits data, and transfer address and order are to the storage chip that glimmers.
5. according to the flash memory system of claim 1, wherein said flicker storage sequencer comprises a counter, a sequencer RAM who in the address that indicates by described counter, deposits instruction, one is connected to that described sequencer RAM is used for instruction decode so that decoded micro-order is delivered to the command decoder of flicker storage chip through described data bus, and the decision circuit of described counter content is adjusted in output according to described AND circuit.
6. according to the flash memory system of claim 1, wherein every described flicker storage chip has 8 in each address.
7. according to the flash memory system of claim 1, further comprise a support card that described flicker storage chip and described flicker memory controller are installed thereon, and described support card has a plug-in unit that is connected to principal computer.
8. a flicker memory controller is used to control the flicker storage chip and the data between the principal computer that link to each other with described controller and transmits, and described controller comprises:
Many data buss, every described bus links to each other with relevant flicker storage chip, be used for to/transmit data from described flash memory;
A plurality of memory buffer, each described memory buffer links to each other with described principal computer with relevant data bus, is used for depositing provisionally to the/data that transmit from flash memory; And
One is used for controlling simultaneously described data bus and described memory buffer, so that visit the flicker storage control circuit of a plurality of flicker storage chips simultaneously, comprise a plurality of comparers, the status information and the predetermined reference information that are used for being provided by relevant flicker storage chip compare, and AND circuit, be used to provide the logic AND computing of described comparer output, thereby described AND circuit just provided one on the occasion of output signal after all flicker storage chips were all correctly operated in just thinking last time to operate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB961011149A CN1136503C (en) | 1996-01-30 | 1996-01-30 | Flash memory system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB961011149A CN1136503C (en) | 1996-01-30 | 1996-01-30 | Flash memory system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1156280A CN1156280A (en) | 1997-08-06 |
| CN1136503C true CN1136503C (en) | 2004-01-28 |
Family
ID=5116936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB961011149A Expired - Fee Related CN1136503C (en) | 1996-01-30 | 1996-01-30 | Flash memory system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1136503C (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200515147A (en) * | 2003-10-17 | 2005-05-01 | Matsushita Electric Ind Co Ltd | Semiconductor memory device, controller, and read/write control method thereof |
| KR100526190B1 (en) * | 2004-02-06 | 2005-11-03 | 삼성전자주식회사 | Remapping method for flash memory |
| CN100397380C (en) * | 2005-12-27 | 2008-06-25 | 北京中星微电子有限公司 | Multi-channel flash memory transmission controller, chip and storage device |
| US20200201562A1 (en) * | 2018-12-20 | 2020-06-25 | Nanya Technology Corporation | Memory device, memory system and method of reading from memory device |
| US11928341B2 (en) | 2022-02-24 | 2024-03-12 | Changxin Memory Technologies, Inc. | Sleep control method and sleep control circuit |
| CN116701044A (en) * | 2022-02-24 | 2023-09-05 | 长鑫存储技术有限公司 | Data transmission circuit and data transmission method |
| KR20230129499A (en) | 2022-02-24 | 2023-09-08 | 창신 메모리 테크놀로지즈 아이엔씨 | Data error correction circuit and data transmission circuit |
| EP4258267A4 (en) | 2022-02-24 | 2024-04-24 | Changxin Memory Tech Inc | Data transmission circuit, data transmission method, and memory |
-
1996
- 1996-01-30 CN CNB961011149A patent/CN1136503C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1156280A (en) | 1997-08-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI659359B (en) | Method for controlling storage device | |
| US8909854B2 (en) | Memory device with specified write data size | |
| TWI376603B (en) | Solid state disk storage system with a parallel accessing architecture and a solid state disk controller | |
| CN1088215C (en) | Memory controller which executes read and write commands out of order | |
| US8799605B2 (en) | Initializing and writing to a nonvolatile storage device based on a client/server model | |
| US7970982B2 (en) | Memory card and memory system having the same | |
| JP2000067574A (en) | Semiconductor memory | |
| KR20100091379A (en) | Solid state disk device and program fail processing method thereof | |
| JP7229326B2 (en) | Controllers, memory devices and hosts associated with memory addressing methods | |
| CN100337217C (en) | Memory control chip and data memory control method | |
| US20200167273A1 (en) | Memory system and operation method thereof | |
| CN1136503C (en) | Flash memory system | |
| CN1040104A (en) | The delay high-speed memory write operation start-up circuit that is used for the double-bus microsystem | |
| Micheloni et al. | Solid state drives (ssds) | |
| TWI749903B (en) | Flash memory controller, memory device and method for accessing flash memory module | |
| CN106919343B (en) | Peripheral interface circuit and peripheral memory system | |
| CN110069427B (en) | Memory controller and operation method thereof | |
| CN1438583A (en) | Device for monitoring computer system resource and communicatin method of serial bus and said resource | |
| CN1514372A (en) | Low Power high speed buffer storage and its method of rapid access data | |
| KR100222908B1 (en) | Flash memory system | |
| US20160239224A1 (en) | Method and system for transferring data over a plurality of control lines | |
| CN1624673A (en) | Data transfer apparatus | |
| CN1295624C (en) | Cache memroy and controlling method | |
| CN113050881A (en) | Apparatus and method for improving input/output throughput of memory system | |
| US11112976B2 (en) | Data storage device that stores multiple values corresponding to multiple keys in a page |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040128 Termination date: 20120130 |