CN100337217C - Memory control chip and data memory control method - Google Patents
Memory control chip and data memory control method Download PDFInfo
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- CN100337217C CN100337217C CNB03140023XA CN03140023A CN100337217C CN 100337217 C CN100337217 C CN 100337217C CN B03140023X A CNB03140023X A CN B03140023XA CN 03140023 A CN03140023 A CN 03140023A CN 100337217 C CN100337217 C CN 100337217C
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Abstract
The present invention relates to a memory control chip, which is used for controlling data access of a semiconductor storage medium and data transmission of a host. The present invention comprises a processor as a controller of the whole chip, a protocol realization controller connected with the processor, an exterior memory medium controller connected with the processor, an interior memory module, a register group, a DMA controller and a data checking module, wherein the processor mainly controls the access and the transmission of data and the setting of parameters; the protocol realization controller enables the data transmission to conform to the protocol standard; the exterior memory medium controller controls the data access of an exterior memory medium; the interior memory module memorizes an application program and/or a system program of the memory control chip and can be used as a buffering memory for the data transmission of the memory control chip; the register group can set control parameters and state parameters; the DMA controller realizes rapid data transmission; the data checking module adopts on-line codec to realize rapid checking in the data transmission. The present invention has the advantages of rapid and correct data transmission, and high reliability for the data transmission.
Description
Technical field
The present invention relates to computer chip technology, relate in particular to the method for the design and the data storage control of storage control chip.
Background technology
The continuous development of semiconductor memory technologies is for having opened up new space in data mobile storage field.Little because of the semiconductor storage small product size, capacity is big, zero access, easy to carry, stable performance, advantage such as not fragile and obtained the application of more and more popularizing.Especially with flash memory (FLASHMemory) the semiconductor storage product of storage medium, become the mobile storage application products of personal data of new generation more, and be applied to the storage control chip of such semiconductor storage product, become the core component of its data access of control especially.At present, use H8S3664, H8S2215 that storage control chip more widely comprises Hitachi company at home and abroad, the ST92163 of ST company, the 6633B2 of 3S company etc.
Yet, most of storage control chips all carry out data access by the processor control mode, promptly carry out data access by modes such as programmed control output input or interrupt control output inputs, these modes need a large amount of time of processor to check and wait for or spend a large amount of time to carry out Interrupt Process, make that data access speed is low, response time is long, thereby cause inefficiency, thereby, there is the mode of direct memory access (DMA) (DMA) to occur, dma mode is to increase dma controller to replace central processing unit work, data are in batch carried out direct access, this mode is except needing the processor intervention when the starting and ending of data block, finish the access of data by dma controller, thereby make processor in the data access process, can carry out other work, improved work efficiency greatly.But therefore the function that does not have data check and correctness to ensure in its chip is easy to make a mistake in the reading and writing data process, influences the correctness of data access.
Thereby some chip is provided with the function of check and correction, for example odd-even check (Parity) and bug check and correction (ECC) etc. in order to overcome above-mentioned shortcoming on function setting.But, this class has the control chip of data check and correctness security function now, all can not immediately carry out the correctness inspection at data transmission procedure to data, and just just whether the data transmitted of inspection correct later on transmit one piece of data, thus can not immediately ensure transmit the correctness and the integrality of data; And, because after having transmitted one piece of data, test again and correct, taken the working time of processor, reduced the efficient of processor.In addition, the dma mode of storage control chip only provides a kind of DMA transport-type mostly, for example from the first memory to the second memory, do not provide the data that memory erase, programming etc. are required directly to be transferred to the DMA transport-type of storer etc., the DMA transport-type of the data transmission of its data direct access control is few, thus the dirigibility of influence operation.
Summary of the invention
The objective of the invention is on the prior art basis, deficiency at the prior art application, a kind of DMA of having function, On line inspection and the function of correcting a mistake are provided, and the storage control chip of multiple DMA transport-type and the method for its realization data access can be provided, realize the zero access of user data.
Storage control chip of the present invention can be achieved through the following technical solutions:
A kind of storage control chip, be used to control semiconductor storage medium data access and with the data transmission of main frame, comprising:
Processor, as the controller of entire chip, the setting of the access of major control data, transmission and parameter;
Agreement realizes controller, is connected with processor, makes data transmission protocol compliant standard;
The exterior storage medium controller is connected with processor, the data access of control exterior storage medium;
The storage inside module is stored the application program and/or the system program of described storage control chip, and can be used as the buffer memory that described storage control chip carries out data transmission;
Registers group can be provided with controlled variable and state parameter;
Dma controller realizes that with processor, agreement controller, exterior storage medium controller are electrically connected at least, and the realization data are transmitted fast; And
The data check module realizes that with dma controller, agreement controller and exterior storage medium controller are connected, and adopts online encoding and decoding, realizes the quick verification in the data transmission.
Storage control chip of the present invention realizes that data access can also realize by following scheme:
A kind of storage control chip is realized the method for data access, when storage control chip when carrying out data access, also comprise the steps:
1) by the parameter of processor definition dma controller, the DMA data transmission of dma controller is set, the parameter of data check module is set according to data transmission simultaneously;
2) dma controller is carried out the DMA data transmission according to the set data transfer mode of described data transmission, adopts online encoding and decoding to realize the quick verification of data in data transmission;
3) described dma controller is exported dma controller transmission sign according to the result of data transmission;
4) described processor is inquired about described dma controller transmission sign or dma controller generation interruption, and processor is made the operation of end data transmission according to transmission sign of inquiring about or interruption.
Described registers group comprises the processor control register, processor status register, processor address register, the DMA control register, the dma state register, the DMA counter register, agreement realizes control register, agreement realizes status register, agreement realizes counter register, the exterior storage medium counter register, storage inside module's address register, the exterior storage medium address register, the exterior storage medium command register, data check control register and/or data check status register.
Described DMA data transmission includes but not limited to: from agreement realize controller to exterior storage medium controller, agreement realize controller realize to storage inside module, storage inside module to agreement controller, storage inside module to exterior storage medium controller, exterior storage medium controller to the storage inside module, the data transmission of exterior storage medium controller to storage inside module (last 16 bytes of sector), exterior storage medium controller to agreement realization controller, and to the programming of the wiping of exterior storage medium, exterior storage medium.
Storage control chip of the present invention can be by being provided with dma controller and realizing carrying out data access with the several data transmission mode by setting the related register parameter, and by bug check with correct function and immediately online the data of being transmitted are carried out error correction and error detection, have access speed soon, advantage such as stable performance, mistake incidence be low.
Description of drawings
Fig. 1 is a hardware structure synoptic diagram of the present invention;
Fig. 2 is an embodiment of the invention hardware structure synoptic diagram;
Fig. 3 is the process flow diagram of embodiment of the invention data DMA transmission;
Fig. 4 is a second embodiment of the invention hardware structure synoptic diagram;
Fig. 5 is a third embodiment of the invention hardware structure synoptic diagram.
Embodiment
The realization of the object of the invention, functional characteristics and advantage will be in conjunction with the embodiments, are described further with reference to accompanying drawing.
See also Fig. 1, storage control chip 1 of the present invention is used to connect exterior storage medium 3 and system host 5, and control data in a large number, fast and correctly transmits, divide from functional module, comprise that processor (MCU) 20, dma controller 30, agreement realize controller 40, exterior storage medium controller 50, data check module 60, storage inside module 70, PLL module 80 and registers group 90.
Here said exterior storage medium 3 is meant but is not limited to SDRAM, DRAM, EPPROM, static RAM (SRAM), ferromagnetic random access memory/ferroelectric memory (FRAM), magnetic random access memory (MRAM), ultrahigh density storage chip (MILLIPEDE), flash media (FLASH Memory) etc.Here said system host 5 is meant but is not limited to PC, notebook computer, palm PC, PDA (Personal Digital Assistant) (PDA), digital album, digital camera, Digital Video etc.
Described processor 20 can adopt programmable single chip computer, and (microcontroller MCU) as the controller of whole storage control chip, can also adopt dsp controller, Risc controller, X86 controller etc.Realize controller 40, exterior storage medium controller 50, data check module 60, storage inside module 70, PLL module 80 and registers group 90 etc. by visit, above-mentioned dma controller 30, the agreement of control, realize functions such as control above-mentioned functions module, parameter configuration.
Described dma controller 30 connects and is controlled by above-mentioned processor 20, and the instruction of sending by this processor 20 starts dma controller 30.And this dma controller 30 can be set up the DMA data transmission channel by calling parameter and the parameter value in the described registers group 90, finishes the quick transfer function of data of different DMA transport-types.
Described agreement realizes that controller 40 mainly is to realize carrying out exchanges data with system host 5, comprising: encoding and decoding, school inspection, position filling, geocoding, conversion etc., thereby make and system host between exchanges data meet corresponding consensus standard.
Described data check module 60 be in the process of exchanges data by online encoding and decoding, can adopt but be not limited to the online encoding and decoding of Hamming code (Hamming Code) or RS (Reed-Soloman) sign indicating number etc., ensure the correctness of data.This data check module 60 is when the DMA data exchange channel is set up, promptly comes into operation.
This storage inside module 70 can comprise ROM and/or RAM as the internal memory of whole storage control chip.Wherein, ROM mainly is storage control entire chip application program operating and/or system program; The buffer memory that RAM moves as application program, and can store by exterior storage medium 3 or/and the data that system host 5 transmission come.Described RAM can select for use but be not limited to SRAM, DRAM, SDRAM, MRAM, FRAM etc.
Described exterior storage medium controller 50 is the read-write sequences that are used for controlling exterior storage medium.Can be (but being not limited to) flash media controller, MRAM controller, ultrahigh density storage medium controller or the like.Described PLL module 80 is then controlled the clock of entire chip, and 48MHz, 24MHz and 12MHz can be provided.
Described registers group 90 comprises a plurality of registers, can set and store the parameter and the parameter value of the acquiescence of each controller, module correspondence respectively.This registers group 90 comprises at least: the processor control register, processor status register, processor address register, the DMA control register, the dma state register, the DMA counter register, agreement realizes control register, agreement realizes status register, agreement realizes counter register, the exterior storage medium counter register, RAM address register, the exterior storage medium address register, the exterior storage medium command register, the data check control register, data check status register etc.
Fig. 2 is the block scheme of the preferred embodiment of storage control chip of the present invention.See also Fig. 2, the present invention is further elaborated below in conjunction with a kind of preferred implementation of storage control chip of the present invention.
This storage control chip 1 comprises processor 20, dma controller 30, usb protocol realization controller 41, flash media controller 51, online ECC module 61, storage inside module 70, PLL module 80 and registers group 90.Wherein this usb protocol realizes that controller 41 is a kind of embodiments that agreement realizes controller 40; Flash media controller 51 is a kind of embodiments of exterior storage medium controller 50; Online ECC module 61 is a kind of embodiments of data check module 60; The storage inside module 70 here comprises ROM72 and SRAM71.With flash media controller 51 correspondingly, exterior storage medium 3 can be selected flash media 31 for use.
Described processor 20 adopts 8 compatible single-chip microcomputers of 8051 instructions, as the controller of entire chip.Described processor 20 realizes that by visit, control dma controller 30, agreement controller 41, flash media controller 51, online ECC module 61, storage inside module 70 and PLL module 80 realize data access function.The application program of this storage control chip 1, system program and other relevant specific informations (for example product information, user profile etc.) can be stored in the storage inside module 70, directly call for processor 20.
Described dma controller 30 connects and is controlled by above-mentioned processor 20, and the instruction of sending by this processor 20 starts dma controller 30, and transmits (detailed aftermentioned) by the DMA of dma controller 30 control datas.
Described usb protocol realizes that controller 41 can carry out exchanges data with system host 5.This usb protocol realizes that controller 41 is by the encoding and decoding of finishing reversing non-return to zero system (NRZI), the generation of CRC (CRC) and the functions such as conversion of end-point addresses coding, differential signal and digital signal that verification, position filling, USB wrap, make and exchange the requirement of data fit USB standard agreement with system host 5.
Described flash media controller 51 can be connected with external flash medium 31, and the read-write sequence of the data access of control external flash medium 31.
Described online ECC module 61 adopts the online encoding and decoding of Hamming code (Hamming Code), finishes 1 error correction of data and the function of two error detections.This single bit error that entangles an inspection two function can correction data, storer is not because of single mistake interruption of work, so its Mean Time Between Failures increase has improved correctness and reliability.Described PLL module 80 is then controlled the clock of whole storage control chip 1, realizes the Clock management function.
Described registers group 90 is provided with a plurality of registers, can comprise processor control register, processor status register, processor address register, DMA control register, dma state register, SRAM address register, DMA counter register, FLASH address register, FLASH command register, USB control register, USB counter register, FLASH counter register, ECC control register, ECC status register etc.Understandable, the registers group 90 of storage control chip 1 of the present invention can also include but not limited to that FLASH buffer register, FLASH sheet select register, FLASH order that register, FLASH status register, USB status register, ECC result register etc. are set.
Each register of above-mentioned registers group 90 can pre-defined dma controller 30 carries out most of parameter of data transmission, this design will greatly reduce the initialization time of operating the DMA data manipulation from processor data, at some in particular cases, if described predefined parameter value does not have the match operation request, processor 20 can also be revised it.
It is mainly to call relevant register parameters to finish that dma controller 30 of the present invention carries out data transmission, promptly calls the default parameter value of DMA control register, SRAM address register, USB counter register, FLASH counter register, FLASH address register, FLASH command register etc. and finishes dissimilar DMA data transmission.And, DMA data transmission of the present invention mainly is to be undertaken by the parameter of calling the DMA control register, and can be implemented in line ECC function in the DMA data transmission procedure, so following parameter to described DMA control register and ECC control register describes.
The parameter that described DMA control register is set mainly comprises DMA_EN, DMA_DONE, DMA_TYPE, USB_EPT, USE_DEFAULT, and it is as follows respectively that its parameter function and being provided with is described:
Parameter DMA_EN is mainly used in switching operation modes, and its default value is 0, and the default mode of operation of storage control chip 1 promptly of the present invention is a processor mode, is controlled by all of data lines and the address wire of 20 pairs of these storage control chips 1 of processor; When its parameter value is set to 1, then switch to the DMA pattern, promptly control by the data line and the address wire of 30 pairs of these storage control chips 1 of dma controller, after data are finished the DMA transmission, described dma controller 30 is set to 0 once more with this parameter value, makes storage control chip 1 be under the processor mode.
Parameter DMA_DONE is mainly used in the look-at-me that produces processor 20 input ports, and its default value is 1.Described processor 20 must be when the DMA_EN parameter be set with its clear 0, make described processor 20 not produce the look-at-me input, after described dma controller 30 was finished the DMA data transmission, it was set to 1, promptly produced stage casing signalisation processor 20 its data and had finished the DMA transmission.
Parameter USB_EPT is mainly used in indication and realizes the DMA transmission of controller 41 about usb protocol, and its parameter value is 0 o'clock, and the expression data transmission realizes controller 41 to usb protocol, when its parameter value is 1, represents that then data realize that from usb protocol controller 41 sends.When the DMA of data transmission realized that with usb protocol controller 41 has nothing to do, its parameter value can be an arbitrary value.
The parameter value of parameter USE_DEFAULT becomes at 1 o'clock from 0, and the register relevant with data DMA transmission obtains default value, and address, size of data that DMA transmits are carried out the initialization setting.
Parameter DMA_TYPE is mainly used in definition DMA data transmission, its data transmission can be polytype, for example: realize that from usb protocol controller 41 is transferred to the DMA data transmission of the buffer area of SRAM71, realizes that from usb protocol DMA data transmission, SRAM71 that controller 41 is transferred to flash media controller 51 are transferred to DMA data transmission of flash media controller 51 or the like, also define the operation of some non-DMA data transmission that outside flash media 31 is carried out simultaneously, for example: wipe, programme or other order.
The major parameter of described ECC control register is ECC_EN, is mainly used in the work of switching online ECC module 61, and its default value is 1, and online ECC function is opened, and promptly carries out online error correction in the process of carrying out the DMA data transmission.When part did not need the non-DMA data transmission (for example wiping outside flash media 3) of error detection or error correction, the ECC_EN parameter value then was 0, and promptly online ECC module 61 need not work.
The switching of two kinds of operator schemes of the present invention (processor mode and DMA pattern) is to control by being provided with of parameter DMA_EN.Its default mode is a processor mode, and under this pattern, described processor 20 is to be undertaken initialized by the look-at-me that usb protocol realization controller 41 transmits.At any time, when system host 5 needs processor 20 response, then effective look-at-me of low state can notification processor 20, and then, processor 20 is determined the response action by reading the state that usb protocol realizes that the detection of controller 41 is interrupted.If this response does not need data transmission, processor 20 can be handled this request; If this response requires data transmission, then dma controller 30 carries out initialization by processor 20, enters the DMA pattern then, finishes the DMA transmission up to data.
When parameter DMA_EN was " 0 ", entire chip was in processor mode, and all data and address bus are directly controlled by processor 20.This processor 20 can be realized controller 41, flash media controller 51 and each register etc. by instruction access storage inside modules 70 such as MOVX, usb protocol, and this processor mode is mainly used in the configuration that usb protocol is realized controller 41.
When parameter DMA_EN was " 1 ", entire chip was in the DMA pattern, and all data and address bus are directly controlled by dma controller 30.12 kinds of DMA data transmission (certainly, can greater or less than 12 kinds) wherein can be arranged, wherein can comprise the order of the non-DMA data transmission that some are finished by dma controller 30 controls.Selecting for use of above-mentioned DMA data transmission is to control by processor 20 to select for use the parameter value of the parameter DMA_TYPE in the DMA control register to realize.And when the passage of DMA data transmission was set up, processor 20 was provided with the parameter ECC_EN of ECC control register according to the DMA data transmission, starts or stops online ECC module 61.This online ECC module 61 is to adopt the online encoding and decoding of Hamming code, finishes an error correction to data, the function of two error detections, thereby guarantees the correctness and the reliability of data transmission.
DMA data transmission recited above includes but not limited to realize that from usb protocol controller 41 is transferred to flash media controller 51, usb protocol is realized controller 41 to SRAM71, SRAM71 realizes controller 41 to usb protocol, SRAM71 is to flash media controller 51, flash media controller 51 to SRAM71, flash media controller 51 to SRAM71 (last 16 bytes of flash sector), flash media controller 51 is realized controller 41 to usb protocol, wiping of external flash medium 31, the programmings of external flash medium 31 etc. also comprise other operational orders of external flash medium 31 and busy signal check etc.Above-mentioned dissimilar DMA data transmission can by DMA transmission effectively (is provided with by parameter DMA_EN), DMA transport-type (parameter value that call parameters DMA_TYPE is suitable) is set, carry out the DMA data transmission (carrying out on-line testing simultaneously), inquiry DMA transmission sign or produce the DMA transmission and finish processes (as shown in Figure 3) such as interruption (as parameter USB_EPT etc.), and the default parameter value of calling corresponding register is finished the DMA data transmission.
Be transferred to the example of external flash medium 31 with data from system host 5 below, come data transmission of the present invention is done further to set forth.
At first, data are transferred to usb protocol from system host 5 and realize controller 41, and this usb protocol realizes that 41 pairs of these data of controller carry out encoding and decoding, verification, position filling, geocoding, conversion etc., make the data type conformance with standard.
Then, produce look-at-me, need carry out data transmission to processor 20 requests of sending.This processor 20 detects and need carry out realizing that from usb protocol controller 41 is transferred to the data transmission of flash media controller 51, then whether the parameter of the register that processor 20 detections are relevant is default value, if not, 20 of processors are revised it, make it can meet data and realize that from usb protocol controller 41 is transferred to the DMA transmission requirement of flash media controller 51; Wherein, Xiang Guan register includes but not limited to that USB counter register, DMA counter register, FLASH address register, FLASH command register, FLASH sheet select register, FLASH status register, FLASH counter register etc.
Then, 20 pairs of DMA control registers 30 of processor are provided with, the parameter value that is about to parameter DMA_DONE is set to 0, selecting parameter DMA_TYPE is that usb protocol realizes that controller 41 is transferred to flash media controller 51, the parameter value that parameter USE_DEFAULT is set is 1, promptly from register parameters, obtain parameter value, the parameter value that parameter USB_EPT is set is 1, the parameter value that parameter DMA_EN is set is 1, simultaneously, processor 20 is according to selected DMA data transmission, the parameter ECC_EN that the ECC control register is set is 1, be that online ECC module 61 is in running order, begin the DMA transmission of data then.Data will be that ground, unit realizes that from usb protocol controller 41 is transferred to flash media controller 51 with a byte, in this process, online ECC module 61 will adopt the online encoding and decoding of Hamming code, finish an error correction to data, the function of two error detections, thereby guarantee the correctness and the reliability of data transmission.
At last, control, write data in the external flash medium 31, until finishing the transmission that all require the transmission data by the read-write sequence of 51 pairs of outside flash medias 31 of flash media controller.After the DMA data transmission is finished, processor 20 poll-final signs or dma controller 30 produce the interrupt notification processor 20 that the DMA transmission is finished, then processor 20 control dma controllers 30 finish the DMA transmission with the value of parameter reconfiguration DMA_DONE, removing parameter DMA_EN and USE_DEFAULT.
Seeing also Fig. 4, is second embodiment of storage control chip 1 of the present invention, and agreement realization controller 40 wherein recited above can select for use the IEEE1394 agreement to realize controller 42.This IEEE1394 agreement realizes that controller 42 foundation are connected with the IEEE1394 of system host 5, the explanation of responsible IEEE1394 agreement, conversion, control, transmission etc., make data transmission meet the IEEE1394 consensus standard, the data transmission between realization and the system host 5.Correspondingly, USB counter register, USB control register etc. use IEEE1394 counter register, IEEE1394 control register to be replaced.And making IEEE1394EPT accordingly into, the parameter USB_EPT of DMA control register gets final product.
When data when system host 5 is transferred to the IEEE1394 agreement and realizes controller 42, at first, this IEEE1394 agreement realizes that 42 pairs of these data of controller carry out encoding and decoding, verification, position filling, geocoding, conversion etc., makes the data type conformance with standard.
Then, produce and interrupt, send request to processor 20.This processor 20 detects and need carry out realizing that from the IEEE1394 agreement controller 42 is transferred to the data transmission of flash media controller 51, then whether the parameter of the register that processor 20 detections are relevant is default value, if not, 20 of processors are revised it, make it can meet data and realize that from the IEEE1394 agreement controller 42 is transferred to the DMA transmission requirement of flash media controller 51; Wherein, Xiang Guan register includes but not limited to that FLASH address register, FLASH command register, FLASH sheet select register, FLASH status register, FLASH counter register etc.
Then, 20 pairs of DMA control registers 30 of processor are provided with, the parameter value that is about to parameter DMA_DONE is set to 0, select parameter DMA_TYPE to realize that for the IEEE1394 agreement controller 42 is transferred to flash media controller 51, the parameter value that parameter USE_DEFAULT is set is 1, promptly from its acquiescence register parameters, obtain default value, the parameter value that parameter I EEE1394_EPT is set is 1, the parameter value that parameter DMA_EN is set is 1, simultaneously, processor 20 is according to selected DMA data transmission, the parameter ECC_EN that the ECC control register is set is 1, be that online ECC module 61 is in running order, begin the DMA transmission of data then.Data will be that ground, unit realizes that from the IEEE1394 agreement controller 42 is transferred to flash media controller 51 with a byte, in this process, online ECC module 61 will adopt the online encoding and decoding of Hamming code, finish an error correction to data, the function of two error detections, thereby guarantee the correctness and the reliability of data transmission.
At last, control, write data in the external flash medium 31, until finishing the transmission that all require the transmission data by the read-write sequence of 51 pairs of outside flash medias 31 of flash media controller.After the DMA data transmission was finished, dma controller 30 was with the value of parameter reconfiguration DMA_DONE, removing parameter DMA_EN and USE_DEFAULT, and generation interrupt notification processor 20 has been finished the DMA transmission of data.
Seeing also Fig. 5, is the 3rd embodiment of storage control chip 1 of the present invention, and agreement realization controller 40 wherein recited above can select for use Bluetooth protocol to realize controller 43.This Bluetooth protocol realizes that controller 43 is set up and the wireless connections of system host 5, and the explanation of responsible Bluetooth protocol, conversion, control, transmission etc. make data transmission meet the Bluetooth protocol standard, realize the unlimited data transmission with system host 5.Correspondingly, USB counter register, USB control register etc. use bluetooth counter register, Bluetooth control register to be replaced.And making BLUETOOTH_EPT accordingly into, the parameter USB_EPT of DMA control register gets final product.
When data when system host 5 is transferred to Bluetooth protocol and realizes controller 43, at first, this Bluetooth protocol realizes that 43 pairs of these data of controller carry out encoding and decoding, verification, position filling, geocoding, conversion etc., makes data type meet the Bluetooth protocol standard.
Then, produce and interrupt, send request to processor 20.This processor 20 detects and need carry out realizing that from Bluetooth protocol controller 43 is transferred to the data transmission of flash media controller 51, then whether the parameter of the register that processor 20 detections are relevant is default value, if not, 20 of processors are revised it, make it can meet data and realize that from Bluetooth protocol controller 42 is transferred to the DMA transmission requirement of flash media controller 51; Wherein, Xiang Guan register includes but not limited to that FLASH address register, FLASH command register, FLASH sheet select register, FLASH status register, FLASH counter register etc.
Then, 20 pairs of DMA control registers 30 of processor are provided with, the parameter value that is about to parameter DMA_DONE is set to 0, selecting parameter DMA_TYPE is that Bluetooth protocol realizes that controller 43 is transferred to flash media controller 51, the parameter value that parameter USE_DEFAULT is set is 1, promptly from its acquiescence register parameters, obtain default value, the parameter value that B parameter LUETOOTH_EPT is set is 1, the parameter value that parameter DMA_EN is set is 1, simultaneously, processor 20 is according to selected DMA data transmission, the parameter ECC_EN that the ECC control register is set is 1, be that online ECC module 61 is in running order, begin the DMA transmission of data then.Data will be that ground, unit realizes that from Bluetooth protocol controller 43 is transferred to flash media controller 51 with a byte, in this process, online ECC module 61 will adopt the online encoding and decoding of Hamming code, finish an error correction to data, the function of two error detections, thereby guarantee the correctness and the reliability of data transmission.
At last, control, write data in the external flash medium 31, until finishing the transmission that all require the transmission data by the read-write sequence of 51 pairs of outside flash medias 31 of flash media controller.After the DMA data transmission was finished, dma controller 30 was with the value of parameter reconfiguration DMA_DONE, removing parameter DMA_EN and USE_DEFAULT, and generation interrupt notification processor 20 has been finished the DMA transmission of data.
Understandable, described agreement realization controller 40 can also select for use other agreements to realize controller, and for example the infrared ray agreement realizes that controller, PCMCIA agreement realize that controller, local area network wireless agreement (as 802.11a, 802.11b, 802.11g etc.) realize that controller, super wideband (UWB) agreement realization controller, short-distance wireless communication (Zigbee) agreement realize controller etc.
Claims (13)
1. storage control chip, be used to control semiconductor storage medium data access and with the data transmission of main frame, comprising:
Processor, as the controller of entire chip, the setting of the access of major control data, transmission and parameter;
Agreement realizes controller, is connected with processor, makes data transmission protocol compliant standard;
The exterior storage medium controller is connected with processor, the data access of control exterior storage medium;
The storage inside module is stored the application program and/or the system program of described storage control chip, and can be used as the buffer memory that described storage control chip carries out data transmission;
Registers group can be provided with controlled variable and state parameter;
Dma controller realizes that with processor, agreement controller, exterior storage medium controller are electrically connected at least, and the realization data are transmitted fast; And
The data check module realizes that with dma controller, agreement controller and exterior storage medium controller are connected, and adopts online encoding and decoding, realizes the quick verification in the data transmission.
2. storage control chip according to claim 1 is characterized in that: can work in processor mode and/or DMA pattern.
3. storage control chip according to claim 1 is characterized in that: described processor can be microcontroller, dsp controller, Risc controller or X86 controller.
4. storage control chip according to claim 1 is characterized in that: described agreement realizes that controller can be that usb protocol realizes that controller, IEEE1394 agreement realize that controller, Bluetooth protocol realization controller, infrared ray agreement realize that controller, PCMCIA agreement realize that controller, UWB agreement realize that controller, Zigbee agreement realize controller and/or local area network wireless agreement realization controller.
5. storage control chip according to claim 1 is characterized in that: described data check module can be to adopt the ECC module of Hamming code, the online encoding and decoding of RS sign indicating number.
6. according to each described storage control chip in the claim 1 to 5, it is characterized in that: described exterior storage medium controller can be flash media controller, MRAM controller, ultrahigh density storage medium controller.
7. storage control chip according to claim 6 is characterized in that: described registers group comprises the processor control register, processor status register, processor address register, the DMA control register, the dma state register, the DMA counter register, agreement realizes control register, agreement realizes status register, agreement realizes counter register, the exterior storage medium counter register, storage inside module's address register, the exterior storage medium address register, the exterior storage medium command register, data check control register and/or data check status register.
8. storage control chip according to claim 7, it is characterized in that: described agreement realizes that control register can be USB control register, IEEE1394 control register or Bluetooth control register, and described agreement realizes that counter register can be USB counter register, IEEE1394 counter register or bluetooth counter register.
9. storage control chip according to claim 7, it is characterized in that: described exterior storage medium counter register can be the FLASH counter register, described exterior storage medium address register can be the FLASH address register, described exterior storage medium command register can be the FLASH command register, and described data check control register can be the ECC control register.
10. storage control chip according to claim 7 is characterized in that: described registers group can also be that FLASH buffer register, FLASH sheet select register, FLASH order that registers such as register, FLASH status register, ECC result register are set.
11. a storage control chip according to claim 1 is realized the method for data access, it is characterized in that: when storage control chip when carrying out data access, also comprise the steps:
By the parameter of processor definition dma controller, the DMA data transmission of dma controller is set, the parameter of data check module is set according to data transmission simultaneously;
2) dma controller is carried out the DMA data transmission according to the set data transfer mode of described data transmission, adopts online encoding and decoding to realize the quick verification of data in data transmission;
3) described dma controller is exported dma controller transmission sign according to the result of data transmission;
4) described processor is inquired about described dma controller transmission sign or dma controller generation interruption, and processor is made the operation of end data transmission according to transmission sign of inquiring about or interruption.
12. method according to claim 11 is characterized in that: described processor can call the parameter of described registers group and parameter value or the parameter and the parameter value of described registers group are revised.
13. method according to claim 11 is characterized in that: described DMA data transmission comprises: from agreement realize controller to exterior storage medium controller, agreement realize controller realize to storage inside module, storage inside module to agreement controller, storage inside module to exterior storage medium controller, exterior storage medium controller to the storage inside module, exterior storage medium controller data transmission, the wiping and/or the programming of exterior storage medium of realizing controller to agreement to exterior storage medium.
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| WO2007048287A1 (en) * | 2005-10-28 | 2007-05-03 | Chipsbank Technologies (Shenzhen) Co., Limited | Memory device with control chip having compatible configure function and manufacturing method thereof |
| KR101425957B1 (en) * | 2007-08-21 | 2014-08-06 | 삼성전자주식회사 | Ecc control circuit and multi channel memory system icluding the same |
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| US8205031B2 (en) | 2008-08-19 | 2012-06-19 | Sonix Technology Co., Ltd. | Memory management system and method thereof |
| CN101958152B (en) * | 2010-10-19 | 2013-02-13 | 华中科技大学 | NAND FLASH controller and application thereof |
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