CN113627108B - Automatic searching method and system for maximum running frequency of cryptographic algorithm in FPGA - Google Patents

Automatic searching method and system for maximum running frequency of cryptographic algorithm in FPGA Download PDF

Info

Publication number
CN113627108B
CN113627108B CN202110929987.5A CN202110929987A CN113627108B CN 113627108 B CN113627108 B CN 113627108B CN 202110929987 A CN202110929987 A CN 202110929987A CN 113627108 B CN113627108 B CN 113627108B
Authority
CN
China
Prior art keywords
period
algorithm
reference point
point
operating frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110929987.5A
Other languages
Chinese (zh)
Other versions
CN113627108A (en
Inventor
王美琴
吴立轩
樊燕红
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shandong University
Original Assignee
Shandong University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shandong University filed Critical Shandong University
Priority to CN202110929987.5A priority Critical patent/CN113627108B/en
Publication of CN113627108A publication Critical patent/CN113627108A/en
Application granted granted Critical
Publication of CN113627108B publication Critical patent/CN113627108B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Complex Calculations (AREA)

Abstract

The disclosure provides a maximum operating frequency automatic search method of a cryptographic algorithm in an FPGA, comprising the following steps: acquiring an initial reference point on a slot-Period curve in a cryptographic algorithm; judging the relative positions of the initial reference point and the maximum operating frequency point, and searching a new reference point; based on the initial reference point and the new reference point, searching the maximum operating frequency point backwards by utilizing multi-process parallel; outputting the maximum operating frequency; the present disclosure uses static timing analysis and unique heuristic algorithms to search for the maximum operating frequency of the cryptographic algorithm and utilizes script-driven and multi-process parallel execution, reducing search time.

Description

Automatic searching method and system for maximum running frequency of cryptographic algorithm in FPGA
Technical Field
The disclosure belongs to the technical field of cryptographic algorithm integrated circuits, and particularly relates to a method and a system for automatically searching a maximum operating frequency of a cryptographic algorithm in an FPGA.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
In the digital information age, the cryptographic algorithm is receiving more and more attention, and many companies are actively developing hardware capable of realizing the cryptographic algorithm of the mobile terminal in a lightweight way, especially combining with future application of the internet of things, and for the realization method of the cryptographic algorithm of the mobile terminal, the FPGA method is a major mainstream direction of the realization of the cryptographic algorithm of the hardware nowadays; the FPGA is a field programmable gate array, and is used as a semi-custom circuit in the ASIC field, so that the defect of custom circuit is overcome, and the defect of limited gate circuit number of the original programmable device is overcome; xilinx and Altera are two leading FPGA vendors worldwide, and different FPGA vendors all have their own EDA development tools, such as Xilinx's Vivado and Altera's quatus Prime.
In the hardware of the cryptographic algorithm, the throughput is an important parameter for measuring the performance of the digital circuit no matter which manufacturer's FPGA product; the maximum clock frequency at which the cryptographic algorithm can operate directly affects the maximum throughput of the cryptographic algorithm; in the hardware design of cryptographic algorithms, the maximum clock frequency that a given RTL code can reach can be estimated or measured at different stages of the implementation process; the main phases are synthesis, placement and routing and actual experimental testing on the circuit board.
The static timing analysis function of the FPGA tool can give the results after synthesis, layout and wiring, but the method of designing and implementing the static timing analysis of the digital circuit using the FPGA tool using the hardware description language has the following problems:
(1) The EDA tool Vivado of Xilinx does not report the maximum frequency that the corresponding code can reach, the tool only reports "pass" or "fail" to achieve this goal; the EDA tool, quartz Prime, of Altera reports the maximum frequency, but is inaccurate, and when the target frequency is changed, the Quartz returns another maximum frequency, resulting in the maximum frequency reported by the tool being inaccurate;
(2) For the problem of the maximum clock frequency supported by the hardware code, the traditional method is to try different target frequencies manually; the results obtained in this process will also vary from person to person and this is a very tedious and time consuming process.
(3) The fluctuation of the slot-period curve of the cryptographic algorithm is frequent, the difficulty of searching the maximum running frequency of the cryptographic algorithm is irregular, and the product design period of the FPGA can be increased undoubtedly; the complexity and diversity of the slice-period curve causes a great difficulty in searching the maximum operating frequency of the cryptographic algorithm, and the classical dichotomy is not only tedious and time-consuming, but also cannot usually obtain a correct result; as shown in FIG. 1, the result is a partial curve of the Sllack-Period implemented by SILC_GMU_v1.0 cryptographic algorithm on the FPGA of model 10CL016YU256C8G of the Cyclone10LP of Altera, and the correct result cannot be found by using the conventional binary search method.
Disclosure of Invention
In order to solve the problems, the present disclosure provides a method and a system for automatically searching the maximum operating frequency of a cryptographic algorithm in an FPGA, and the present disclosure provides a Fast-Find algorithm, where the Fast-Find uses static timing analysis and a unique heuristic algorithm to search the maximum operating frequency of the cryptographic algorithm, and on the implementation of the Fast-Find algorithm, script driving and multi-process parallel execution are used, so that the search time is reduced.
In order to achieve the above object, the present application is realized by the following technical scheme:
in a first aspect, the present disclosure provides a method for automatically searching for a maximum operating frequency of a cryptographic algorithm in an FPGA, including:
acquiring an initial reference point on a slot-Period curve in a cryptographic algorithm;
judging the relative positions of the initial reference point and the maximum operating frequency point, and searching a new reference point;
based on the initial reference point and the new reference point, searching the maximum operating frequency point backwards by utilizing multi-process parallel;
outputting the maximum operating frequency.
Further, the average value of Period-slot values is taken as the initial reference point on the slot-Period curve.
Further, in the searching process, the minimum operation period is used to replace the maximum operation frequency; outputting a time residual value through the static time sequence analysis function of an EDA tool of the FPGA; static time sequence analysis is carried out by driving an EDA tool through a TCL script.
Further, by utilizing the static time sequence analysis function of the EDA tool, the m process synthesizes an initial reference point and n points backwards and forwards, wherein m=2n+1, and the relative position of the initial reference point and the minimum operation period is primarily judged;
storing the point with the time residual value being more than or equal to 0 and the period being the smallest in the m time residual values as a preselected value, and adopting multiprocess backward recursion to search for the possible minimum operation period;
when the m time residual values are smaller than zero, increasing the period step length, and synthesizing p points before the initial reference point by the p processes; storing the point with the time residual value being more than or equal to 0 and the period being the smallest in the p time residual values, and adopting multiprocess backward recursion to search the possible minimum operation period;
when the p time residual values are all smaller than zero, the minimum possible running period is searched recursively backwards by adopting a plurality of processes based on the new reference point.
In a second aspect, the present disclosure further provides a maximum operating frequency automatic search system for a cryptographic algorithm in an FPGA, including a data acquisition module, a judgment module, a search module, and an output module;
the data acquisition module is configured to: acquiring an initial reference point on a slot-Period curve in a cryptographic algorithm;
the judging module is configured to: judging the relative positions of the initial reference point and the maximum operating frequency point, and searching a new reference point;
the search module is configured to: based on the initial reference point and the new reference point, searching the maximum operating frequency point backwards by utilizing multi-process parallel;
the output module is configured to: outputting the maximum operating frequency.
Further, the average value of Period-slot values is taken as the initial reference point on the slot-Period curve.
Further, in the searching process, the minimum operation period is used to replace the maximum operation frequency; outputting a time residual value through the static time sequence analysis function of an EDA tool of the FPGA; static time sequence analysis is carried out by driving an EDA tool through a TCL script.
Further, by utilizing the static time sequence analysis function of the EDA tool, the m process synthesizes an initial reference point and n points backwards and forwards, wherein m=2n+1, and the positions of the initial reference point and the minimum operation period are primarily judged;
storing the point with the time residual value being more than or equal to 0 and the period being the smallest in the m time residual values as a preselected value, and adopting multiprocess backward recursion to search for the possible minimum operation period;
when the m time residual values are smaller than zero, increasing the period step length, and synthesizing p points before the initial reference point by the p processes; storing the point with the time residual value being more than or equal to 0 and the period being the smallest in the p time residual values, and adopting multiprocess backward recursion to search the possible minimum operation period;
when the p time residual values are all smaller than zero, the minimum possible running period is searched recursively backwards by adopting a plurality of processes based on the new reference point.
Compared with the prior art, the beneficial effects of the present disclosure are:
1. according to the method and the device, the initial reference point is obtained through pre-calculation, the relative positions of the reference point and the maximum operating frequency point are judged, the maximum operating frequency point is searched backwards in parallel through multiple processes, and the accurate maximum operating frequency of the corresponding cryptographic algorithm can be searched under the precision of the designated periodic step length according to the slack value returned by the EDA tool.
2. The present disclosure uses static timing analysis and unique heuristic algorithms to search for the maximum operating frequency of the cryptographic algorithm and utilizes script-driven and multi-process parallel execution, reducing search time.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification, illustrate and explain the embodiments and together with the description serve to explain the embodiments.
FIG. 1 is a slice-period graph of example 1 of the present disclosure;
FIG. 2 is a flow chart of the main body of the Fast-Find algorithm of embodiment 1 of the present disclosure;
FIG. 3 is a flow chart of the Fast-Find algorithm presented in the present disclosure with a clock CLK clock period of 0.01ns as the precision of the cryptographic algorithm;
fig. 4 is a flowchart of the get_pmin algorithm given by the present disclosure with the clock period of the clock CLK of the cryptographic algorithm of 0.01ns as precision.
Fig. 5 is a flowchart of the multprocessbe_recu algorithm given by the present disclosure with a clock period of 0.01ns of the clock CLK of the cryptographic algorithm as precision.
The specific embodiment is as follows:
the disclosure is further described below with reference to the drawings and examples.
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
Example 1:
as shown in fig. 3, this embodiment provides a method for automatically searching the maximum operating frequency of the cryptographic algorithm in the FPGA, and in this embodiment, the Fast-Find algorithm is adopted to implement the automatic search of the maximum operating frequency of the cryptographic algorithm in the FPGA.
In the field of hardware implementation, an automatic search algorithm is urgently needed to solve some hardware parameters uniformly in the face of complex irregularity of a slice-period curve of a cryptographic algorithm, the slice-period curves of different cryptographic algorithms are also quite different, and the characteristics of different EDA software (Vivado and Quartus Prime) inside an FPGA are different; fast-Find is an automatic searching method capable of uniformly solving the maximum running frequency of the cryptographic algorithm in the FPGA, and the Fast-Find uses static time sequence analysis and a unique heuristic algorithm to automatically search the maximum running frequency of the cryptographic algorithm; the prominent advantages of Fast-Find compared to other automated search methods are two: in algorithm design, obtaining a get_pmin algorithm of a reference frequency through pre-calculation; in algorithm realization, a scheme of script driving and multi-process parallel execution is utilized; based on the two advantages, the automatic search of Fast-Find is faster and more efficient.
As shown in FIG. 1, the Fast-Find algorithm has a clear automatic search process, and the automatic search process for realizing the maximum running frequency of the cryptographic algorithm in the FPGA comprises the following steps:
acquiring an initial reference point on a slot-Period curve in a cryptographic algorithm;
judging the relative positions of the initial reference point and the maximum operating frequency point, and searching a new reference point;
based on the initial reference point and the new reference point, searching the maximum operating frequency point backwards by utilizing multi-process parallel;
outputting the maximum operating frequency.
Because of the complex volatility of the slice-period curve, fast-Find adopts a method of firstly selecting an initial reference point on the curve, then judging the relative position of the reference point and a final maximum operating frequency point, and then expanding multi-process parallel search.
In this embodiment, the design of Fast-Find is introduced from three parts, namely, the main body Fast-Find algorithm of the algorithm, the Get initial reference point get_pmin algorithm and the multiprocess backward recursion search maximum operating frequency multprocessbe_recu algorithm.
It should be noted that, in the process of calling the EDA tool to perform static timing analysis, in order to facilitate synthesis, layout and wiring, in the implementation of the cryptographic algorithm, the operation frequency of the cryptographic algorithm is adjusted by changing the clock period of the clock CLK, where the period P and the frequency F satisfy the relationship:
when the frequency reaches the maximum, the period reaches the minimum; therefore, in the present embodiment, the minimum operation period is used instead of the maximum operation frequency.
Through the foregoing discussion, a general way to find the maximum running frequency of the cryptographic algorithm in the FPGA can be summarized by continuously setting the clock period of the CLK clock of the cryptographic algorithm, and then obtaining the result after synthesis and layout and wiring through the static timing analysis function of the EDA tool, where it is mainly determined whether the slot Time parameter is greater than zero.
As shown in fig. 3, in this embodiment, with the clock period of the clock CLK of the cryptographic algorithm being 0.01ns as the precision, the flow of implementing the automatic search of the maximum running frequency of the cryptographic algorithm in the FPGA by the Fast-Find algorithm is described:
because the slot-Period curves of different cryptographic algorithms in the FPGA are complex and have different forms, in the embodiment, a pre-per cut-in point on the slot-Period curve is found through the Get-Pmin algorithm; then, by utilizing the static time sequence analysis function of the EDA tool, m processes parallelly synthesize pre_per and n points backwards and forwards, wherein m=2n+1, and the function of this step is to preliminarily judge the relative positions of the access point pre_per and the minimum operation period fin_period, wherein the first case is pre_per > =fin_period, and the other case is pre_per < fin_period; in the m slots synthesized above, if there is a slot > =0, fast-Find is considered as the first case, the point min_period_point with the minimum period of slot > =0 is stored as a preselected value in tmp_period. Txt file, and then the multprocessbe_recu algorithm is called to further Find the possible minimum running period fin_period, wherein period_ed is an array storing the period which has been synthesized; in another case, there is a case that m combined slacks are smaller than zero, fast-Find considers this as the second case, so a larger interval of 0.05 is used to Find the appropriate entry point forward, p points are combined in parallel, then it is judged whether a case that slack > =0 exists, if so, a point min_period_point with a minimum period of slack > =0 is stored as a preselected value in tmp_period. If the p slots are smaller than zero, taking pre_per+0.05×p as an access point, and calling a multprocessbe_recu algorithm, wherein the pre_per obtained by using the get_pmin algorithm and the proper p value are selected to meet the requirement of pre_per+0.05×p > fin_period.
As shown in fig. 4, a flowchart of the get_pmin algorithm is given with the clock period of the cryptographic algorithm CLK clock of 0.01ns as precision.
In this embodiment, the get_pmin algorithm is a core algorithm for obtaining a slot-Period curve entry point, and the closer the curve entry point is to the final fin_period, the better; the get_pmin algorithm is directed to this, the main idea of which is that
period ref ＝period-slack
Wherein the period value and the slice value are respectively the input parameter and the output parameter of the static time sequence analysis, and the calculation result of the period-slice is recorded as period ref Reference to a minimum run length is intended herein. By using the equation above, we can estimate the minimum running period of the cryptographic algorithm by calculating the value of period-slot, and through experimental test, the estimated minimum running period is inaccurate, on one hand, the value of period-slot estimated at one time is far from the target fin_period, and the value of period-slot estimated at one time is not worth referring; on the other hand, period obtained by two evaluations 1 -slack 1 And period 2 -slack 2 The difference is large, and a compromise of reasonable entry points cannot be obtained.
In this embodiment, the inventor finds that only the period-slot value of slot <0 has a reference value, and can understand that only the result of letting the EDA tool "go to great lengths" to synthesize has a reference value; the difference of different Period-slot values obtained by the method is greatly reduced, and in order to obtain a compromise result, the average value of the Period-slot values is taken as the final slot-Period curve entry point.
In this embodiment, the initial reference point period may be adjusted accordingly according to the FPGA product model and the integrated cryptographic algorithm used i To obtain a cut point on the slot-Period curve that is closer to the fin Period.
In this embodiment, the multprocessbe_recu algorithm is an algorithm that attempts to find the minimum run period backwards if an access point is found; before introducing the main idea of the algorithm, a hypothesis is introduced in this embodiment:
for the case of a clock CLK with a clock period precision of 0.01ns, if the slacks at consecutive t points after a period point are all less than zero, then this period value is considered to be the minimum run period of the cryptographic algorithm.
As shown in fig. 5, a flowchart of the multprocessbe_recu algorithm is given with a clock period of 0.01ns of the cryptographic algorithm CLK clock as precision.
Based on the previous assumption, finding t points backwards from the min_period_point, if all t slots are smaller than zero, ending the multprocessbe_recu algorithm, and finally obtaining the fin_period as a period value in tmp_period. If there is a slot greater than or equal to zero in the t points, the point with slot > =0 and the smallest period is written as a preselected value into the tmp_period. Txt file, and then the multprocessbe_recu algorithm is recursively invoked until the slots of t points backward in min_period_point are all less than zero.
In testing the slack of t points, we divide the t points into two groups according to the interval of 0.02, integrate in turn, and recursively call the algorithm itself once the situation that the slack > =0 is encountered, and certainly divide into two groups according to the interval of 0.02 is a compromise scheme which is compatible with most of the cryptographic algorithms and has higher searching speed.
Finally, in order to search the maximum running frequency of the cryptographic algorithm more quickly, the TCL script drives the EDA tool to perform static time sequence analysis, so that tedious and complex operation of a graphical interface is effectively reduced, a period_ed array is introduced into the algorithm to remove repetition and finally is most important in order to avoid repeated synthesis of the same period value, and a plurality of period values are synthesized in parallel by multiple processes, so that compared with a scheme of multiple synthesis by a single process, a great amount of time is saved.
Algorithm running results:
the implementation of different cryptographic algorithms on FPGA of 10CL016YU256C8G model of the Cyclone10LP of Altera is realized, and the Fast-Find algorithm is adopted to automatically search the operation result of the maximum operation frequency of the cryptographic algorithm, as shown in the following table:
in this embodiment, the runtime is the runtime on a server with a CPU of AMD EPYC 7302 16-Core Processor and a runtime memory of 256G.
Example 2:
the embodiment provides a maximum operating frequency automatic search system of a cryptographic algorithm in an FPGA, which comprises a data acquisition module, a judgment module, a search module and an output module;
the data acquisition module is configured to: acquiring an initial reference point on a slot-Period curve in a cryptographic algorithm;
the judging module is configured to: judging the relative positions of the initial reference point and the maximum operating frequency point, and searching a new reference point;
the search module is configured to: based on the initial reference point and the new reference point, searching the maximum operating frequency point backwards by utilizing multi-process parallel;
the output module is configured to: outputting the maximum operating frequency.
In this embodiment, the average value of Period-slice values is taken as the initial reference point on the slot-Period curve.
In this embodiment, the minimum operating period is used instead of the maximum operating frequency during the search; outputting a time residual value through the static time sequence analysis function of an EDA tool of the FPGA; static time sequence analysis is carried out by driving an EDA tool through a TCL script.
In this embodiment, by using the static timing analysis function of the EDA tool, the m process synthesizes an initial reference point and n points backward and forward, where m=2n+1, and initially determines the relative position of the initial reference point and the minimum operation period;
storing the point with the time residual value being more than or equal to 0 and the period being the smallest in the m time residual values as a preselected value, and adopting multiprocess backward recursion to search for the possible minimum operation period;
when the m time residual values are smaller than zero, increasing the period step length, and synthesizing p points before the initial reference point by the p processes; storing the point with the time residual value being more than or equal to 0 and the period being the smallest in the p time residual values, and adopting multiprocess backward recursion to search the possible minimum operation period;
when the p time residual values are all smaller than zero, the minimum possible running period is searched recursively backwards by adopting a plurality of processes based on the new reference point.
Example 3:
the embodiment provides an electronic device, which comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the processor is used for realizing the maximum running frequency automatic searching method of the cryptographic algorithm in the FPGA in the embodiment 1 when executing the program.
Embodiment four:
the present embodiment provides a computer readable storage medium having stored thereon a computer program which when executed by a processor implements the method for automated searching for maximum operating frequency of a cryptographic algorithm in an FPGA as described in embodiment 1.
The above description is only a preferred embodiment of the present embodiment, and is not intended to limit the present embodiment, and various modifications and variations can be made to the present embodiment by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present embodiment should be included in the protection scope of the present embodiment.

Claims (5)

  1. The automatic searching method for the maximum operating frequency of the cryptographic algorithm in the FPGA is characterized by comprising the following steps:
    acquiring an initial reference point on a slot-Period curve in a cryptographic algorithm;
    judging the relative positions of the initial reference point and the maximum operating frequency point, and searching a new reference point;
    based on the initial reference point and the new reference point, searching the maximum operating frequency point backwards by utilizing multi-process parallel, wherein the maximum operating frequency automatic search of the cryptographic algorithm in the FPGA is realized by adopting the Fast-Find algorithm, and the method is specific: because of the complex fluctuation of the slice-period curve, fast-Find adopts a method of firstly selecting an initial reference point on the curve, then judging the relative position of the initial reference point and a final maximum operating frequency point fin_period, and then expanding multi-process parallel search;
    the main body of the algorithm comprises a Fast-Find algorithm, an initial reference point get_pmin acquisition algorithm and a multi-process backward recursion search maximum operating frequency multprocessbe_recu algorithm; the multprocessbe_recu algorithm is an algorithm that attempts backwards to find the minimum run period if an access point is found; before introducing the main idea of the algorithm, a hypothesis is introduced: for the case where the clock period precision of the clock CLK is 0.01ns, if the slacks at consecutive t points after a period point are all less than zero, then this period value is considered to be the minimum running period of the cryptographic algorithm;
    the multprocessbe_recu algorithm: finding t points backwards from the min_period_point, if the t slots are smaller than zero, ending the multprocessbe_Recu algorithm, and finally obtaining the final fin_period as a period value in tmp_period.txt file; if there is a slot greater than or equal to zero in the t points, writing the point with slot > =0 and the smallest period as a preselected value into tmp_period. Txt file, and then recursively calling multprocessbe_recu algorithm until slots of t points backward of min_period_point are all less than zero;
    outputting the maximum operating frequency;
    in the searching process, the minimum operation period is used for replacing the maximum operation frequency; outputting a time residual value through the static time sequence analysis function of an EDA tool of the FPGA; driving an EDA tool to perform static time sequence analysis through a TCL script; utilizing the static time sequence analysis function of the EDA tool, the m process synthesizes an initial reference point and n points backwards and forwards, wherein m=2n+1, and primarily judging the positions of the initial reference point and the minimum operation period;
    storing the point with the time residual value being more than or equal to 0 and the period being the smallest in the m time residual values as a preselected value, and adopting multiprocess backward recursion to search for the possible minimum operation period;
    when m time residual values are smaller than zero, increasing the period step length, and integrating a new reference point and the previous p minus one point by the p process, wherein the new reference point is the point of the initial reference point for searching the set interval value forwards; storing the point with the time residual value being more than or equal to 0 and the period being the smallest in the p time residual values, and adopting multiprocess backward recursion to search the possible minimum operation period;
    when the p time residual values are all smaller than zero, the minimum possible running period is searched recursively backwards by adopting a plurality of processes based on the new reference point.
  2. 2. The method for automatically searching for the maximum operating frequency of a cryptographic algorithm in an FPGA as claimed in claim 1, wherein the method is characterized by takingThe average of the values serves as the initial reference point on the slot-Period curve.
  3. The automatic search system for the maximum operating frequency of the cryptographic algorithm in the FPGA is characterized by comprising a data acquisition module, a judgment module, a search module and an output module;
    the data acquisition module is configured to: acquiring an initial reference point on a slot-Period curve in a cryptographic algorithm;
    the judging module is configured to: judging the relative positions of the initial reference point and the maximum operating frequency point, and searching a new reference point;
    the search module is configured to: based on the initial reference point and the new reference point, searching the maximum operating frequency point backwards by utilizing multi-process parallel, wherein the maximum operating frequency automatic search of the cryptographic algorithm in the FPGA is realized by adopting the Fast-Find algorithm, and the method is specific: because of the complex fluctuation of the slice-period curve, fast-Find adopts a method of firstly selecting an initial reference point on the curve, then judging the relative position of the initial reference point and a final maximum operating frequency point fin_period, and then expanding multi-process parallel search;
    the main body of the algorithm comprises a Fast-Find algorithm, an initial reference point get_pmin acquisition algorithm and a multi-process backward recursion search maximum operating frequency multprocessbe_recu algorithm; the multprocessbe_recu algorithm is an algorithm that attempts backwards to find the minimum run period if an access point is found; before introducing the main idea of the algorithm, a hypothesis is introduced: for the case where the clock period precision of the clock CLK is 0.01ns, if the slacks at consecutive t points after a period point are all less than zero, then this period value is considered to be the minimum running period of the cryptographic algorithm;
    the multprocessbe_recu algorithm: finding t points backwards from the min_period_point, if the t slots are smaller than zero, ending the multprocessbe_Recu algorithm, and finally obtaining the final fin_period as a period value in tmp_period.txt file; if there is a slot greater than or equal to zero in the t points, writing the point with slot > =0 and the smallest period as a preselected value into tmp_period. Txt file, and then recursively calling multprocessbe_recu algorithm until slots of t points backward of min_period_point are all less than zero;
    the output module is configured to: outputting the maximum operating frequency;
    in the searching process, the minimum operation period is used for replacing the maximum operation frequency; outputting a time residual value through the static time sequence analysis function of an EDA tool of the FPGA; driving an EDA tool to perform static time sequence analysis through a TCL script; utilizing the static time sequence analysis function of the EDA tool, the m process synthesizes an initial reference point and n points backwards and forwards, wherein m=2n+1, and primarily judging the positions of the initial reference point and the minimum operation period;
    storing the point with the time residual value being more than or equal to 0 and the period being the smallest in the m time residual values as a preselected value, and adopting multiprocess backward recursion to search for the possible minimum operation period;
    when m time residual values are smaller than zero, increasing the period step length, and integrating a new reference point and the previous p minus one point by the p process, wherein the new reference point is the point of the initial reference point for searching the set interval value forwards; storing the point with the time residual value being more than or equal to 0 and the period being the smallest in the p time residual values, and adopting multiprocess backward recursion to search the possible minimum operation period;
    when the p time residual values are all smaller than zero, the minimum possible running period is searched recursively backwards by adopting a plurality of processes based on the new reference point.
  4. 4. A computer readable storage medium having stored thereon a computer program for fingerprint similarity calculation, characterized in that the program when executed by a processor implements a method for automated searching for the maximum operating frequency of cryptographic algorithms in an FPGA according to any of claims 1-2.
  5. 5. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method for automated searching for maximum operating frequency of cryptographic algorithms in an FPGA of any of claims 1-2 when the program is executed by the processor.
CN202110929987.5A 2021-08-13 2021-08-13 Automatic searching method and system for maximum running frequency of cryptographic algorithm in FPGA Active CN113627108B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110929987.5A CN113627108B (en) 2021-08-13 2021-08-13 Automatic searching method and system for maximum running frequency of cryptographic algorithm in FPGA

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110929987.5A CN113627108B (en) 2021-08-13 2021-08-13 Automatic searching method and system for maximum running frequency of cryptographic algorithm in FPGA

Publications (2)

Publication Number Publication Date
CN113627108A CN113627108A (en) 2021-11-09
CN113627108B true CN113627108B (en) 2023-08-25

Family

ID=78385315

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110929987.5A Active CN113627108B (en) 2021-08-13 2021-08-13 Automatic searching method and system for maximum running frequency of cryptographic algorithm in FPGA

Country Status (1)

Country Link
CN (1) CN113627108B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104346270A (en) * 2013-07-23 2015-02-11 京微雅格（北京）科技有限公司 Method for searching maximum frequency in which field programmable gate array (FPGA) software can operate
CN105573901A (en) * 2014-10-10 2016-05-11 京微雅格（北京）科技有限公司 Hybrid search method enabling FPGA software to reach highest frequency
CN111970112A (en) * 2020-08-10 2020-11-20 山东大学 Ether house deployment method and system based on ZYNQ heterogeneous computing platform
CN112099762A (en) * 2020-09-10 2020-12-18 上海交通大学 Co-processing system and method for quickly realizing SM2 cryptographic algorithm

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102017202002A1 (en) * 2017-02-08 2018-08-09 Siemens Aktiengesellschaft Method and computer for cryptographically protecting control communication in and / or service access to IT systems, in particular in connection with the diagnosis and configuration in an automation, control or monitoring system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104346270A (en) * 2013-07-23 2015-02-11 京微雅格（北京）科技有限公司 Method for searching maximum frequency in which field programmable gate array (FPGA) software can operate
CN105573901A (en) * 2014-10-10 2016-05-11 京微雅格（北京）科技有限公司 Hybrid search method enabling FPGA software to reach highest frequency
CN111970112A (en) * 2020-08-10 2020-11-20 山东大学 Ether house deployment method and system based on ZYNQ heterogeneous computing platform
CN112099762A (en) * 2020-09-10 2020-12-18 上海交通大学 Co-processing system and method for quickly realizing SM2 cryptographic algorithm

Also Published As

Publication number Publication date
CN113627108A (en) 2021-11-09

Similar Documents

Publication Publication Date Title
Kahng et al. Optimization of linear placements for wirelength minimization with free sites
US8434047B1 (en) Multi-level clock gating circuitry transformation
US5046012A (en) Pattern data processing method
US20110214095A1 (en) Decomposition based approach for the synthesis of threshold logic circuits
US8302041B1 (en) Implementation flow for electronic circuit designs using choice networks
US6587990B1 (en) Method and apparatus for formula area and delay minimization
US6925628B2 (en) High-level synthesis method
Georgopoulos et al. An evaluation of vivado HLS for efficient system design
US8000951B2 (en) Timing analysis method and apparatus for enhancing accuracy of timing analysis and improving work efficiency thereof
CN116822422A (en) Analysis optimization method of digital logic circuit and related equipment
CN113627108B (en) Automatic searching method and system for maximum running frequency of cryptographic algorithm in FPGA
US8776003B2 (en) System and method for employing side transition times from signoff-quality timing analysis information to reduce leakage power in an electronic circuit and an electronic design automation tool incorporating the same
US20060041852A1 (en) Targeted optimization of buffer-tree logic
Polzin et al. Extending reduction techniques for the Steiner tree problem
US6253356B1 (en) System and method for improving logic synthesis in logic circuits
US10853036B2 (en) Modulo hardware generator
JPH09321145A (en) Layout of semiconductor integrated circuit
Wong et al. A scalable and accurate rectilinear Steiner minimal tree algorithm
Xiu et al. Timing-driven placement by grid-warping
US7685587B2 (en) Automated instruction-set extension
CN109901884B (en) Method and device for high-level synthesis and code stream generation of FPGA
CN112800704B (en) Function buffer-based chip rear-end revising method and device and computer equipment
US6405352B1 (en) Method and system for analyzing wire-only changes to a microprocessor design using delta model
RU2663474C1 (en) Method of searching for similar files placed on data storage devices
JPH0981604A (en) Software/hardware cooperation design system and design method therefor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant