CN113627108A - Method and system for automatically searching maximum running frequency of cryptographic algorithm in FPGA (field programmable Gate array) - Google Patents

Method and system for automatically searching maximum running frequency of cryptographic algorithm in FPGA (field programmable Gate array) Download PDF

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CN113627108A
CN113627108A CN202110929987.5A CN202110929987A CN113627108A CN 113627108 A CN113627108 A CN 113627108A CN 202110929987 A CN202110929987 A CN 202110929987A CN 113627108 A CN113627108 A CN 113627108A
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CN113627108B (en
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王美琴
吴立轩
樊燕红
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Shandong University
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Abstract

The invention provides an automatic searching method for the maximum operating frequency of a cryptographic algorithm in an FPGA (field programmable gate array), which comprises the following steps of: acquiring an initial reference point on a Slack-Period curve in a cryptographic algorithm; judging the relative positions of the initial reference point and the maximum operating frequency point, and searching a new reference point; based on the initial reference point and the new reference point, searching a maximum operating frequency point backwards in parallel by utilizing multiple processes; outputting the maximum running frequency; the present disclosure uses static timing analysis and unique heuristic algorithms to search for the maximum operating frequency of the cryptographic algorithm and utilizes script-driven and multi-process parallel execution, reducing search time.

Description

Method and system for automatically searching maximum running frequency of cryptographic algorithm in FPGA (field programmable Gate array)
Technical Field
The disclosure belongs to the technical field of cryptographic algorithm integrated circuits, and particularly relates to a method and a system for automatically searching the maximum operating frequency of a cryptographic algorithm in an FPGA (field programmable gate array).
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
In the digital information era, the cryptographic algorithm is concerned more and more, and many companies are actively developing hardware capable of realizing the cryptographic algorithm of the mobile terminal in a light weight manner, especially the hardware capable of being combined with future application of the internet of things, and for the realization method of the cryptographic algorithm hardware of the mobile terminal, an FPGA method is a major mainstream direction for realizing the cryptographic algorithm of the hardware at present; the FPGA is a field programmable gate array, appears as a semi-custom circuit in the field of ASIC, not only solves the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited; xilinx and Altera are the two leading FPGA vendors worldwide, and different FPGA vendors all have their own EDA development tools, such as Xilinx's Vivado and Altera's Quartus Prime.
In the hardware of the cryptographic algorithm, the throughput is an important parameter for measuring the performance of a digital circuit no matter which manufacturer produces the FPGA product; the maximum clock frequency at which the cryptographic algorithm can run directly affects the maximum throughput of the cryptographic algorithm; in the hardware design of the cryptographic algorithm, the maximum clock frequency that a given RTL code can reach can be estimated or measured at different stages of the implementation process; the main stages are synthesis, placement and routing, and actual experimental testing on the circuit board.
The static timing analysis function of the FPGA tool can give results after synthesis, placement and wiring, but the method of designing using a hardware description language and implementing the static timing analysis of the digital circuit using the FPGA tool has the following problems:
(1) the EDA tool Vivado of Xilinx will not report the maximum frequency that the corresponding code can reach, and the tool will only report "pass" or "fail" to achieve this goal; the EDA tool Quartus Prime of Altera would report a maximum frequency but is not accurate and when the target frequency is changed, Quartus would return another maximum frequency, causing the maximum frequency reported by the tool to be inaccurate;
(2) for the problem of the maximum clock frequency supported by hardware codes, the traditional method is to try different target frequencies manually and continuously; the results obtained in this process can also vary from person to person and this is a very tedious and time consuming process.
(3) Fluctuation of a sleep-period curve of the cryptographic algorithm is frequent and irregular, and the difficulty of searching the maximum operating frequency of the cryptographic algorithm can increase the product design period of the FPGA undoubtedly; due to the complex diversity of the sleep-period curve, the maximum operation frequency of the cipher algorithm is searched for a big difficulty, and the classical dichotomy is not only tedious and time-consuming, but also can not obtain correct results generally; as shown in fig. 1, the slice-Period partial curve, which is the implementation of the SILC _ GMU _ v1.0 cryptographic algorithm on FPGA model 10CL016YU256C8G of clone10LP of Altera, cannot find the correct result using the conventional binary search method.
Disclosure of Invention
The invention provides a Fast-Find algorithm, which uses static time sequence analysis and a unique heuristic algorithm to search the maximum operating frequency of the cryptographic algorithm, and uses script drive and multi-process parallel execution to reduce the search time on the implementation of the Fast-Find algorithm.
In order to achieve the purpose, the invention is realized by the following technical scheme:
in a first aspect, the present disclosure provides an automatic search method for maximum operating frequency of a cryptographic algorithm in an FPGA, including:
acquiring an initial reference point on a Slack-Period curve in a cryptographic algorithm;
judging the relative positions of the initial reference point and the maximum operating frequency point, and searching a new reference point;
based on the initial reference point and the new reference point, searching a maximum operating frequency point backwards in parallel by utilizing multiple processes;
and outputting the maximum running frequency.
Further, the average of Period-Period values was taken as the initial reference point on the Period-Period curve.
Further, in the searching process, the minimum operation period is used for replacing the maximum operation frequency; outputting a time margin value through a static time sequence analysis function of an EDA tool of the FPGA; the EDA tool is driven by the TCL script for static timing analysis.
Further, by using a static time sequence analysis function of the EDA tool, the m process integrates an initial reference point and n points backward and forward, wherein m is 2n +1, and the relative position of the initial reference point and the minimum operation period is preliminarily judged;
in m time margin values, storing a point with the time margin value more than or equal to 0 and the minimum period as a preselected value, and searching the possible minimum operation period by adopting multi-process backward recursion;
when m time residual values are all smaller than zero, increasing the period step length, and integrating p points in front of the initial reference point by the p process; in the p time margin values, storing the point with the time margin value more than or equal to 0 and the minimum period, and carrying out backward recursive search on the possible minimum operation period by adopting multiple processes;
and when the p time margin values are all smaller than zero, searching the possible minimum operation period by adopting multi-process backward recursion on the basis of the new reference point.
In a second aspect, the present disclosure further provides an automatic search system for maximum operating frequency of a cryptographic algorithm in an FPGA, comprising a data acquisition module, a judgment module, a search module and an output module;
the data acquisition module configured to: acquiring an initial reference point on a Slack-Period curve in a cryptographic algorithm;
the determination module configured to: judging the relative positions of the initial reference point and the maximum operating frequency point, and searching a new reference point;
the search module configured to: based on the initial reference point and the new reference point, searching a maximum operating frequency point backwards in parallel by utilizing multiple processes;
the output module configured to: and outputting the maximum running frequency.
Further, the average of Period-Period values was taken as the initial reference point on the Period-Period curve.
Further, in the searching process, the minimum operation period is used for replacing the maximum operation frequency; outputting a time margin value through a static time sequence analysis function of an EDA tool of the FPGA; the EDA tool is driven by the TCL script for static timing analysis.
Further, by using a static time sequence analysis function of the EDA tool, the m process integrates an initial reference point and n points backward and forward, wherein m is 2n +1, and the positions of the initial reference point and the minimum operation period are preliminarily judged;
in m time margin values, storing a point with the time margin value more than or equal to 0 and the minimum period as a preselected value, and searching the possible minimum operation period by adopting multi-process backward recursion;
when m time residual values are all smaller than zero, increasing the period step length, and integrating p points in front of the initial reference point by the p process; in the p time margin values, storing the point with the time margin value more than or equal to 0 and the minimum period, and carrying out backward recursive search on the possible minimum operation period by adopting multiple processes;
and when the p time margin values are all smaller than zero, searching the possible minimum operation period by adopting multi-process backward recursion on the basis of the new reference point.
Compared with the prior art, the beneficial effect of this disclosure is:
1. the method comprises the steps of obtaining an initial reference point through pre-calculation, judging the relative position of the reference point and the maximum operating frequency point, searching the maximum operating frequency point backwards in a multi-process parallel mode to search the maximum operating frequency, and searching the accurate maximum operating frequency of a corresponding cryptographic algorithm under the specified cycle step precision according to the slack value returned by an EDA tool.
2. The present disclosure uses static timing analysis and unique heuristic algorithms to search for the maximum operating frequency of the cryptographic algorithm and utilizes script-driven and multi-process parallel execution, reducing search time.
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The accompanying drawings, which form a part hereof, are included to provide a further understanding of the present embodiments, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present embodiments and together with the description serve to explain the present embodiments without unduly limiting the present embodiments.
FIG. 1 is a plot of slack-period for example 1 of the present disclosure;
FIG. 2 is a main flow chart of Fast-Find algorithm in embodiment 1 of the present disclosure;
FIG. 3 is a flow chart of the Fast-Find algorithm of the present disclosure with the clock period of CLK of the cryptographic algorithm 0.01ns as the precision;
FIG. 4 is a flowchart of the Get _ Pmin algorithm with the accuracy of 0.01ns of the clock CLK clock period of the cryptographic algorithm according to the present disclosure.
FIG. 5 is a flow chart of the Multprocesbe _ Recu algorithm with the clock period of CLK of the cryptographic algorithm 0.01ns as the precision according to the present disclosure.
The specific implementation mode is as follows:
the present disclosure is further described with reference to the following drawings and examples.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
Example 1:
as shown in fig. 3, in this embodiment, an automatic maximum operating frequency searching method for a cryptographic algorithm in an FPGA is provided, and in this embodiment, a Fast-Find algorithm is used to implement automatic maximum operating frequency searching for the cryptographic algorithm in the FPGA.
In the field of hardware implementation, in the face of the complex irregularity of the slice-period curves of the cryptographic algorithms, the distinct slice-period curves of different cryptographic algorithms, the differences of the characteristics of different EDA software (Vivado and Quartus Prime) in the FPGA, and the like, an automatic search algorithm is urgently needed to uniformly solve some hardware parameters; Fast-Find is an automatic searching method which can uniformly solve the maximum operating frequency of the cryptographic algorithm in the FPGA, and Fast-Find uses static time sequence analysis and a unique heuristic algorithm to automatically search the maximum operating frequency of the cryptographic algorithm; compared with other automatic search methods, Fast-Find has two outstanding advantages: in the aspect of algorithm design, a Get _ Pmin algorithm of a reference frequency is obtained through pre-calculation; in the aspect of algorithm implementation, a scheme of script driving and multi-process parallel execution is utilized; based on the two advantages, the automatic search of Fast-Find is faster and more efficient.
As shown in FIG. 1, the Fast-Find algorithm has a clear automatic search process, and the process for realizing the automatic search of the maximum operating frequency of the cryptographic algorithm in the FPGA comprises the following steps:
acquiring an initial reference point on a Slack-Period curve in a cryptographic algorithm;
judging the relative positions of the initial reference point and the maximum operating frequency point, and searching a new reference point;
based on the initial reference point and the new reference point, searching a maximum operating frequency point backwards in parallel by utilizing multiple processes;
and outputting the maximum running frequency.
Due to the complex wave mobility of the sleep-period curve, Fast-Find adopts a method of firstly selecting an initial reference point on the curve, then judging the relative position of the reference point and a final maximum operating frequency point, and then developing multi-process parallel search.
In the embodiment, the design of Fast-Find is introduced from three parts, namely a main body Fast-Find algorithm of the algorithm, an initial reference point Get _ Pmin algorithm obtained and a multiprocess backward recursive search maximum operating frequency multprocesbe _ Recu algorithm.
It should be noted that, in the process of calling the EDA tool to perform the static timing analysis, in order to facilitate synthesis, layout and routing, in the implementation of the cryptographic algorithm, the operating frequency of the cryptographic algorithm is adjusted by changing the clock period of the clock CLK, where the period P and the frequency F satisfy the relationship:
Figure BDA0003210987090000071
when the frequency reaches the maximum, the period reaches the minimum; therefore, in the present embodiment, the minimum operation period is used instead of the maximum operation frequency.
Through the foregoing discussion, it can be concluded that a general way of finding the maximum operating frequency of the cryptographic algorithm in the FPGA is to continuously set the clock period of the CLK clock of the cryptographic algorithm, and then obtain the result after synthesis and layout by the static timing analysis function of the EDA tool, where it is mainly determined whether the Slack Time parameter is greater than zero.
As shown in fig. 3, in this embodiment, a flow of the Fast-Find algorithm for realizing the automatic search of the maximum operating frequency of the cryptographic algorithm in the FPGA is introduced with a clock cycle of CLK of the cryptographic algorithm of 0.01ns as precision:
because the slice-Period curves of different cryptographic algorithms in the FPGA are complex and have different forms, in this embodiment, a cut-in point pre _ per on the slice-Period curve is found through the Get _ Pmin algorithm; then, by using a static timing analysis function of the EDA tool, m processes parallelly integrate pre _ per and n points backwards and forwards, wherein m is 2n +1, the function of the step is to preliminarily judge the relative position of a cut-in point pre _ per and a minimum operation period fin _ period, the first case is pre _ per > fin _ period, and the other case is pre _ per < fin _ period; if the slice > is 0 in the m integrated slices, Fast-Find is considered as the first case, the slice > is 0 and the point min _ period _ point with the minimum period is stored as a preselected value in a tmp _ period. In another case, of course, m integrated slots are smaller than zero, Fast-Find considers this as the second case, and then a suitable entry point is found forward at a larger interval of 0.05, where p points are integrated in parallel, then it is determined whether there is a slot > -0 case, if so, the slot > -0 and the point min _ period _ point with the minimum period are stored as a preselected value in a tmp _ period _ txt file, and then a multprocesbe _ Recu algorithm is called to further Find the possible minimum operating period finjperiod. If all of these p slacks are less than zero, the multprocesbe _ Recu algorithm is called with pre _ per +0.05 p as the cut-in point, because pre _ per obtained using Get _ Pmin algorithm and selecting the appropriate p value satisfy pre _ per +0.05 p > fin _ period.
As shown in FIG. 4, a flowchart of the Get _ Pmin algorithm is given with the clock period of the clock CLK of the cipher algorithm 0.01ns as the precision.
In this embodiment, the Get _ Pmin algorithm is a core algorithm for obtaining a slit-Period curve entry point, and the closer the curve entry point is to the final fin _ Period, the better; the Get _ Pmin algorithm is addressed, and its main idea is
periodref＝period-slack
Wherein period value and slack value are input parameter and output parameter of static time sequence analysis, and calculation result of period-slack is recorded as periodrefHere, the reference value of the minimum operation period is meant. By using the above equation, we can estimate the minimum running period of the cryptographic algorithm by calculating the period-slope value, and through experimental tests, the estimated minimum running period is inaccurate, on one hand, the period-slope value estimated once is far away from the target fin _ period and has no reference value; on the other hand, period obtained by two evaluations1-slack1And period2-slack2The difference is large, and a compromise reasonable entry point cannot be obtained.
In this example, the inventors found that only period-slope values of slope <0 had a reference value, which can be understood as only the result of "go to full" integration of EDA tools; the difference of different Period-slope values obtained by the method is greatly reduced, and in order to obtain a compromise result, the average value of the Period-slope values is taken as the cut-in point of a final slope-Period curve.
In this embodiment, the initial reference point period can be adjusted according to the model of the FPGA product and the comprehensive cryptographic algorithmiTo obtain a cut-in point on the slak-Period curve closer to the fin _ Period.
In the embodiment, the multprocesbe _ Recu algorithm is an algorithm which tries to find the minimum running period backwards when finding the entry point; before introducing the main idea of the algorithm, an assumption is introduced in this embodiment:
for the case that the clock period precision of the clock CLK is 0.01ns, if the slack at t consecutive points after a period point is less than zero, the period value is considered to be the minimum running period of the cryptographic algorithm.
As shown in fig. 5, a flow chart of the multprocesbe _ Recu algorithm is given with a clock period of 0.01ns of the clock of the cryptographic algorithm CLK as the precision.
Based on the previous assumption, finding t points backwards from min _ period _ point, if the t slacks are all smaller than zero, ending the multprocesbe _ Recu algorithm, and finally finjperiod being the period value in the tmp _ period. If the slack is larger than or equal to zero in the t points, writing the slack > 0 and the point with the minimum period as a preselected value into a tmp _ period.
In the slack of the test t points, the t points are divided into two groups according to the interval of 0.02, the two groups are sequentially integrated, and the algorithm itself is recursively called once the slack > is 0, and the division into two groups at the interval of 0.02 is a compromise scheme which is compatible with most cryptographic algorithms and has a faster search speed.
Finally, in the aspect of realizing the Fast-Find algorithm, in order to search the maximum running frequency of the cryptographic algorithm more quickly, the TCL script is used for driving the EDA tool to perform static time sequence analysis, so that the tedious and complex operation of a graphical interface is effectively reduced, in order to avoid repeated integration of the same period value, a period _ ed array is introduced into the algorithm to perform deduplication, and finally, the most important is also, multiple processes integrate multiple period values in parallel, and compared with a scheme of integrating multiple times by using a single process, a large amount of time is saved.
And (3) algorithm operation results:
the implementation of different cryptographic algorithms on FPGA of 10CL016YU256C8G model of clone10LP of Altera, the operation result of the maximum operation frequency of the cryptographic algorithm is automatically searched by adopting Fast-Find algorithm, as shown in the following table:
Figure BDA0003210987090000111
in this embodiment, the runtime is the runtime on a server with CPU AMD EPYC 730216-Core Processor and running memory 256G.
Example 2:
the embodiment provides an automatic searching system for the maximum operating frequency of a cryptographic algorithm in an FPGA (field programmable gate array), which comprises a data acquisition module, a judgment module, a searching module and an output module;
the data acquisition module configured to: acquiring an initial reference point on a Slack-Period curve in a cryptographic algorithm;
the determination module configured to: judging the relative positions of the initial reference point and the maximum operating frequency point, and searching a new reference point;
the search module configured to: based on the initial reference point and the new reference point, searching a maximum operating frequency point backwards in parallel by utilizing multiple processes;
the output module configured to: and outputting the maximum running frequency.
In this example, the average of Period-Period values was taken as the initial reference point on the Period-Period curve.
In this embodiment, in the search process, the minimum operation period is used instead of the maximum operation frequency; outputting a time margin value through a static time sequence analysis function of an EDA tool of the FPGA; the EDA tool is driven by the TCL script for static timing analysis.
In this embodiment, using the static timing analysis function of the EDA tool, the m process integrates an initial reference point and n points backward and forward, where m is 2n +1, and preliminarily determines the relative position of the initial reference point and the minimum operation period;
in m time margin values, storing a point with the time margin value more than or equal to 0 and the minimum period as a preselected value, and searching the possible minimum operation period by adopting multi-process backward recursion;
when m time residual values are all smaller than zero, increasing the period step length, and integrating p points in front of the initial reference point by the p process; in the p time margin values, storing the point with the time margin value more than or equal to 0 and the minimum period, and carrying out backward recursive search on the possible minimum operation period by adopting multiple processes;
and when the p time margin values are all smaller than zero, searching the possible minimum operation period by adopting multi-process backward recursion on the basis of the new reference point.
Example 3:
the embodiment provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and capable of running on the processor, and when the processor executes the program, the method for automatically searching the maximum running frequency of the cryptographic algorithm in the FPGA according to embodiment 1 is implemented.
Example four:
the embodiment provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the method for automatically searching the maximum operating frequency of the cryptographic algorithm in the FPGA according to embodiment 1 is implemented.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and those skilled in the art can make various modifications and variations. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present embodiment should be included in the protection scope of the present embodiment.

Claims (10)

  1. The method for automatically searching the maximum operating frequency of the cryptographic algorithm in the FPGA is characterized by comprising the following steps:
    acquiring an initial reference point on a Slack-Period curve in a cryptographic algorithm;
    judging the relative positions of the initial reference point and the maximum operating frequency point, and searching a new reference point;
    based on the initial reference point and the new reference point, searching a maximum operating frequency point backwards in parallel by utilizing multiple processes;
    and outputting the maximum running frequency.
  2. 2. The method for automatically searching the maximum operating frequency of the cryptographic algorithm in the FPGA according to claim 1, wherein an average value of Period-Period values is taken as an initial reference point on a Period-Period curve.
  3. 3. The method for automatically searching the maximum operating frequency of a cryptographic algorithm in an FPGA of claim 1, wherein a minimum operating period is used instead of the maximum operating frequency during the searching process; outputting a time margin value through a static time sequence analysis function of an EDA tool of the FPGA; the EDA tool is driven by the TCL script for static timing analysis.
  4. 4. The method for automatically searching the maximum operating frequency of the cryptographic algorithm in the FPGA of claim 3, wherein the static timing analysis function of the EDA tool is utilized, the m process integrates an initial reference point and n points backward and forward, wherein m is 2n +1, and the positions of the initial reference point and the minimum operating period are preliminarily determined;
    in m time margin values, storing a point with the time margin value more than or equal to 0 and the minimum period as a preselected value, and searching the possible minimum operation period by adopting multi-process backward recursion;
    when m time residual values are all smaller than zero, increasing the period step length, and integrating p points in front of the initial reference point by the p process; in the p time margin values, storing the point with the time margin value more than or equal to 0 and the minimum period, and carrying out backward recursive search on the possible minimum operation period by adopting multiple processes;
    and when the p time margin values are all smaller than zero, searching the possible minimum operation period by adopting multi-process backward recursion on the basis of the new reference point.
  5. The automatic searching system for the maximum running frequency of the cryptographic algorithm in the FPGA is characterized by comprising a data acquisition module, a judging module, a searching module and an output module;
    the data acquisition module configured to: acquiring an initial reference point on a Slack-Period curve in a cryptographic algorithm;
    the determination module configured to: judging the relative positions of the initial reference point and the maximum operating frequency point, and searching a new reference point;
    the search module configured to: based on the initial reference point and the new reference point, searching a maximum operating frequency point backwards in parallel by utilizing multiple processes;
    the output module configured to: and outputting the maximum running frequency.
  6. 6. The system of claim 5, wherein the average value of Period-Period values is used as an initial reference point on the Period-Period curve.
  7. 7. The system of claim 5, wherein the minimum run period is used in place of the maximum run frequency during the search process; outputting a time margin value through a static time sequence analysis function of an EDA tool of the FPGA; the EDA tool is driven by the TCL script for static timing analysis.
  8. 8. The automatic search system of maximum operating frequency of cryptographic algorithm in FPGA of claim 6, characterized in that, using static timing analysis function of EDA tool, m process synthesizes initial reference point and backward n points, wherein m is 2n +1, and preliminarily judges position of initial reference point and minimum operating period;
    in m time margin values, storing a point with the time margin value more than or equal to 0 and the minimum period as a preselected value, and searching the possible minimum operation period by adopting multi-process backward recursion;
    when m time residual values are all smaller than zero, increasing the period step length, and integrating p points in front of the initial reference point by the p process; in the p time margin values, storing the point with the time margin value more than or equal to 0 and the minimum period, and carrying out backward recursive search on the possible minimum operation period by adopting multiple processes;
    and when the p time margin values are all smaller than zero, searching the possible minimum operation period by adopting multi-process backward recursion on the basis of the new reference point.
  9. 9. A computer-readable storage medium, on which a computer program is stored for fingerprint similarity calculation, wherein the program, when executed by a processor, implements a maximum operating frequency automated search method for cryptographic algorithms in an FPGA according to any one of claims 1 to 4.
  10. 10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor when executing the program implements a maximum operating frequency automated search method for cryptographic algorithms in an FPGA according to any one of claims 1-4.
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