CN113589642B - Method, device, computer equipment and medium for predicting open circuit defect of integrated circuit - Google Patents
Method, device, computer equipment and medium for predicting open circuit defect of integrated circuit Download PDFInfo
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- 230000007547 defect Effects 0.000 title claims abstract description 112
- 238000000034 method Methods 0.000 title claims abstract description 72
- 238000004088 simulation Methods 0.000 claims abstract description 126
- 238000005530 etching Methods 0.000 claims abstract description 64
- 230000008569 process Effects 0.000 claims abstract description 36
- 239000012634 fragment Substances 0.000 claims abstract description 21
- 230000000877 morphologic effect Effects 0.000 claims abstract description 17
- 238000013461 design Methods 0.000 claims abstract description 16
- 230000000694 effects Effects 0.000 claims abstract description 16
- 230000003287 optical effect Effects 0.000 claims abstract description 16
- 239000000126 substance Substances 0.000 claims abstract description 15
- 238000001259 photo etching Methods 0.000 claims abstract description 9
- 238000012937 correction Methods 0.000 claims description 26
- 239000011159 matrix material Substances 0.000 claims description 21
- 230000011218 segmentation Effects 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 230000008859 change Effects 0.000 claims description 7
- 238000003860 storage Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 238000004422 calculation algorithm Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
- G03F1/44—Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/72—Repair or correction of mask defects
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/80—Etching
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
- G03F7/70441—Optical proximity correction [OPC]
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70608—Monitoring the unpatterned workpiece, e.g. measuring thickness, reflectivity or effects of immersion liquid on resist
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/7065—Defects, e.g. optical inspection of patterned layer for defects
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Abstract
The present invention is capable of providing a method, apparatus, computer device and medium for integrated circuit open defect prediction, which may include the following steps. And correcting the optical proximity effect of the photoetching pattern contained in the integrated circuit design layout to obtain a first simulation pattern. And correcting the first simulation pattern based on the process of etching the first simulation pattern to obtain a second simulation pattern. And correcting the second simulation pattern based on the process of chemical mechanical planarization treatment of the second simulation pattern to obtain a third simulation pattern. And determining a plurality of graph fragments by sectioning the target line graph contained in the third simulation graph. Predicting whether the target line graph has open defects according to the morphological characteristics of all graph segments. The invention combines the fluctuation factors of various processes such as optical proximity effect, etching, chemical mechanical planarization and the like, realizes the method for predicting the open-circuit defect of the integrated circuit with process fluctuation resistance, and improves the yield and the reliability of the integrated circuit.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and more particularly, to a method, an apparatus, a computer device, and a medium for predicting an open defect of an integrated circuit.
Background
The development speed of moore's law gradually slows down as the process nodes of integrated circuits evolve, and the manufacturing difficulty and cost of integrated circuits continue to rise. Along with the improvement of the complexity of chip manufacturing, simulation verification before chip throwing is particularly important, and rework in subsequent chips is avoided to the greatest extent possible. Conventional pre-die inspection is typically DRC (Design Rule Check, design rule inspection), but this approach still does not guarantee adequate yield, and improvement or optimization is highly desirable.
Disclosure of Invention
In order to solve the problem that the conventional inspection scheme before the film-forming cannot fully ensure the yield, the invention can provide the method, the device, the computer equipment and the medium for predicting the open circuit defects of the integrated circuit, so that the open circuit defects can be predicted before the film-forming, the yield of the integrated circuit is improved, and the reliability of the integrated circuit is enhanced.
To achieve the above technical objective, the present invention discloses a method for predicting open defects of an integrated circuit, which may include, but is not limited to, one or more of the following steps.
And correcting the optical proximity effect of the photoetching pattern contained in the integrated circuit design layout to obtain a first simulation pattern.
And correcting the first simulation pattern based on the process of etching the first simulation pattern to obtain a second simulation pattern.
And correcting the second simulation pattern based on the process of chemical mechanical planarization treatment of the second simulation pattern so as to obtain a third simulation pattern.
And determining a plurality of graph fragments by sectioning the target line graph contained in the third simulation graph.
Predicting whether the target line graph has open defects according to the morphological characteristics of all graph segments.
Further, the topographical features comprise a minimum width.
The predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all graph segments comprises:
and determining that the target line pattern has an open circuit defect according to the fact that the minimum width of any pattern segment is smaller than the open circuit defect threshold value.
Or determining that the target line pattern has no open circuit defect according to the fact that the minimum width of all pattern fragments is larger than or equal to the open circuit defect threshold value.
Further, the determining that the target line pattern has an open defect according to the minimum width of any pattern segment being less than the open defect threshold value includes:
and determining the open circuit probability of the graph segment according to the fact that the minimum width of the graph segment is smaller than the open circuit defect threshold value.
And determining the open circuit probability of the target line graph according to the open circuit probability of the graph segment.
Further, the modifying the first simulation pattern based on the process of etching the first simulation pattern includes:
and forming an etching deviation matrix set based on a simulation process of etching the first simulation pattern, wherein the etching deviation matrix set is used for representing the profile change of the first simulation pattern generated by etching.
And correcting the first simulation graph through the etching deviation matrix group.
Further, the determining the plurality of graphics segments by segmenting the target line graph included in the third simulation graph includes:
and traversing all target line patterns contained in the third simulation pattern.
And respectively removing the tail ends of the target line patterns.
And carrying out segmentation division on the target line graph with the tail end removed so as to obtain a plurality of graph segments.
Further, the topographical features include edge roughness.
The predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all graph segments comprises:
predicting whether the target line pattern has an open circuit defect according to the edge roughness of both sides of all pattern fragments.
Further, the target line pattern is a metal line pattern.
To achieve the above technical objective, the present invention discloses an apparatus for predicting an open circuit defect of an integrated circuit, which includes, but is not limited to, a graphic correction module, a first correction module, a second correction module, a graphic segmentation module, and a defect prediction module.
And the pattern correction module is used for correcting the optical proximity effect of the photoetching pattern contained in the integrated circuit design layout so as to obtain a first simulation pattern.
And the first correction module is used for correcting the first simulation pattern based on the process of etching the first simulation pattern so as to obtain a second simulation pattern.
And the second correction module is used for correcting the second simulation pattern based on the process of chemical mechanical planarization treatment of the second simulation pattern so as to obtain a third simulation pattern.
And the graph segmentation module is used for determining a plurality of graph segments in a mode of segmenting and dividing the target line graph contained in the third simulation graph.
And the defect prediction module is used for predicting whether the target line pattern has an open circuit defect according to the morphological characteristics of all the pattern fragments.
To achieve the above object, the present invention also provides a computer device, including a memory and a processor, where the memory stores computer readable instructions that, when executed by the processor, cause the processor to perform the steps of the method for predicting open defects of an integrated circuit according to any embodiment of the present invention.
To achieve the above object, the present invention may further provide a storage medium storing computer readable instructions that, when executed by one or more processors, cause the one or more processors to perform the steps of the method for predicting open defects of an integrated circuit in any of the embodiments of the present invention.
The beneficial effects of the invention are as follows:
the open circuit defect prediction technical scheme combines the fluctuation factors of various processes such as optical proximity effect, etching, chemical mechanical planarization and the like, so that the invention can provide the method for predicting the open circuit defect of the integrated circuit with process fluctuation resistance, and the reliability of the integrated circuit is obviously improved.
The method can better predict the open circuit defect of the metal wire, so as to pre-treat the open circuit defect problem by adjusting the design layout and other modes before the chip is put into operation, greatly reduce the high cost caused by defect reworking in the chip flowing process, improve the yield of the integrated circuit and have wide application range.
Drawings
FIG. 1 illustrates a flow diagram of a method of integrated circuit open defect prediction in one or more embodiments of the invention.
FIG. 2 is a schematic diagram showing a graph profile change state after two corrections in one or more embodiments of the present invention.
FIG. 3 illustrates a schematic diagram of segment partitioning of a target line graph in one or more embodiments of the invention.
FIG. 4 illustrates a schematic composition of an apparatus for integrated circuit open defect prediction in one or more embodiments of the invention.
FIG. 5 is a schematic diagram showing the internal constitution of a computer device in one or more embodiments of the invention.
Detailed Description
The method, the device, the computer equipment and the medium for predicting the open circuit defect of the integrated circuit provided by the invention are explained and illustrated in detail below with reference to the attached drawings.
As shown in FIG. 1, one or more embodiments of the present invention may specifically provide a method of open defect prediction for an integrated circuit, including, but not limited to, one or more of the following steps.
In step 100, the present invention first performs optical proximity correction (Optical Proximity Correction, OPC, or optical proximity correction) on a lithographic pattern included in an integrated circuit design layout to obtain a first dummy pattern.
It should be understood that the photolithography pattern in the embodiment of the present invention is a simulated pattern after exposure in the circuit design layout, and is consistent with the pattern formed after actual exposure. The invention can enter optical proximity correction by performing photoetching target reset (retarget) on the integrated circuit design layout.
Step 200, the present invention corrects the first simulation pattern based on the process of etching (etching) the first simulation pattern, that is, superimposes the pattern deviation caused by etching on the basis of the first simulation pattern, so as to obtain the second simulation pattern.
As shown in fig. 2, in the embodiment of the present invention, after the size of the first simulation pattern corrected based on etching is reduced, a second simulation pattern is formed, where the profile of the etched pattern of the second simulation pattern is consistent with the profile of the pattern formed after etching the real wafer or the related material layer formed on the wafer.
Optionally, the modifying the first simulation pattern based on the process of etching the first simulation pattern according to the embodiment of the present invention includes: forming an etching deviation matrix group based on a simulation process of etching the first simulation pattern, wherein the etching deviation matrix group of the embodiment is used for representing the profile change of the first simulation pattern generated by etching; and correcting the first simulation graph through the etching deviation matrix group, and particularly superposing the etching deviation matrix on the basis of the first simulation graph data. Preferably, the etching bias matrix set rule-based method is obtained by means of a look-up table (look-up table), as shown in the following.
| F(W,S) | 100 | 110 | 120 | 130 |
| 40 | 18 | 17 | 16 | 16 |
| 50 | 18 | 17 | 16 | 15 |
| 60 | 19 | 18 | 17 | 17 |
| 70 | 19 | 18 | 17 | 17 |
| 80 | …… | …… | …… | …… |
| 90 | …… | …… | …… | …… |
Wherein, etching deviation bias=f (W, S), F represents a combination function, W represents Line Width (Line Width), S represents Space (pattern pitch); taking w=60 and s=110 as an example, the etching Bias bias=f (W, S) =18.
In general, the two effects, aperture effect and microloading effect, are referred to as etch proximity effect. In the etching process of the silicon substrate, the side wall and the bottom of the pattern are etched by the reaction gas at the same time, so that the etching proximity effect often causes deviation of the etched pattern size and the etching depth at the same time. Based on the strong correlation between the two, the correction of the pattern size generally compensates the deviation in etching depth, so that the layout correction of the etching proximity effect only aims at the etching pattern size and does not consider the factor of etching depth. Therefore, the etching deviation based on the method can be a unified value, and the mode of taking the unified value as the etching deviation is adopted as the parallel scheme of the etching deviation matrix set, so that the running speed of the algorithm on a computer for realizing the method can be further improved.
Step 300, correcting the second simulation pattern based on the process of chemical mechanical planarization (chemical mechanical planarization, CMP) to obtain a third simulation pattern, wherein the second simulation pattern is modified by superimposing the pattern deviation caused by the chemical mechanical planarization of the present invention.
As shown in fig. 2, the second simulation pattern after being corrected based on the chemical mechanical planarization of the present invention is reduced in size to form a third simulation pattern, and the pattern profile of the third simulation pattern is consistent with the pattern profile formed after the material layer on the wafer is subjected to chemical mechanical planarization.
Step 400, determining a plurality of graphic segments (segments) by means of segment division of the target line graph contained in the third simulation graph. The target line pattern in the embodiment of the present invention may include, for example, but is not limited to, a metal line pattern.
Optionally, in the embodiment of the present invention, a length of one graphics segment is less than or equal to 1 μm, so as to ensure that a main optical influence range is covered. In addition, the lengths of the plurality of graphic segments may be the same or different in embodiments of the present invention.
As shown in fig. 3, determining the plurality of graphics segments by segmenting the target line graphic included in the third simulation graphic according to the present embodiment may include: traversing all target Line patterns contained in a third simulation pattern, and respectively removing tail ends (Line End) of all target Line patterns; and then, carrying out segmentation division on the target line graph with the tail end removed so as to obtain a plurality of graph segments.
The invention can help to improve the accuracy of the subsequent measurement of the width and/or roughness of the target line pattern by removing the tail end part, and can also improve the running speed of the algorithm in the computer.
Step 500, predicting whether the target line pattern has an open defect according to the morphological characteristics of all pattern fragments.
Optionally, the topographical features in embodiments of the present invention include a pattern segment minimum width S min I.e. the minimum distance between the two sides of the graphic fragment. Predicting whether the target line pattern has an open defect according to the morphological features of all the pattern segments comprises: according to the minimum width of any graph segment being smaller than the open defect threshold d open The method comprises the steps of indicating that an open circuit defect exists in a graph segment, and determining that the open circuit defect exists in a target line graph; or according to the minimum width of all the pattern segments being greater than or equal to the open defect threshold d open Indicating that the graph segment has no open circuit defect, and determining that the target line graph has no open circuit defectAnd (5) sinking.
Optionally, determining that the target line pattern has the open defect according to the minimum width of any pattern segment being smaller than the open defect threshold value includes: determining an open probability of the graphic segment based on the minimum width of the graphic segment being less than the open defect threshold, e.g., by a functional relationship between the minimum width of the graphic segment and the open probability; according to the open circuit probability of the graph segments, the open circuit probability of the target line graph where the graph segments are located is determined, and the embodiment takes the maximum open circuit probability of all the graph segments in the target line segment graph as the open circuit probability of the current target line graph. For the metal line pattern, the invention can determine the open circuit probability of the metal line.
Optionally, the topographical features in embodiments of the present invention include edge roughness (LER, line Edge Roughness), which may include roughness on both sides of the patterned fragment: first roughness sigma LER1 And a second roughness sigma LER2 . Predicting whether the target line graph has an open defect according to the morphological characteristics of all graph segments comprises: predicting whether the target line pattern has an open defect according to the edge roughness of both sides of all the pattern segments. In some embodiments of the invention, the open circuit probability can be calculated by a mathematical distribution mode based on the edge roughness and the minimum width of two sides, for example, the open circuit probability is determined by a normal distribution analysis solution mode, and the method is suitable for predicting the open circuit defects of metal wires of a large-scale layout.
Optionally, some embodiments of the present invention can reduce the open probability P of the target line pattern failure And set early warning probability P open Comparison. If the open circuit probability P failure Is smaller than the set early warning probability P open The layout is not subjected to open circuit defect occurrence with high probability, and the layout can be not modified or optimized under the general technological requirements; if the open circuit probability P failure Greater than or equal to the set early warning probability P open The layout is described as having a high probability of open circuit, and the layout can be modified by widening the lines and the like, and the invention can be re-executed for a new design layout. Can be used for setting early warning probabilityThe invention is set reasonably on the basis of the invention, and the invention is not limited by the invention.
It should be understood that, based on the method for predicting open circuit defects of an integrated circuit provided by the present invention, the technical concept of the present invention may also be used to predict other defects or faults that may occur in an integrated circuit such as a bridging defect.
As shown in fig. 4, the present invention is also capable of providing an apparatus for predicting an open defect of an integrated circuit based on the same inventive concept as the method for predicting an open defect of an integrated circuit of the present invention.
The device for predicting the defect in the embodiment of the invention can include, but is not limited to, a graphic correction module, a first correction module, a second correction module, a graphic segmentation module and a defect prediction module, and is specifically described below.
The pattern correction module can be used for correcting the optical proximity effect of the photoetching pattern contained in the integrated circuit design layout so as to obtain and output a first simulation pattern.
The first correction module may be configured to correct the first simulation pattern based on a process of etching the first simulation pattern to obtain the second simulation pattern.
Optionally, the first correction module may be configured to form an etching deviation matrix set based on a simulation process of etching the first simulation pattern, and to correct the first simulation pattern through the etching deviation matrix set; wherein the etching deviation matrix set is used for representing the outline change of the first simulation pattern generated by etching.
The second correction module can be used for correcting the second simulation pattern based on the process of chemical mechanical planarization treatment of the second simulation pattern so as to obtain a third simulation pattern.
The graphics segmentation module may be configured to determine a plurality of graphics fragments by segmenting a target line graphic contained in the third simulation graphic. Specifically, the graph segmentation module is used for traversing all target line graphs contained in the third simulation graph, removing tail ends of all target line graphs respectively, and segmenting the target line graphs with the tail ends removed to obtain a plurality of graph segments. The target line pattern in one or more embodiments of the present invention is a metal line pattern.
The defect prediction module is used for predicting whether the target line pattern has an open circuit defect according to the morphological characteristics of all the pattern fragments.
Optionally, topographical features in the present invention include, but are not limited to, minimum widths. The defect prediction module in this embodiment may be configured to determine that the target line pattern has an open defect according to the minimum width of any pattern segment being less than the open defect threshold; or the defect prediction module is used for determining that the target line pattern has no open defect according to the fact that the minimum width of all pattern fragments is larger than or equal to the open defect threshold value. Preferably, the defect prediction module is operable to determine the open probability of a graphic segment based on the minimum width of the graphic segment being less than the open defect threshold, and to determine the open probability of the target line pattern based on the open probability of the graphic segment.
Optionally, topographical features in the present invention include, but are not limited to, edge roughness. The defect prediction module in this embodiment may be configured to predict whether the target line pattern has an open defect according to edge roughness of both sides of all the pattern segments.
As shown in fig. 5, one or more embodiments of the present invention can provide a computer device including a memory and a processor, the memory having stored therein computer readable instructions that, when executed by the processor, cause the processor to perform the steps of the method of open defect prediction for an integrated circuit in any of the embodiments of the present invention. Methods of integrated circuit open defect prediction in the present invention include, but are not limited to: and 100, performing optical proximity effect correction on the photoetching patterns contained in the integrated circuit design layout to obtain a first simulation pattern. And 200, correcting the first simulation pattern based on the process of etching the first simulation pattern to obtain a second simulation pattern. Optionally, the modifying the first simulation pattern based on the process of etching the first simulation pattern according to the embodiment of the present invention includes: forming an etching deviation matrix group based on a simulation process of etching the first simulation pattern, wherein the etching deviation matrix group is used for representing the profile change of the first simulation pattern generated by etching; and correcting the first simulation pattern through the etching deviation matrix group. And 300, correcting the second simulation pattern based on the process of chemical mechanical planarization treatment of the second simulation pattern to obtain a third simulation pattern. And 400, determining a plurality of graph fragments by sectioning the target line graph contained in the third simulation graph. The target line pattern in the embodiment of the invention is a metal line pattern. Optionally, determining the plurality of graphics fragments by segmenting the target line graph included in the third simulation graph includes: traversing all target line patterns contained in the third simulation pattern, and respectively removing tail ends of all target line patterns; and carrying out segmentation division on the target line graph with the tail end removed so as to obtain a plurality of graph segments. And 500, predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all graph segments. Optionally, the topographical features in embodiments of the present invention comprise a minimum width. Predicting whether the target line pattern has an open defect according to the morphological features of all the pattern segments comprises: determining that the target line pattern has an open circuit defect according to the fact that the minimum width of any pattern segment is smaller than the open circuit defect threshold value; or determining that the target line pattern has no open defects according to the fact that the minimum width of all the pattern fragments is larger than or equal to the open defect threshold value. Optionally, determining that the target line pattern has an open defect according to the minimum width of any pattern segment being less than the open defect threshold comprises: and determining the open-circuit probability of the graph segment according to the graph segment with the minimum width smaller than the open-circuit defect threshold value, and determining the open-circuit probability of the target line graph according to the open-circuit probability of the graph segment. Optionally, the topographical features in embodiments of the present invention include edge roughness. Predicting whether the target line graph has an open defect according to the morphological characteristics of all graph segments comprises: predicting whether the target line pattern has an open defect according to the edge roughness of both sides of all the pattern segments.
As shown in fig. 5, a storage medium storing computer readable instructions that, when executed by one or more processors, cause the one or more processors to perform the steps of a method of open defect prediction for an integrated circuit in any of the embodiments of the invention. Methods of integrated circuit open defect prediction in the present invention include, but are not limited to: and 100, performing optical proximity effect correction on the photoetching patterns contained in the integrated circuit design layout to obtain a first simulation pattern. And 200, correcting the first simulation pattern based on the process of etching the first simulation pattern to obtain a second simulation pattern. Optionally, the modifying the first simulation pattern based on the process of etching the first simulation pattern according to the embodiment of the present invention includes: forming an etching deviation matrix group based on a simulation process of etching the first simulation pattern, wherein the etching deviation matrix group is used for representing the profile change of the first simulation pattern generated by etching; and correcting the first simulation pattern through the etching deviation matrix group. And 300, correcting the second simulation pattern based on the process of chemical mechanical planarization treatment of the second simulation pattern to obtain a third simulation pattern. And 400, determining a plurality of graph fragments by sectioning the target line graph contained in the third simulation graph. The target line pattern in the embodiment of the invention is a metal line pattern. Optionally, determining the plurality of graphics fragments by segmenting the target line graph included in the third simulation graph includes: traversing all target line patterns contained in the third simulation pattern, and respectively removing tail ends of all target line patterns; and carrying out segmentation division on the target line graph with the tail end removed so as to obtain a plurality of graph segments. And 500, predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all graph segments. Optionally, the topographical features in embodiments of the present invention comprise a minimum width. Predicting whether the target line pattern has an open defect according to the morphological features of all the pattern segments comprises: determining that the target line pattern has an open circuit defect according to the fact that the minimum width of any pattern segment is smaller than the open circuit defect threshold value; or determining that the target line pattern has no open defects according to the fact that the minimum width of all the pattern fragments is larger than or equal to the open defect threshold value. Optionally, determining that the target line pattern has an open defect according to the minimum width of any pattern segment being less than the open defect threshold comprises: and determining the open-circuit probability of the graph segment according to the graph segment with the minimum width smaller than the open-circuit defect threshold value, and determining the open-circuit probability of the target line graph according to the open-circuit probability of the graph segment. Optionally, the topographical features in embodiments of the present invention include edge roughness. Predicting whether the target line graph has an open defect according to the morphological characteristics of all graph segments comprises: predicting whether the target line pattern has an open defect according to the edge roughness of both sides of all the pattern segments.
Obviously, compared with a complex open probability calculation scheme (for example, based on the Monte Carlo principle), the method has the outstanding advantages of higher running speed, higher calculation efficiency, suitability for large-scale or very large-scale integrated circuit design and the like. Therefore, the invention can meet the requirement of mass production and has wide application range.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable storage medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable storage medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection (electronic device) with one or more wires, a portable computer cartridge (magnetic device), a random access Memory (RAM, random Access Memory), a Read-Only Memory (ROM), an erasable programmable Read-Only Memory (EPROM, erasable Programmable Read-Only Memory, or flash Memory), an optical fiber device, and a portable compact disc Read-Only Memory (CDROM, compact Disc Read-Only Memory). In addition, the computer-readable storage medium may even be paper or other suitable medium upon which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits with logic gates for implementing logic functions on data signals, application specific integrated circuits with appropriate combinational logic gates, programmable gate arrays (PGA, programmable Gate Array), field programmable gate arrays (FPGA, field Programmable Gate Array), and the like.
In the description of the present specification, a description referring to the terms "present embodiment," "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
The above description is only of the preferred embodiments of the present invention, and is not intended to limit the invention, but any modifications, equivalents, and simple improvements made within the spirit of the present invention should be included in the scope of the present invention.
Claims (9)
1. A method of integrated circuit open defect prediction, comprising:
performing optical proximity effect correction on a photoetching pattern contained in the integrated circuit design layout to obtain a first simulation pattern;
correcting the first simulation pattern based on the process of etching the first simulation pattern to obtain a second simulation pattern;
correcting the second simulation pattern based on the process of chemical mechanical planarization treatment of the second simulation pattern to obtain a third simulation pattern;
determining a plurality of graph fragments by sectionally dividing a target line graph contained in the third simulation graph;
predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all graph segments; wherein the topographical feature is a minimum width or edge roughness;
the determining the plurality of graph segments by segmenting the target line graph contained in the third simulation graph comprises the following steps:
traversing all target line patterns contained in the third simulation pattern;
the tail ends of all target line patterns are removed respectively;
and carrying out segmentation division on the target line graph with the tail end removed so as to obtain a plurality of graph segments.
2. The method of claim 1, wherein when the topographical feature is a minimum width, the predicting whether the target line pattern has an open defect based on topographical features of all pattern segments comprises:
determining that the target line graph has an open circuit defect according to the fact that the minimum width of any graph segment is smaller than an open circuit defect threshold value;
or determining that the target line pattern has no open circuit defect according to the fact that the minimum width of all pattern fragments is larger than or equal to the open circuit defect threshold value.
3. The method of claim 2, wherein determining that the target line pattern has an open defect based on a minimum width of any pattern segment being less than an open defect threshold comprises:
determining the open circuit probability of the graph segment according to the fact that the minimum width of the graph segment is smaller than the open circuit defect threshold value;
and determining the open circuit probability of the target line graph according to the open circuit probability of the graph segment.
4. The method of integrated circuit open defect prediction of claim 1, wherein the modifying the first simulation pattern based on the process of etching the first simulation pattern comprises:
forming an etching deviation matrix group based on a simulation process of etching the first simulation pattern, wherein the etching deviation matrix group is used for representing the profile change of the first simulation pattern generated by etching;
and correcting the first simulation graph through the etching deviation matrix group.
5. The method of claim 1, wherein when the topographical feature is edge roughness, the predicting whether the target line pattern has an open defect based on topographical features of all pattern segments comprises:
predicting whether the target line pattern has an open circuit defect according to the edge roughness of both sides of all pattern fragments.
6. The method of claim 1, wherein the target line pattern is a metal line pattern.
7. An apparatus for integrated circuit open defect prediction, comprising:
the pattern correction module is used for correcting the optical proximity effect of the photoetching pattern contained in the integrated circuit design layout to obtain a first simulation pattern;
the first correction module is used for correcting the first simulation pattern based on the process of etching the first simulation pattern so as to obtain a second simulation pattern;
the second correction module is used for correcting the second simulation pattern based on the process of chemical mechanical planarization treatment of the second simulation pattern so as to obtain a third simulation pattern;
the graphic segmentation module is used for determining a plurality of graphic fragments in a manner of segmenting and dividing a target line graphic contained in the third simulation graphic;
the defect prediction module is used for predicting whether the target line graph has an open circuit defect according to the morphological characteristics of all graph segments; wherein the topographical feature is a minimum width or edge roughness;
the graphic segmentation module is specifically used for:
traversing all target line patterns contained in the third simulation pattern;
the tail ends of all target line patterns are removed respectively;
and carrying out segmentation division on the target line graph with the tail end removed so as to obtain a plurality of graph segments.
8. A computer device comprising a memory and a processor, the memory having stored therein computer readable instructions which, when executed by the processor, cause the processor to perform the steps of the method of integrated circuit open defect prediction as claimed in any one of claims 1 to 6.
9. A storage medium storing computer readable instructions which, when executed by one or more processors, cause the one or more processors to perform the steps of the method of integrated circuit open defect prediction as claimed in any one of claims 1 to 6.
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