CN113536351B

CN113536351B - Encryption method with permanent encryption based on FLASH type FPGA

Info

Publication number: CN113536351B
Application number: CN202110850726.4A
Authority: CN
Inventors: 曹常锐; 蔺旭辉; 马金龙
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2021-07-27
Filing date: 2021-07-27
Publication date: 2023-01-20
Anticipated expiration: 2041-07-27
Also published as: CN113536351A

Abstract

The invention discloses an encryption method with permanent encryption based on a FLASH type FPGA, belonging to the technical field of FLASH type FPGA logic. The encryption method comprises four encryption steps of primary encryption, combined password encryption, encryption result check feedback and decryption result feedback. The first-level encryption comprises permanent encryption and FLASH _ LCOK, the combined password encryption comprises multi-bit user password encryption and multi-bit fixed password encryption, and the states of the permanent encryption, the FLASH _ LOCK and the user encryption can be returned to the upper computer for judgment by the encryption result feedback and the decryption result feedback. The novel encryption method of the FLASH type FPGA with the permanent encryption can simply and practically improve the security of a chip only by controlling an addressing circuit of a FLASH switch, and reduce the possibility that data on the FLASH type FPGA is read and modified by an attacker. The permanent encryption design can prohibit the JTAG device from accessing the chip data, and the multi-bit user password encryption can be adapted to an AES encryption mode. The invention has strong universality and high safety and can effectively deal with the malicious attacks of the current mainstream.

Description

Encryption method with permanent encryption based on FLASH type FPGA

Technical Field

The invention relates to the technical field of FLASH type FPGA logic, in particular to an encryption method with permanent encryption based on a FLASH type FPGA.

Background

FLASH memory type FPGA (Field Programmable Gate Array) is an advanced FPGA structure at present; the FPGA is nonvolatile, small in size, reprogrammable and has the characteristics of LAPU (Live At Power _ Up) and the like, and is used for manufacturing an aerospace-oriented anti-radiation FPGA device. The FLASH type FPGA chip is a reprogrammable FPGA device based on a FLASH structure, the FPGA chip of the type adopts a single chip solution, does not need an external configuration device, can operate after being powered on, can store configuration codes after being powered off, has more reliable single-particle-upset resistance compared with an SRAM type FPGA, and has relatively small process size; the reprogrammable nature of this is also a distinct advantage over antifuse-type FPGAs. However, the process is relatively more complex, the most advanced CMOS process cannot be used, and the on-resistance and complex capacitance inside the FLASH type FPGA are large, so that the FLASH type FPGA is not widely used at present.

The traditional safety protection of the FLASH type FPGA uses a multi-bit key, and the range of the FLASH type FPGA series of the ACTEL company is from 55 bits to 263 bits, and whether the decryption of the key is the only way for a user to access the FLASH type FPGA chip or not after the safety key is programmed. At the speed of the current device JTAG port, it takes about 57 years for only 55 bits of the security key to decrypt if an exhaustive approach is used. However, in a reverse engineering mode, the metal connection layers of the chip are sequentially stripped and photographed to obtain a chip structure, so that a circuit diagram of an original design is obtained to re-manufacture a blank circuit, and the capability of the existing FLASH type FPGA chip for coping with the reverse engineering is still poor.

Due to the reprogrammable characteristic of the FLASH type chip, an attacker can also sample an FPGA configuration interface or obtain the configuration information of the FPGA through an engineering file, and write bit streams in the configuration file into the FLASH type FPGA chip with the same blank internal circuit structure according to a special time sequence, so that the same product can be copied, and the intellectual property of a designer is stolen. In addition, the black box attack is also one of the commonly used means of attack, but the attack means is influenced by the difficulty degree of circuit design, and for the current FLASH chip, the design of multi-user passwords makes the password cracking of the FPGA chip by an attacker by using an exhaustion method more difficult.

At present, the mainstream method for encrypting the FLASH type FPGA chip is to utilize a built-in AES encryption device and a built-in AES decryption device, so that external data can be input after being decrypted by an internal AES, and internal data can be output after being encrypted by the AES. Another method is a method using MAC (information verification code), and the specific encryption method is to add MAC verification in the secure data stream transmission to ensure that information is not changed in the transmission to prevent the chip from being maliciously tampered, so that the security of the FPGA chip is effectively improved to a certain extent, but the security may still be cracked by an attacker using external resources.

Disclosure of Invention

The invention aims to provide an encryption method with permanent encryption based on a FLASH type FPGA so as to improve the security performance of the FLASH type FPGA.

In order to solve the technical problem, the invention provides an encryption method with permanent encryption based on a FLASH type FPGA, which comprises the following steps: the method comprises four encryption steps of primary encryption, combined password encryption, encryption result check feedback and decryption result feedback, wherein:

the first-level encryption comprises permanent encryption and FLASH _ LOCK encryption; the permanent encryption is used for permanently encrypting the FLASH type FPGA chip; the FLASH _ LOCK encryption LOCKs the readable and writable property of the chip;

the combined password encryption comprises a multi-bit fixed password and a multi-bit user set password encryption, and the password used for encryption is formed by combining two passwords; the multi-bit fixed password closes an addressing critical path of the FLASH switch after programming, so that the internal data of the FLASH type FPGA chip cannot be normally accessed through a JTAG device; the multi-bit user-set password defines multi-bit data for a user, AES encryption is supported, the password can be decrypted only under the condition that permanent encryption is not carried out, and the priority of the password is lower than that of the permanent encryption;

the encryption result checking feedback is used for feeding back an encryption result of the FLASH type FPGA chip of the upper computer, and the encryption result comprises a permanent encryption state, a FLASH _ LOCK encryption state and a user encryption state;

and the decryption result feedback is used for feeding back the user password decryption result of the FLASH type FPGA chip of the upper computer.

Optionally, the permanent encryption belongs to one-time encryption based on software and circuit design, data interaction between the chip and an external JTAG device can be effectively isolated after programming, so that data in the chip cannot be read or written, the encrypted data is 1 bit, and when the encryption is successful, a user password is input correctly and the chip cannot be unlocked;

after the FLASH _ LOCK encryption is carried out, the chip can be erased, programmed and read only after the chip is subjected to combined password decryption.

Optionally, the multi-bit fixed password is related to whether the FPGA chip is permanently encrypted, when the permanent encryption is not encrypted, the multi-bit fixed password is consistent with a preset password of the upper computer, and after the permanent encryption is encrypted, the multi-bit password is inverted or otherwise transformed according to bits, that is, the multi-bit fixed password is inconsistent with default data of the upper computer.

Optionally, when the encryption result inspection feedback is in a permanent encryption state, the upper computer prints that the permanent encryption is encrypted, and the FLASH type FPGA chip directly loses power and exits the operation; .

Optionally, when the feedback is the encrypted state of the FLASH _ LOCK, the upper computer prints 'permanent encryption is not encrypted, the FLASH _ LOCK is encrypted', and the FLASH type FPGA chip exits the operation;

when the feedback is the user encryption state, the upper computer prints 'user encryption is successful'; at this time, after the encryption is successful, the operations of encryption permanent encryption or locking of the FLASH _ LOCK are required, and the FLASH type FPGA chip can quit the operations.

Optionally, the specific detection process of the user password decryption result fed back to the FLASH type FPGA chip of the upper computer includes:

unlocking by a user password;

detecting a user password unlocking result;

operating the FLASH type FPGA chip after detecting the successful unlocking;

detecting the unlocking failure, detecting the permanent encryption state, if the permanent encryption or the FLASH _ LOCK is encrypted, printing a detection result, and exiting the operation; if neither the permanent encryption nor the FLASH _ LOCK is encrypted, the circuit is operated.

Optionally, the encryption method includes:

(1) The FLASH type FPGA enters the decryption of the user encryption;

(2) An encryption result verification feedback comprising (2 a) a multi-bit user password encrypted state and (2 b) a permanently encrypted encryption state;

(3) Primary encryption, permanent encryption and FLASH _ LOCK encryption result detection feedback;

(4) Encrypting a multi-bit user password;

(5) Performing encryption primary encryption, including (5 a) encrypting permanent encryption and (5 b) encrypting FLASH _ LOCK;

(6) And exiting the operation.

Optionally, the specific process of the encryption method includes:

when the encrypted FLASH type FPGA chip enters a user decryption mode, user password data are filled into the FPGA chip by using a JTAG device through a decryption special instruction and fed back to a decryption result of an upper computer through an internal detection circuit; if the current permanent encryption and the FLASH _ LOCK are not encrypted, entering the next operation; if the FLASH _ LOCK is encrypted, the power is cut off and the operation on the FLASH type FPGA is quitted;

when the combined password encryption fed back in the step (2 a) is successfully unlocked, ending the current decryption operation, entering the next operation, if the chip password needs to be operated, erasing circuit data before programming the chip according to the working characteristics of the FLASH type FPGA, and resetting the user password and the FLASH _ LOCK through the erasing operation;

if the user needs to set a user password, the upper computer operates the FLASH type FPGA chip to enter the encryption detection of the FLASH _ LOCK, the operation is the first step of operating all the chips, when the FLASH _ LOCK is reset, the user can enter the step (4), the user sets multi-bit data as the user password, and the password structure of the FLASH type FPGA chip programmed by the upper computer is the combination of the multi-bit fixed password and the multi-bit user password;

after encryption of the combined password, the upper computer operates the FLASH type FPGA chip to enter the step (5 b), operates the FLASH _ LOCK, and exits the encryption operation after the encryption is finished;

if the user directly enters the permanent encryption operation, after decryption is finished, whether the current user encryption is successfully unlocked needs to be detected, after the unlocking is successful, the upper computer controls the FPGA chip to enter the permanent encryption operation, the permanent encryption operation programs the fixed password which is inverted according to the bit or performs other logic transformation on the fixed password, and after the encryption operation is finished, the operation is quitted after power failure.

Compared with the prior art, the invention has the following advantages:

(1) The encryption method can be realized only by a special encryption circuit module in the FLASH type FPGA, and a peripheral encryption circuit is not required to be added;

(2) The encrypted data realizes password input and reset based on programming and erasing of a FLASH switch in a FLASH type FPGA, and whether the encryption of a user is decrypted or not is realized by utilizing a verification circuit of the FPGA of the FLASH;

(3) Besides being capable of feeding back to an upper computer, after encryption is successfully achieved, the upper computer can control a circuit to be powered off and quit, the encryption signal can also be designed in a control circuit inside an FPGA based on the principle, and an attacker is prevented from accessing chip data by controlling transmission of a key control signal.

Drawings

FIG. 1 is a schematic diagram showing the specific steps of an encryption method with permanent encryption based on FLASH type FPGA;

FIG. 2 is a schematic diagram of an encryption flow of the encryption method with permanent encryption based on FLASH type FPGA;

FIG. 3 is a schematic diagram of a decryption process of the encryption method with permanent encryption based on FLASH type FPGA;

fig. 4 is a schematic view of a permanent encryption flow of the encryption method with permanent encryption based on the FLASH type FPGA of the present invention.

Detailed Description

The encryption method with permanent encryption based on FLASH type FPGA according to the present invention is further described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

The invention provides an encryption method with permanent encryption based on a FLASH type FPGA, which comprises the following steps as shown in figure 1: cipher encryption, permanent encryption, encryption result check feedback and decryption result feedback are combined.

Specifically, the encryption process is as shown in fig. 2, after the user finishes designing the FLASH type FPGA, the state of the FLASH _ LOCK in encryption needs to be determined (step 201), and the FLASH _ LOCK is initialized by an erase operation after the user password is decrypted. When the erasure reset is judged not to be carried out, the encryption operation is stopped, and the power failure quits; after FLASH _ LOCK has been initialized, the user can choose whether to do permanent encryption (step 202); if the permanent encryption is not selected, presetting the fixed password as 4 bits data consistent with the preset data in the upper computer (step 2031); if permanent encryption is selected, the fixed password is inverted bitwise (step 2032); after the combination password encryption is successful, the chip enters FLASH _ LCOK encryption (step 2042) or FLASH _ LOCK and permanent encryption (step 2041), and after the encryption is successful, the chip is powered down and exits the encryption operation.

Specifically, as shown in fig. 3, when a user connects a chip through a JTAG device, a decryption operation of a user password needs to be first performed (step 301), when an input password is consistent with a set password, a FLASH _ LOCK is opened (step 3021), the user can normally access internal data of the chip, and if the FLASH _ LOCK is not unlocked, it is checked whether the chip is permanent.

Encrypt (step 3022) and return to the state of this one-level encryption, then power down exit directly (step 3023). When the user connects the chip which is permanently encrypted through the JTAG device, even if the input password is consistent with the preset password, the user still can not access the internal data of the chip because the fixed password is changed.

Specifically, the specific operation method of the permanent encryption of the encryption method with permanent encryption of the FLASH type FPGA of the present invention is shown in fig. 4. After the permanent encryption operation (step 401), the preset fixed password in the combined password data sent by the upper computer is inverted according to bits (step 402), the key path inside the FLASH chip is closed (step 403), and both an attacker and a user access the data inside the chip through the JTAG device (step 404).

Preferably, the change of the fixed password in the permanent encryption method is related to the designed encryption circuit, different configuration information can be stored by programming different fixed passwords, and a key path for accessing data in the FPGA by JTAG can be selected to be closed without being limited to bit-wise negation. In this embodiment, the bit-wise negation operation on the fixed password is a preset operation of closing a designed JTAG interface of the FLASH-type FPGA chip.

Preferably, in this embodiment, the permanently encrypted fixed password is not limited to 4 bits, and the password lengths of the fixed password and the user password may be set according to the size of the FLASH switch array and the encryption difficulty of the combined password.

Preferably, in this embodiment, the permanent encryption is a one-time encryption, and after the permanent encryption, anyone, including the user himself, cannot access through the JTAG device, although some general-purpose instructions may still be used.

The invention contains the user password encryption which can support AES encryption, the multi-bit user password can effectively avoid being exhaustively decrypted, if the safety of the FPGA chip is further improved, the multi-bit user password encryption circuit can be upgraded to adopt a built-in circuit which needs AES encryption for a data input chip and needs AES decryption for the output data of the chip to carry out further encryption; the invention comprises the FLASH _ LOCK switch, can effectively ensure that the internal data of the FLASH type FPGA chip can be accessed and operated only after being correctly decrypted, and can effectively prevent the external unauthorized operation on the FLASH type FPGA chip. Based on the characteristic that the FLASH type FPGA can work after being electrified, a channel for permanently locking a chip structure after programming can be provided for a designer. When the permanent encryption is encrypted, any operation of accessing the internal data of the chip through the JTAG device is rejected, the permanent encryption is one-time encryption and is realized only through the design of an internal hardware circuit, and the data exchange with an external interface is directly avoided.

The permanent encryption mode provided by the invention is realized only by changing a multi-bit fixed password, if the multi-bit fixed password is not locked, the multi-bit fixed password is consistent with a password pre-stored in an upper computer, and the password input by a user is consistent with a set password, so that the unlocking can be realized; when the chip is permanently encrypted, the fixed password is inverted according to bits, the combined password can never be consistent with the preset password, and further the chip can not be decrypted through the password. The permanent encryption mode provided by the invention has the advantages that the setting of the initial value of the multi-bit fixed password and the operation of the fixed password transformation after the permanent encryption can be controlled only by programming software, and only the switch for the operation of the fixed password transformation can be turned on or off. The user has no right to modify the password content, i.e. the encryption mode is protected inside the programming software.

Once the 1-bit permanent encryption data is successfully configured to the FLASH type FPGA chip, an addressing circuit corresponding to the address of the stored password in the circuit structure is closed. Based on this, even if an attacker attacks the chip by cracking the programming software, the JTAG device cannot access the password storage position to decrypt the password storage position when inputting the correct user password, and moreover, even if the global reset signal of the chip is triggered, the permanent encryption cannot be changed.

The conversion of the permanent encryption to the fixed password can control the starting and closing of an addressing circuit of a FLASH array in the FLASH type FPGA, and can ensure that even an attacker uses a special method to unlock mixed encryption, the FLASH switch cannot be correctly addressed by using a JTAG device, thereby realizing the second protection of data information in the chip.

The encryption system provided by the invention is integrated in the FLASH type FPGA, and the permanent encryption design can effectively prevent an attacker from over-building or maliciously destroying the FPGA product and stealing data in a chip, so that the system is simple and practical.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. An encryption method with permanent encryption based on FLASH type FPGA is characterized by comprising the following steps: the method comprises four encryption steps of primary encryption, combined password encryption, encryption result check feedback and decryption result feedback, wherein:

the combined password encryption comprises a multi-bit fixed password and a multi-bit user set password encryption, and the password used for encryption is formed by combining two passwords; the multi-bit fixed password closes the addressing critical path of the FLASH switch after programming, so that the internal data of the FLASH type FPGA chip cannot be normally accessed through a JTAG device; the multi-bit user-set password defines multi-bit data for a user, AES encryption is supported, the password can be decrypted only under the condition that permanent encryption is not carried out, and the priority of the password is lower than that of the permanent encryption;

2. The encryption method with permanent encryption based on FLASH type FPGA according to claim 1, wherein the permanent encryption belongs to one-time encryption based on software and circuit design, and after programming, data interaction between the chip and an external JTAG device can be effectively isolated, so that data in the chip can not be read and written, the encrypted data is 1 bit, and when the encryption is successful, the user password input is correct and the chip can not be unlocked;

3. The encryption method with permanent encryption based on the FLASH-type FPGA according to claim 2, wherein the multi-bit fixed password is related to whether the FPGA chip is permanently encrypted or not, and when the permanent encryption is not encrypted, the multi-bit fixed password is consistent with a preset password of the upper computer, and when the permanent encryption is encrypted, the multi-bit password is inverted or otherwise transformed in a bit manner, namely, is inconsistent with default data of the upper computer.

4. The encryption method with permanent encryption based on the FLASH type FPGA according to claim 3, wherein when the encryption result check feedback is in a permanent encryption state, the upper computer prints that the permanent encryption is encrypted, and the FLASH type FPGA chip directly loses power and exits the operation;

when the FLASH _ LOCK encryption state is fed back, the upper computer prints 'permanent encryption is not encrypted, FLASH _ LOCK is encrypted', and the FLASH type FPGA chip exits the operation;

5. The encryption method with permanent encryption based on the FLASH type FPGA according to claim 4, wherein the specific detection process of the user password decryption result fed back to the FLASH type FPGA chip of the upper computer comprises the following steps:

unlocking by a user password;

detecting a user password unlocking result;

operating a FLASH type FPGA chip after successful unlocking detection;

detecting unlocking failure, detecting a permanent encryption state, printing a detection result and exiting the operation if the permanent encryption or the FLASH _ LOCK is encrypted; if neither the permanent encryption nor the FLASH _ LOCK is encrypted, the circuit is operated.

6. The encryption method with permanent encryption based on FLASH type FPGA of claim 5, wherein the encryption method comprises:

(1) The FLASH type FPGA enters the decryption of user encryption;

(4) Encrypting a multi-bit user password;

(6) And exiting the operation.

7. The encryption method with permanent encryption based on FLASH type FPGA of claim 6, wherein the specific flow of said encryption method includes:

if the user needs to set the user password, the upper computer operates the FLASH type FPGA chip to enter the encryption detection of the FLASH _ LOCK, the operation is the primary step of operating all the chips, when the FLASH _ LOCK is reset, the user can enter the step (4), the user sets multi-bit data as the user password, and the upper computer programs the password structure of the FLASH type FPGA chip to be the combination of the multi-bit fixed password and the multi-bit user password;