WO2018040678A1

WO2018040678A1 - Memory data protection method, integrated circuit chip, and storage medium

Info

Publication number: WO2018040678A1
Application number: PCT/CN2017/089040
Authority: WO
Inventors: 刘振军
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2016-08-30
Filing date: 2017-06-19
Publication date: 2018-03-08
Also published as: CN107784235A

Abstract

A memory data protection method, an integrated circuit chip, and a storage medium. The method comprises setting first access authentication information for a specified data saving area of a memory (101). The method further comprises: obtaining information about an access target of a specified port, and limiting, when the access target is the specified data saving area, to access the specified data saving area (102); and obtaining second access authentication information, and allowing, when the second access authentication information matches the first access authentication information, the access to the specified data saving area (103).

Description

Memory data protection method, integrated circuit chip and storage medium

Cross-reference to related applications

The present application is based on a Chinese patent application filed on Apr. 30, 2016, the entire disclosure of which is hereby incorporated by reference.

Technical field

The present application relates to the field of integrated circuit data security, and in particular, to a memory data protection method, an integrated circuit chip, and a storage medium.

Background technique

Usually, a chip such as a system on chip (SoC) has a memory embedded therein, such as a nonvolatile memory (Flash), a read only memory (ROM), and a random access memory (Ram, Random Access Memory). The memory is used to store applications and user data, etc. The stored application and user data include algorithm software, fingerprint information, and password information, and the information is extremely confidential, and is an object that the chip needs to be protected. . Therefore, the protection of in-chip memory data becomes more and more important.

Existing methods for encrypting chip memory data usually require an additional encryption chip to encrypt the memory, which increases the cost and design complexity on the one hand, and on the other hand, the method can only be used for off-chip memory, on-chip. Memory is powerless.

Another encryption method is based on a set of security collaboration specifications that require software and hardware to work together; for example, software needs to be configured in a secure mode to enable software in non-secure mode to access memory in secure mode. So, the system in which the chip is located becomes more complicated, and it needs to match the processor core with this function, for some old versions. The core is not available; and when it is operated by the Joint Test Action Group (JTAG), there is no security effect due to the lack of software.

Another method is to directly burn the pins (PIN) of the debugging port when the chip is mass-produced. On the one hand, it is necessary to modify the package and increase the workload; on the other hand, if you find the problem, To find the problem through the debug port, but since the debug port is no longer available, it will become unworkable.

Therefore, how to implement memory data protection and reduce the complexity and cost of system design is an urgent problem to be solved.

Summary of the invention

In view of this, the present application is expected to provide a memory data protection method, an integrated circuit chip, and a storage medium, which can implement memory data protection and reduce system design complexity and cost.

In order to achieve the above object, the technical solution of the present application is implemented as follows:

The present application provides a memory data protection method, the method comprising: setting a first access authentication information for a specified data storage area of a memory; the method further comprising:

Obtaining access target information of the designated port; when the access target is the specified data save area, restricting access to the specified data save area;

Obtaining second access authentication information;

When the second access authentication information matches the first access authentication information, access to the designated data save area is permitted.

In the above solution, the method further includes: when the preset condition is met, clearing the content of the specified data storage area.

In the above solution, when the preset condition is met, the content of the specified data storage area is cleared, including:

Clearing the content of the specified data storage area when the number of times the second access authentication information fails to match the first access authentication information exceeds a preset matching failure threshold; and/or,

When the preset clear command is input, the content of the specified data save area is cleared.

In the above solution, the method further includes: storing the first access authentication information in the designated data storage area.

The application also provides an integrated circuit chip, the integrated circuit chip comprising: a setting module and a control module; wherein

The setting module is configured to set first access authentication information for a designated data storage area of the memory;

The control module is configured to acquire access target information of the designated port; when the access target is the specified data save area, restrict access to the specified data save area; the input second access authentication information and the first access When the authentication information matches, the specified data storage area is allowed to be accessed.

In the above solution, the control module is configured to clear the content of the specified data storage area when the preset condition is met.

In the above solution, the control module is configured to clear the content of the specified data storage area when the number of times that the second access authentication information and the first access authentication information fail to match exceed the preset matching failure number threshold; and or,

In the above solution, the setting module is configured to store the first access authentication information in the designated data storage area.

The application also provides a storage medium comprising a set of computer executable instructions configured as steps of the aforementioned method.

The application also provides an integrated circuit chip comprising: a processor and a memory for storing a computer program capable of running on the processor,

Wherein the processor is configured to perform the steps of the foregoing method when the computer program is run.

A memory data protection method, an integrated circuit chip and a storage medium provided by the present application, Setting a first access authentication information for a specified data storage area of the memory by using software or hardware logic inside the chip; acquiring access target information of the designated port; and restricting access when the access target is the specified data storage area Specifying a data save area; accessing the specified data save area when the input second access authentication information matches the first access authentication information. In this way, only when the input access authentication information is consistent with the access authentication information preset in the specified data storage area, access to the specified data storage area is allowed, memory data protection can be realized, and the system design complexity and cost of the chip are reduced.

DRAWINGS

1 is a schematic flow chart of a method for protecting a memory data of the present application;

2 is a schematic diagram of state transition of a chip of the present application;

3 is a schematic diagram of hardware logic for reading a chip password according to the present application;

4 is a schematic diagram of hardware logic of the chip locking of the present application;

FIG. 5 is a schematic diagram of hardware logic for unlocking a chip of the present application; FIG.

6 is a schematic diagram of hardware logic of restoring factory settings of the present application;

FIG. 7 is a schematic structural diagram of an integrated circuit chip of the present application.

detailed description

In the application, the first access authentication information is set for the designated data storage area of the memory; the access target information of the designated port is acquired; and when the access target is the designated data storage area, the access to the designated data storage area is restricted; When the second access authentication information matches the first access authentication information, access to the designated data storage area is permitted.

The present application will be further described in detail below with reference to the embodiments.

The memory data protection method provided by the present application is as shown in FIG. 1 , and the method includes:

Step 101: Set first access authentication information for a specified data storage area of the memory;

The memory data protection method provided by the present application can be implemented by using software inside the chip, such as The memory data protection by the startup program may also be implemented by the hardware logic of the chip; here, the memory data protection method is explained by taking the hardware logic implementation as an example;

Typically, the chip contains ROM, RAM, Flash, and other programmable memories. The ROM is used to store the startup program, and cannot be rewritten after being solidified. The RAM is used to store the intermediate variables of the central processing unit (CPU, Central Processing Unit), and the Flash is used to store the user program and some user information, and the user can rewrite; It usually contains a data area and a non-Volatile Random Access Memory (NVR) area. The two areas are independent of each other and cannot be accessed at the same time. It is necessary to select which area to access through the configuration register. The data area is used to store user programs and data, and the NVR area is used to store passwords, bad block information, and important information of other users. The specified data storage area may include a data area and an NVR area of the flash, etc.; first, the first access authentication information may be set for the specified data storage area, where the first access authentication information may include an access password, etc.; further, Set a multi-layer password to improve security; you can save the password in the NVR area to improve password security.

Step 102: Obtain access target information of the designated port. When the access target is the designated data save area, restrict access to the designated data save area.

Here, the designated port includes one or more ports specified in each input/output (I/O, Input/Output) port of the chip, such as a COM port and a JTAG port; and the access target information includes: an access address, and the like; The access authority of the designated port may be preset, and the identity authentication is required when the designated port accesses the specified data storage area; when the chip is started, the chip may read the first access authentication information of the NVR area into the register, and detect When the access address to the designated port is the designated data storage area, the specified data storage area may be locked, and access to the designated data storage area is not allowed; thus, non-secure access may be restricted.

Step 103: Acquire second access authentication information, and when the second access authentication information matches the first access authentication information, allow access to the designated data storage area;

Here, the second access authentication information may pass through a designated port that is being accessed or The input of the I/O port is performed, and the second access authentication information includes an access password and the like;

When the second access authentication information matches the first access authentication information, access to the designated data storage area is allowed.

Further, the specified data storage area in the chip may be set to an unlock state, and when not in the unlock state, the designated data storage area may be accessed without restriction.

Here, the setting of the unlocked state may include: when the first access authentication information is preset default information, and/or when the designated port has no access activity; when the first access authentication information is a preset In the default information, it can be considered that the data that the chip has just initialized and does not need to be protected is in the specified data storage area, and therefore, the specified data storage area may not be protected by access; when the designated port has no access activity, it is considered to be absent. An external security risk event occurs. Therefore, the specified data storage area may not be protected from access, and the specified data storage area may be freely accessed by the chip itself.

Further, the chip is further provided with one or more methods for performing a factory reset on the specified data storage area, including: when the second authentication information matches the first authentication information, the number of failed failures is greater than a preset matching failure. When the threshold is reached, and/or, when the chip receives the preset reset command, the designated data save area is factory reset.

Specifically, when the number of failures of matching the second authentication information with the first authentication information is greater than a preset threshold of the number of matching failures, the intentional attack behavior may be considered as the maximum security risk, and the specified data storage area is protected. The data is not illegally obtained, and can be resetted by the factory. At the same time, the chip can be reset by the preset instruction. In case the user forgets the first authentication information, in order to avoid wasting the chip, the preset reset command can be used. Resetting the designated data storage area to play the role of reusing the chip; in order to prevent the user from being unable to use the chip once the user forgets the password of the chip preset, based on the protection of the memory data, by inputting to the chip A set of preset reset commands causes the chip to forcibly clear the preset password. To protect the user program and user data, all data areas must be erased before erasing the NVR area. Domain, this prevents the user program and data from being leaked after the password in the NVR area is erased for some reason.

In practical applications, hardware logic circuits can be used to protect the memory data. First, various states can be set for the chip. Accordingly, the chip can work in different states. As shown in FIG. 2, the state of the chip can include:

Unlocked state: The password is the default value after the memory is erased, that is, the password is invalid. At this time, even if it is detected that the specified port has an action, the chip does not enter the locked state;

Pre-locked state: The password is valid, but the detection logic does not detect the state that the debug port is in any action. In this state, the program can run normally;

Lock status: The password is valid, the detection logic detects the action of the specified port, locks the chip, that is, restricts access to the specified data storage area, and the program running in the Flash is suspended, and the protected memory cannot be accessed;

Unlocked state: After the chip is locked, the state after successful unlocking is performed, the program resumes operation, and the protected memory space is unprotected;

Factory state: In any of the above states, the factory reset operation can be performed. After the operation is completed, it is the factory state. In this state, the user program, data and password information are erased, and the memory can be accessed by the host.

The process of reading the chip password is as shown in FIG. 3, and the hardware logic can be used to read the chip password; after the chip is powered on, the controller automatically reads the password in the NVR area of the memory, that is, reads the first access. Authentication information and the password is stored in the register. At this time, if the password is a valid password, it enters the pre-lock state; if it is an invalid password, it enters the unlock state.

Specifically, after the power-on reset, the chip controller automatically reads the password data of the NVR area of the memory, reads back the password data (DATA), latches the read back DATA into the register, generates a password (PASSWORD) signal, and compares whether the PASSWORD is For the factory password, generate a flag (FLAG) signal; determine the value of FLAG, FLAG=1 means the current password is the factory password, enter no lock Status; FLAG=0 means that the current password is not the factory password and enters the pre-lock state; after entering the pre-lock state, the host can access the memory and start monitoring the action of the debug port.

Figure 4 is a hardware schematic diagram of the chip lock; when the new password is programmed to the specified location, the new password can take effect after the next reset; after the power-on reset, the password is read, and if it is a valid password, it enters the pre-lock state; If the detection logic detects that the specified port has access to the chip, the chip enters a locked state, and the host cannot access the memory, thereby preventing code and user information from being leaked, and preventing the code and user data from being maliciously rewritten. Here, the method for determining whether the password is valid includes determining whether the new password is the initial password, and if it is the initial password, the password is considered to be in an invalid state; wherein the designated port, such as JTAG, also called the debug port, generally needs to provide an external one. When the clock signal TCK has no action, the clock is at a low level, and when there is an action, there is a switch between high and low levels; therefore, the rising edge can be used to count, and after a certain value is counted, the JTAG action can be determined to be valid, and the lock is enabled. (LOCK) signal is pulled high; after the LOCK signal is high, the memory is locked; CLOCK is the working clock, which is counted by the rising edge signal TCK_P of TCK. After counting to N, LOCK is pulled high, indicating that the memory is locked; the data selector in the figure (MUX) is just a schematic diagram, not a real logic circuit. When LOCK = 1, "invalid access" passes through the MUX, indicating that the memory cannot be accessed; when LOCK = 0, the "host access request" passes through the MUX, indicating that the memory can be accessed.

5 is a hardware logic for unlocking a chip. After the chip is locked, the chip can be unlocked by writing a password to a corresponding register of the chip, that is, inputting the second access authentication information to unlock the chip; when the memory is locked Although the debug port does not have access to the memory, it can access the internal unlock register, and the password can be written to the unlock register through the configuration bus to unlock. In order to increase the difficulty of unlocking, multiple password registers can be set to increase the bit width of the password.

Further, in order to prevent brute force decryption, a limit on the number of unlocking times is also added, and if the unlocking is unsuccessful for more than a certain number of times, the factory reset operation is performed. The specific steps of unlocking the chip include: a: The entered password is written to the unlock register; b: the password is correct, UNLOCK_EN is pulled high for one clock cycle; b: the LOCK signal is pulled low; c: the memory is unlocked; if the unlocked number reaches the predetermined value, the recovery is started. The setting steps include: the number of unlock failures reaches the specified number of times; CLEAR_EN is pulled high, indicating that the notification factory reset logic starts to restore the factory setting; RECOVER_EN is pulled high, indicating that the factory reset is started.

Figure 6 shows the hardware logic implementation of the factory reset; any state of the unlocked state, the pre-locked state, the locked state, and the unlocked state can be restored to the factory state by the factory reset operation, that is, the memory is completely wiped. The status of the division. After performing the factory reset, the user password and data are erased. When the factory setting is restored, RECOVER_EN is pulled high, indicating that the factory reset operation is in progress. After the end, RECOVER_EN is pulled low, indicating that the operation is completed. At this time, the falling edge of RECOVER_EN is used to generate the RECOVER_EN_N signal, and the RECOVER_EN_N signal is used as the Select end of the MUX. Pull LOCK low, indicating that the user memory is not locked, the user can access the memory through the debug port;

The operation of restoring the factory settings includes: RECOVER_EN is pulled high, indicating that the factory reset operation starts; erasing the Flash data area, erasing the Flash NVR area; RECOVER_EN is low, indicating that the factory reset operation ends; sampling the falling edge of RECOVER_EN RECOVER_EN_N, And use RECOVER_EN_N to pull LOCK low, indicating that the memory is not locked; the memory can be accessed;

Among them, to prevent misoperation, the factory setting start command can follow certain rules, and the user finally determines the actual receipt to restore the factory settings.

The integrated circuit chip provided by the present application, as shown in FIG. 7, the integrated circuit chip includes: a setting module 71 and a control module 72;

The setting module 71 is configured to set first access authentication information for a designated data storage area of the memory;

The memory data protection method provided by the present application can use software inside the integrated circuit chip The implementation, such as the memory data protection by the startup program, can also be implemented by the hardware logic of the chip; here, the memory data protection method is explained by taking the hardware logic implementation as an example;

Typically, the chip contains ROM, RAM, Flash, and other programmable memories. Among them, the ROM is used to store the startup program, and can not be rewritten after curing. The RAM is used to store the intermediate variables of the CPU runtime, the Flash is used to store the user program and some user information, and the user can rewrite; the Flash usually includes the data area and the NVR area, The areas are independent of each other and cannot be accessed at the same time. It is necessary to select which area to access through the configuration register. The data area is used to store user programs and data, and the NVR area is used to store passwords, bad block information, and important information of other users. The specified data storage area may include a data area and an NVR area of the flash, etc.; first, the first access authentication information may be set for the specified data storage area, where the first access authentication information may include an access password, etc.; further, Set a multi-layer password to improve security; you can save the password in the NVR area to improve password security.

The control module 72 is configured to acquire access target information of the designated port; when the access target is the designated data save area, restrict access to the specified data save area; when the input second access authentication information is When the first access authentication information matches, the access to the specified data storage area is allowed;

Here, the designated port includes one or more ports specified in each I/O port of the chip, such as a COM port and a JTAG port; the access target information includes: an access address, etc.; access of the designated port may be preset Privilege, when the designated port accesses the specified data storage area, identity authentication is required; when the chip is started, the chip can read the first access authentication information of the NVR area into the register, and detect the access address of the specified port. When the designated data storage area is reserved, the specified data storage area may be locked, and access to the specified data storage area is not allowed; thus, non-secure access may be restricted.

The second access authentication information may be input through a designated port or other I/O port that is being accessed, the second access authentication information includes an access password, etc.; when the second access authentication When the certificate information matches the first access authentication information, access to the specified data storage area is permitted.

Further, the specified data storage area in the chip may be set to an unlocked state, and when in the unlocked state, the specified data storage area may be accessed without restriction; wherein the condition of setting the unlocked state may include: When the first access authentication information is preset default information, and/or when the designated port has no access activity; when the first access authentication information is preset default information, it may be considered that the chip has just been initialized and does not need to be The protected data is in the designated data storage area, and therefore, the specified data storage area may not be protected by access; when the designated port has no access activity, no external security risk event is considered to occur, and therefore, the The data save area is designated for access protection, and the specified data save area can be freely accessed by the chip itself.

Further, the chip is further provided with one or more methods for performing a factory reset on the specified data storage area, including: when the second authentication information matches the first authentication information, the number of failed failures is greater than a preset matching failure. When the threshold is received, and/or when the chip receives the preset reset command, the designated data save area is factory reset; when the second authentication information matches the first authentication information, the number of failures is greater than the preset. When the matching failure threshold is used, it can be considered that there is intentional attack behavior, and the security risk is the greatest. To protect the data of the specified data storage area from being illegally obtained, the factory reset can be performed; at the same time, the chip can be reset by default. If the user forgets the first authentication information, in order not to waste the chip, the preset data storage area may be reset by using a preset reset instruction, thereby playing the role of reusing the chip; The user forgets the password of the chip preset and cannot use the chip. Based on the basis of protecting the memory data. Basically, by inputting a set of preset reset commands to the chip, the chip forcibly clears the preset password. To protect the user program and user data, all data areas must be erased first, and then the NVR area is erased. This prevents After some reason causes the password in the NVR area to be erased, the user program and data are leaked.

In practical applications, hardware logic circuits can be used to protect the memory data;

First, various states can be set for the chip. Accordingly, the chip can work in different states. As shown in FIG. 2, the state of the chip can include:

Specifically, after power-on reset, the chip controller automatically reads the password data of the memory NVR area, reads back DATA; latches the read back DATA into the register to generate a PASSWORD signal; compares whether PASSWORD is a factory password, and generates a FLAG signal. ; judge the value of FLAG, FLAG=1 indicates that the current password is the factory password, enter the unlock state; FLAG=0 indicates that the current password is not the factory password, enter the pre-lock state; after entering the pre-lock state, the host can access the memory and start monitoring Debug port action.

Figure 4 is a schematic diagram of the hardware of the chip lock; when the new password is programmed to the specified location, the new secret The code can take effect after the next reset; after the power-on reset, the password is read, and if it is a valid password, it enters the pre-lock state; at this time, if the detection logic detects that the specified port has access to the chip, the chip enters the locked state. The host can't access the memory, which prevents code and user information from leaking out, and prevents code and user data from being maliciously overwritten. Here, the method for determining whether the password is valid includes determining whether the new password is the initial password, and if it is the initial password, the password is considered to be in an invalid state; wherein the designated port, such as JTAG, also called the debug port, generally needs to provide an external one. Clock signal TCK, when there is no action, the clock is at a low level, when there is an action, there is a switch between high and low level; therefore, the rising edge can be used to count, after counting a certain value, it can be judged that the JTAG action is valid, and LOCK is The signal is pulled high; after the LOCK signal is high, the memory is locked; CLOCK is the working clock, which is counted by the rising edge signal TCK_P of TCK. After counting to N, the LOCK is pulled high, indicating that the memory is locked; the MUX in the figure is only a schematic diagram, and Not a real logic circuit. When LOCK = 1, "invalid access" passes through the MUX, indicating that the memory cannot be accessed; when LOCK = 0, the "host access request" passes through the MUX, indicating that the memory can be accessed.

5 is a hardware logic for unlocking a chip. After the chip is locked, the chip can be unlocked by writing a password to a corresponding register of the chip, that is, inputting the second access authentication information to unlock the chip; when the memory is locked Although the debug port does not have access to the memory, it can access the internal unlock register, and the password can be written to the unlock register through the configuration bus to unlock. In order to increase the difficulty of unlocking, multiple password registers can be set to increase the bit width of the password. Further, in order to prevent brute force decryption, a limit on the number of unlocking times is also added, and if the unlocking is unsuccessful for more than a certain number of times, the factory reset operation is performed. The specific steps of unlocking the chip include: a: the input password is written to the unlock register; b: the password is correct, UNLOCK_EN is pulled up one clock cycle; b: the LOCK signal is pulled low; c: the memory is unlocked; if the unlocking number reaches The predetermined value starts the step of restoring the factory settings, including: the number of unlock failures reaches the specified number of times; CLEAR_EN is pulled high, indicating that the notification factory reset logic starts to recover. Factory setting; RECOVER_EN is pulled high to indicate the start of factory reset.

In practical applications, the setup module 71 and the control module 72 can be implemented by a processor or hardware logic or the like of an integrated circuit chip.

The above is only the preferred embodiment of the present application, and is not intended to limit the scope of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in Within the scope of protection of this application.

Based on the foregoing embodiments, the present application further provides a storage medium including a set of computer executable instructions configured to execute:

Setting first access authentication information for a specified data storage area of the memory; acquiring access target information of the designated port; and restricting access when the access target is the specified data storage area Specify the data save area;

Obtaining second access authentication information;

The computer executable instructions are configured to execute: clearing content of the specified data save area when a predetermined condition is met.

The computer executable instructions are configured to: when the number of times the second access authentication information matches the first access authentication information fails to exceed a preset matching failure threshold, clear the content of the specified data storage area;

and / or,

The computer executable instructions are configured to execute: storing the first access authentication information in the designated data save area.

Further, an integrated circuit chip includes: a processor and a memory for storing a computer program executable on the processor,

Wherein the processor is configured to execute when the computer program is executed:

Setting first access authentication information for the designated data storage area of the memory; acquiring access target information of the designated port; and restricting access to the specified data storage area when the access target is the designated data storage area;

Obtaining second access authentication information;

The processor is configured to execute when the computer program is executed:

Clearing the content of the specified data storage area when the number of times the first access authentication information fails to match the first access authentication information exceeds a preset matching failure number threshold;

and / or,

The processor is configured to execute when the computer program is executed:

The first access authentication information is stored in the designated data storage area.

Industrial applicability

The present application provides a memory data protection method, an integrated circuit chip, and a storage medium. The first access authentication information is set for a specified data storage area of the memory by using software or hardware logic inside the chip; and the access target information of the designated port is obtained. When the access target is the specified data save area, restrict access to the specified data save area; and when the input second access authentication information matches the first access authentication information, permit access to the specified data save area. In this way, only when the input access authentication information is consistent with the access authentication information preset in the specified data storage area, access to the specified data storage area is allowed, memory data protection can be realized, and the system design complexity and cost of the chip are reduced.

Claims

A memory data protection method, the method comprising: setting a first access authentication information for a specified data storage area of the memory; the method further comprising:

Obtaining access target information of the designated port; when the access target is the specified data save area, restricting access to the specified data save area;

Obtaining second access authentication information;

When the second access authentication information matches the first access authentication information, access to the designated data save area is permitted.
The method of claim 1, wherein the method further comprises: clearing the content of the designated data save area when the preset condition is met.
The method of claim 2, wherein when the predetermined condition is met, clearing the content of the specified data save area comprises:

Clearing the content of the specified data storage area when the number of times the first access authentication information fails to match the first access authentication information exceeds a preset matching failure number threshold;

and / or,

When the preset clear command is input, the content of the specified data save area is cleared.
The method of claim 1, wherein the method further comprises storing the first access authentication information in the designated data save area.
An integrated circuit chip, the integrated circuit chip comprising: a setting module and a control module; wherein

The setting module is configured to set first access authentication information for a designated data storage area of the memory;

The control module is configured to acquire access target information of the designated port; when the access target is the specified data save area, restrict access to the designated data save area; acquire second access authentication information; and when the second access authentication information Allow access to the first access authentication information Ask the specified data save area.
The integrated circuit chip of claim 5, wherein the control module is configured to clear content of the designated data save area when the preset condition is met.
The integrated circuit chip according to claim 6, wherein the control module is configured to clear the second access authentication information and the first access authentication information when the number of matching failures exceeds a preset matching failure threshold Specify the contents of the data save area; and/or,

When the preset clear command is input, the content of the specified data save area is cleared.
The integrated circuit chip of claim 5 wherein said setting module is configured to store said first access authentication information in said designated data save area.
A storage medium comprising a set of computer executable instructions configured to perform the steps of the method of any one of claims 1 to 4.
An integrated circuit chip comprising: a processor and a memory for storing a computer program capable of running on the processor,

Wherein the processor is operative to perform the steps of the method of any one of claims 1 to 4 when the computer program is run.