CN113443602B - Wafer level packaging structure of micro-electromechanical system chip and manufacturing process thereof - Google Patents
Wafer level packaging structure of micro-electromechanical system chip and manufacturing process thereof Download PDFInfo
- Publication number
- CN113443602B CN113443602B CN202110613510.6A CN202110613510A CN113443602B CN 113443602 B CN113443602 B CN 113443602B CN 202110613510 A CN202110613510 A CN 202110613510A CN 113443602 B CN113443602 B CN 113443602B
- Authority
- CN
- China
- Prior art keywords
- cover plate
- micro
- silicon
- wafer
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 70
- 239000010703 silicon Substances 0.000 claims description 70
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 68
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 18
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 15
- 229910000679 solder Inorganic materials 0.000 claims description 14
- 238000012858 packaging process Methods 0.000 claims description 13
- 229910052732 germanium Inorganic materials 0.000 claims description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 10
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 9
- -1 aluminum-germanium Chemical compound 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 claims description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 230000004927 fusion Effects 0.000 claims description 4
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 claims description 4
- BLIQUJLAJXRXSG-UHFFFAOYSA-N 1-benzyl-3-(trifluoromethyl)pyrrolidin-1-ium-3-carboxylate Chemical compound C1C(C(=O)O)(C(F)(F)F)CCN1CC1=CC=CC=C1 BLIQUJLAJXRXSG-UHFFFAOYSA-N 0.000 claims description 3
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 3
- 230000006835 compression Effects 0.000 claims description 2
- 238000007906 compression Methods 0.000 claims description 2
- 230000005496 eutectics Effects 0.000 claims description 2
- 239000000843 powder Substances 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 65
- 230000035882 stress Effects 0.000 description 38
- 238000010586 diagram Methods 0.000 description 9
- 239000011257 shell material Substances 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 238000012536 packaging technology Methods 0.000 description 6
- 229910000927 Ge alloy Inorganic materials 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 229920003023 plastic Polymers 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0006—Interconnects
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00277—Processes for packaging MEMS devices for maintaining a controlled atmosphere inside of the cavity containing the MEMS
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/07—Interconnects
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Micromachines (AREA)
Abstract
The present invention relates to the field of wafer level packaging of chips, and more particularly, to wafer level packaging of mems chips susceptible to package stress and related fabrication processes. The wafer-level packaging structure comprises a substrate and a cover plate, wherein the substrate is a micro-electromechanical system chip to be packaged, and a concave part is formed on the cover plate. The cover plate and the base plate are bonded to form a sealed cavity, and the base plate in the cavity is provided with a micro-electromechanical element. The cover plate can be divided into a plurality of mutually insulated elastic electric pins through scribing. The bottom of the electric pin is smaller than the top, and the electric pin is in a mushroom-shaped structure and has the effect of releasing packaging stress. The wafer level package can reduce package stress, thereby improving the performance of the micro-electromechanical system chip. In addition, the wafer-level packaged micro-electromechanical system chip has smaller volume and low packaging cost, meets the requirement of flip-chip ball bonding, and is beneficial to improving the integration level of the micro-electromechanical system.
Description
Technical Field
The present invention relates to wafer level packaging, and more particularly, to a wafer level packaging structure of a mems chip susceptible to package stress and a manufacturing process thereof.
Background
In the integrated circuit chip production process, chip packaging is an important link. Because of the very small feature sizes on the chip, it is difficult for the metal contacts to connect directly with the wires on the circuit board, and it is necessary to establish a connection between the contacts on the chip and the circuit board by packaging techniques. In addition, the chip generally needs to be protected from accidental damage during actual use. The traditional chip packaging technology is to fix single chip which is processed and segmented in advance in a packaging tube shell, electrically connect contacts on the chip with electric pins on the packaging tube shell through a wire bonding technology, and finally pour insulating packaging material or a capping plate into the packaging tube shell for sealing. The common packaging tube shell and packaging materials are plastics, ceramics, metals and the like. With the development of semiconductor manufacturing processes, wafer level packages (Wafer Lever Packaging, WLP) have been developed for improving integration and reducing chip manufacturing costs. The wafer level packaging technology firstly packages a silicon wafer, sets metal solder balls on each contact on the wafer, and finally divides the wafer into single chips. The separated single chip is directly and electrically connected with the circuit board through the flip-chip ball bonding technology, so that a package tube shell and leads and pins thereof are omitted, and parasitic coupling is reduced. Since the chip itself is packaged, this packaging process is also known as chip scale packaging (Chip Scale Package, CSP). Compared with the traditional shell-and-tube packaging, the wafer-level packaging has smaller chip size and lower manufacturing cost, and is more suitable for small mobile application or high-integration system.
In recent years, microelectromechanical systems (Micro-Electro-Mechanical Systems, MEMS) have been widely used in various fields. Micro-electromechanical system chips are provided with micro-scale mechanical structures and electrodes, so that transmission or sensing of signals such as physical signals, sound signals, light signals, magnetic signals and the like can be realized, and various sensors and drivers such as pressure gauges, accelerometers, gyroscopes, microphones, micro mirrors, magnetometers and the like are manufactured. The packaging technology of the mems chip references many of the packaging technologies of the integrated circuit chips, and further requirements are additionally put forward on the basis of the packaging technologies. Because microelectromechanical devices are very fragile and vulnerable to external contaminants or particles, a capping plate seal is typically required for protection. In addition, the gaps between the microstructures in the microelectromechanical component are also on the order of microns, and therefore, any deformation due to package stress can have a significant impact on the performance of the microelectromechanical system. The current package materials for MEMS chip packaging are still based on plastics, ceramics or metals. However, since the mems chip is mostly composed of monocrystalline silicon, mismatch of young's modulus and thermal expansion coefficient between the packaging shell material and the monocrystalline silicon introduces packaging stress, which is often transferred to stress sensitive structures on the mems chip, resulting in reduced chip performance. Besides, the tube shell package has the defects of higher cost and larger package volume. The wafer level packaging technology is also suitable for packaging the micro-electromechanical system chip, and the bonding of the cover plate silicon wafer and the micro-electromechanical system silicon wafer is generally carried out firstly, so that the requirement of wafer level sealing is met, and meanwhile, the problem of mismatch of Young modulus and thermal expansion coefficient between different materials is avoided. Compared with the shell-level package, the wafer-level package has smaller package volume and lower cost. However, if the mems chip of the wafer level package is soldered to the circuit board by flip-chip ball bonding, there is a problem that young's modulus and thermal expansion coefficient are not matched between the circuit board and the chip. Meanwhile, external stress can be transmitted to the micro-electromechanical system chip through the circuit board, so that the micro-electromechanical structure inside is deformed, and the performance of the micro-electromechanical system is greatly affected. Therefore, conventional wafer level packaging techniques are not effective in reducing the impact of package stress on the mems chip.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide the micro-electromechanical system chip packaging method which can release packaging stress, has high integration level, high reliability and low manufacturing cost and is suitable for wafer level packaging.
A wafer level packaging structure of a micro-electromechanical system chip comprises a substrate and a cover plate which are bonded with each other; the cover plate is made of monocrystalline silicon; a concave part is formed on one surface of the cover plate, and a sealed cavity is formed after the concave part is bonded with the substrate; a micro-electromechanical element is arranged on the substrate in the cavity; after the cover plate is bonded with the substrate, a plurality of mutually independent elastic electric pins are separated through scribing, and each elastic electric pin is electrically connected with the micro-electromechanical element on the substrate through ohmic contact.
The invention also has the following accessory features:
the cross-sectional area of one end of the elastic electric pin connected with the micro-electromechanical element is not larger than that of the other end.
One end of the elastic electric pin is provided with a metal solder ball.
The cavity is a vacuum sealed cavity.
The ohmic contact includes: aluminum germanium alloy-silicon ohmic contacts, ohmic contacts formed from other metals or alloys with silicon, and the like.
A microelectromechanical system die wafer level packaging process, the packaging process comprising the steps of:
the method comprises the steps of firstly, aligning a substrate silicon wafer with a micro-electromechanical element which is processed in advance with a cover plate silicon wafer which is processed in advance;
bonding the aligned cover plate silicon wafer and the substrate silicon wafer;
thirdly, forming solder balls on the top surface of the bonded cover plate silicon wafer;
fourthly, dividing the cover plate silicon wafer by scribing to form an elastic electric pin structure;
and fifthly, dividing the bonded silicon wafer by scribing to form a sealed micro-electromechanical system chip which is packaged in a wafer level and has an elastic electric pin structure.
The processing of the cover plate silicon wafer in the packaging process further comprises the following steps:
forming an alignment mark on the top surface of the cover plate silicon wafer through photoetching and etching;
step two, forming a concave part on the bottom surface of the cover plate silicon wafer through photoetching and etching;
thirdly, depositing metal on the top surface of the cover plate silicon wafer;
and fourthly, depositing metal or germanium, preferably germanium, on the bottom surface of the cover plate silicon wafer.
The cover plate silicon wafer and the substrate silicon wafer are bonded by one or more of the following bonding methods: aluminum-germanium bonding, metal bonding, eutectic bonding, solder bonding, glass frit bonding, silicon-silicon direct fusion bonding, or other thermal compression bonding methods.
The etching method is one or more of the following methods: a dry etch or a wet etch, the dry etch comprising: deep reactive ions of silicon, reactive ions, and gaseous xenon difluoride etching and reactive ions of silicon oxide, plasma, and gaseous hydrogen fluoride etching.
The etchant for wet etching the silicon layer is one or a combination of more of the following etchants: potassium hydroxide, tetramethylammonium hydroxide, or ethylenediamine catechol etching solution.
The etchant for wet etching the silicon oxide layer is one or a combination of a plurality of the following etchants: hydrofluoric acid and buffered hydrofluoric acid.
The packaging cover plate of the invention is basically composed of monocrystalline silicon and is consistent with the micro-electromechanical system chip substrate, so that packaging stress caused by mismatch of Young modulus and thermal expansion coefficient can not be generated between the packaging cover plate and the substrate. The cover plate can completely protect the micro-electromechanical elements of the micro-electromechanical system chip in the cavity, and external foreign matters cannot contact the fragile micro-electromechanical elements. The cavity has a sealing function and can provide a stable working environment for the micro-electromechanical element. The elastic electric pin of the packaging structure comprises a conductive silicon column with smaller cross section area and a top cover with larger cross section area, and is in a mushroom-shaped structure. The conductive silicon column with smaller cross-sectional area is electrically connected with the micro-electromechanical element on the substrate through ohmic contact, so that an electric signal can be transmitted from the substrate to the top cover of the electric pin, and the top cover with larger cross-sectional area is enough for accommodating the metal solder balls, so that the micro-electromechanical system chip can be directly electrically connected with the circuit board through the flip-chip ball bonding technology. The wafer level packaging and flip chip ball bonding technology omits packaging leads and pins in the common tube shell level packaging, thereby obviously reducing parasitic coupling affecting the performance of the chip and greatly reducing the packaging volume. Soldering a mems chip to a circuit board by flip-chip ball bonding techniques can create packaging stresses at the soldering sites that, if transmitted to stress sensitive areas of the mems elements on the substrate, can adversely affect the chip performance. The conductive silicon column in the invention plays a role in releasing packaging stress: the conductive silicon column is deformed under the action of the packaging stress, and the packaging stress is completely released in the conductive silicon column structure along with the deformation of the conductive silicon column, so that the stress sensitive area of the micro-electromechanical structure on the substrate is not influenced by the packaging stress. The packaging cover plate provided by the invention has a plurality of structures with different functions, namely the sealing cavity, the conductive silicon column and the ball welding top cover, but the side wall of the sealing cavity and the conductive silicon column structure can be formed by only carrying out one etching process in the processing process. The elastic electric pin formed by the conductive silicon column and the top cover is naturally formed in the process of dividing the single chip after the wafer-level packaging is completed, no extra processing step is needed, the manufacturing process is very simple, and the manufacturing cost is not increased additionally.
Drawings
Fig. 1 is a three-dimensional schematic diagram of a wafer level package mems chip.
Fig. 2 is a three-dimensional schematic perspective view taken along line AA' of fig. 1.
FIG. 3 is a layout diagram of the bottom of the cover plate.
Fig. 4 is a top layout of a substrate.
Fig. 5 is a schematic diagram of a first step and a second step of a manufacturing process of the cover plate.
Fig. 6 is a schematic diagram of a third and fourth steps of the manufacturing process of the cover plate.
Fig. 7 is a schematic diagram of a first step of a wafer level packaging process.
Fig. 8 is a schematic diagram of a second step of the wafer level packaging process.
Fig. 9 is a schematic diagram of a third step of the wafer level packaging process.
Fig. 10 is a schematic diagram of a fourth and fifth step of the wafer level packaging process.
Fig. 11 is a schematic diagram of an operation principle of the elastic electrical pin to release the package stress.
Fig. 12 is a simulation result of elastic electrical pins releasing package stress.
Cover plate 1, substrate 2, elastic electrical pins 3, cavities 4, microelectromechanical element 5, aluminum 6, germanium 7, silicon oxide 8, aluminum-germanium alloy 9, solder balls 10, circuit board 11, alignment marks 12, recesses 13, electrical connection areas 14, and package stress 15.
Detailed Description
The invention will now be described in detail with reference to the following examples and the accompanying drawings, it being pointed out that the examples described are intended only to facilitate an understanding of the invention and are not intended to be limiting in any way.
Referring to fig. 1 and 2, an embodiment of a wafer level package for a micro-electromechanical system chip is provided according to the present invention. In the present embodiment, the cover plate 1 and the base plate 2 are bonded to each other. The cover plate 1 is typically made of monocrystalline silicon. The substrate 2 may be selected from a single crystal silicon wafer, an SOI silicon wafer, and the like according to the final chip structure and the manufacturing process. Wherein, a concave part 13 is formed on one surface of the cover plate 1, and a cavity is formed between the concave part 13 and the substrate 2 after the cover plate 1 is bonded with the substrate 2. And a plurality of microelectromechanical elements 5 are provided on the substrate 2 within the cavity. The cavity is preferably a vacuum sealed cavity, thereby reducing the effects of foreign matter and temperature on the microelectromechanical element 5. The substrate 1 is further provided with a metal polar plate 6, and the metal polar plate 6 is electrically connected with the micro-electromechanical element 5 so as to transmit detection signals. A plurality of independent elastic electrical pins 3 are divided on the cover plate 1. Each elastic electrical pin 3 is independent and electrically insulated from each other. Each elastic electrical pin 3 is electrically connected with a metal polar plate 6 on the substrate 2, and further electrically connected with the micro-electromechanical element 5 through an ohmic contact and an electrical connection area 14. For this reason, it is necessary to use a conductive bonding material for bonding the cover plate 1 and the substrate 2. Preferably, germanium 7 is provided on the bonding surface of the cover plate 1, and an aluminum metal plate 6 is provided on the bonding surface of the substrate 2. When the cover plate 1 and the base plate 2 are bonded, aluminum 6 and germanium 7 form an aluminum-germanium alloy 9 at high temperature, and simultaneously the functions of connecting and conducting the cover plate 1 and the base plate 2 are achieved. The bonding mode adopting the aluminum-germanium alloy has the main advantages that: after heating, the aluminum 6 and the germanium 7 are in a molten state, so that unevenness between bonding surfaces can be overcome, and an airtight bonding effect can be achieved. Meanwhile, the aluminum-germanium alloy 9 has low resistivity, can form ohmic contact with monocrystalline silicon, and can provide an electric path for the micro-electromechanical system chip. Thus, when the cover plate 1 and the substrate 2 are combined together by aluminum-germanium bonding, the cover plate 1 can be electrically connected to the area of the substrate 2 where the aluminum 6 is deposited. In addition, the cover plate 1 is diced to form a plurality of mutually independent elastic electric pins 3, and the tops of the elastic electric pins 3 are provided with aluminum 6 and can be also provided with solder balls 10. Therefore, the electrical signal detected by the micro-electromechanical system chip can be directly transmitted to the top surface of the cover plate through the elastic electrical pin 3 and is electrically connected with the circuit board 11 through flip-chip ball bonding, and no lead is needed, so that parasitic coupling is effectively reduced and the packaging volume is greatly reduced. Fig. 3 shows the layout design of the cover plate 1, in which the white parts will be formed by an etching process to form recesses 13, while the non-etched bonding parts deposit germanium 7. Correspondingly, fig. 4 shows a layout design of the substrate 2, in which the portion deposited with the metal aluminum 6 is bonded to the portion deposited with the germanium 7 on the cover plate 1 to form an aluminum-germanium alloy 9 and to integrate the cover plate 1 with the substrate 2 when performing the die bonding process.
Furthermore, in flip-chip ball bonding packages, the mems chip is bonded to the circuit board 11 by flip-chip bonding techniques, and the circuit board 11 is typically made of plastic or ceramic. Due to the mismatch of Young's modulus and thermal expansion coefficient between the plastic or ceramic and the silicon material of the MEMS chip, the packaging stress generated by external force or temperature change can be directly transferred to the MEMS chip, thereby affecting the accuracy of the MEMS element. In contrast, the elastic electrical leads 3 of the present invention are made of silicon, and are elastically deformed when being stressed, thereby releasing the package stress. Furthermore, it is preferable that the area of the cross section of the connection end of the elastic electrical pin 3 and the substrate 1 is not larger than the area of the cross section of the connection end of the elastic electrical pin 4 and the circuit board 11. As shown in fig. 11, the package stress 15 generated by the external force or the temperature change is applied to the elastic electrical pins 3 to deform, and along with the deformation of the elastic electrical pins 3 due to the stress, the package stress distributed on the elastic electrical pins 3 gradually decreases along the vertical direction until most of the package stress is released when the surface of the substrate 2 is reached, so that the influence of the package stress on the stress sensitive area of the mems chip is avoided, and the measurement accuracy of the chip is improved. FIG. 12 is a simulation result of the wafer level package MEMS chip subjected to package stress using the present invention, showing the magnitude of the package stress applied to the center of the substrate 2 when the elastic electrical leads 3 of the MEMS chip are subjected to 250 megapascals package stress. Wherein the abscissa is the side length of the cross section of the elastic electric pin 3, namely the thickness of the elastic electric pin 3; the ordinate is the magnitude of the package stress in the center of the substrate 2. It can be seen that when the side length of the cross section of the spring electric pin 3 is smaller than 100 micrometers, the deformation of the spring electric pin 3 is enough to release the package stress, so that the package stress of the stress sensitive area in the center of the substrate 2 is approximately equal to zero. The simulation result shows that the elastic electric pin 3 can effectively eliminate the influence of the packaging stress on the stress sensitive area of the substrate 2, and the detection precision of the whole chip is improved.
Next, a process of manufacturing the wafer level package will be further described with reference to fig. 7 to 10. The manufacturing steps comprise:
in a first step, the substrate silicon wafer 2 with the micro electromechanical elements pre-processed and the cover plate silicon wafer 1 pre-processed are aligned by the alignment mark 12.
And secondly, bonding the substrate silicon wafer 2 and the cover plate silicon wafer 1 to form a sealed cavity 4. The bonding technique may be one or more of the following: bonding of silicon wafers is performed by aluminum-germanium bonding, metal bonding, solder bonding, glass frit bonding, silicon-silicon direct fusion bonding, or other thermocompression bonding methods.
Third, solder balls 10 are formed on top of the bonded cover silicon wafer 1.
Fourth, the cover plate silicon wafer 1 is divided by dicing to form a plurality of independent elastic electric pin structures.
Fifthly, dividing the bonded silicon wafer into a whole by scribing, wherein the whole comprises a cover plate and a base plate; thereby forming a hermetically sealed, wafer level packaged mems chip with the spring motor pins 3.
The wafer level packaging method in fig. 7 to 10 further includes a pre-processing of the cover silicon wafer 1, and referring to fig. 5 and 6, the processing steps include:
first, the top surface of the cover silicon wafer 1 is subjected to photolithography, and then, the alignment mark 12 is formed on the top surface of the cover silicon wafer 1 by deep reactive ion etching or other dry or wet etching.
And secondly, photoetching the bottom surface of the cover plate silicon wafer 1, and then forming a concave part 13 on the bottom surface of the cover plate silicon wafer 1 by deep reactive ion etching or other dry or wet etching.
In a third step, a metal, preferably aluminum 6, is deposited on the top surface of the cap silicon wafer 1.
In a fourth step, a bonding material, preferably germanium 7, is deposited on the bottom surface of the cap silicon wafer 1.
The etching method is one or more of the following methods: a dry etch or a wet etch, the dry etch comprising: deep reactive ions of silicon, reactive ions, and gaseous xenon difluoride etching and reactive ions of silicon oxide, plasma, and gaseous hydrogen fluoride etching.
The etchant for wet etching the silicon layer is one or a combination of more of the following etchants: potassium hydroxide, tetramethylammonium hydroxide, or ethylenediamine catechol etching solution.
The etchant for wet etching the silicon oxide layer is hydrofluoric acid or buffered hydrofluoric acid.
The package cover plate of the invention is basically composed of monocrystalline silicon as most MEMS chips, so that package stress generated by Young's modulus or thermal expansion coefficient mismatch is not introduced. The concave part of the cover plate is bonded with the base plate to form a sealed cavity, so that effective protection can be provided for the micro-electromechanical elements on the micro-electromechanical system chip. After the wafer level packaging is completed, a plurality of independent elastic electric pins 3 can be formed on the chips simultaneously in the single chip dividing process, and each elastic electric pin 3 is composed of a thin conductive silicon column and a top cover with a large area and is in a mushroom-shaped structure. The electrical conductivity of silicon is utilized by the elasto-electrical pins 3, which can directly transmit the electrical signals of the mems chip to the solder balls 10 disposed on the top cap of the elasto-electrical pins 3, so that advanced chip packaging techniques such as flip-chip ball bonding are possible, such that the wafer-level packaged mems of the present invention is much smaller in size than conventional package mems. Meanwhile, in the packaging process, the elastic electric pins 3 can release most of packaging stress through deformation, so that the influence of the packaging stress on the micro-electromechanical elements on the micro-electromechanical system chip, which are sensitive to the stress, is reduced, and the accuracy of the chip is further improved.
Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the scope of the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention.
Claims (10)
1. A wafer level packaging structure of a micro-electromechanical system chip comprises a substrate and a cover plate which are bonded with each other; the method is characterized in that: the cover plate is made of monocrystalline silicon; a concave part is formed on one surface of the cover plate, and a sealed cavity is formed after the concave part is bonded with the substrate; a micro-electromechanical element is arranged on the substrate in the cavity; the cover plate is divided into a plurality of mutually independent elastic electric pins through scribing, and each elastic electric pin is electrically connected with the micro-electromechanical element on the substrate through ohmic contact; the elastic electric pin consists of a thin conductive silicon column and a top cover with a larger area, and the cross section area of one end of the elastic electric pin connected with the micro-electromechanical element is smaller than that of the other end.
2. The package structure of claim 1, wherein: one end of the elastic electric pin is provided with a metal solder ball.
3. The package structure of claim 1, wherein the cavity is a vacuum sealed cavity.
4. The package structure of claim 1, wherein the ohmic contact comprises: aluminum-germanium ohmic contacts, aluminum-germanium alloy-silicon ohmic contacts, gold-Jin Oum contacts, silicon-silicon fusion bonding contacts, and solder contacts.
5. A wafer level packaging process for a micro-electro-mechanical system chip, which is characterized in that: the packaging process is used for packaging the wafer-level packaging structure of the micro-electromechanical system chip of any one of claims 1 to 4, and comprises the following steps:
the method comprises the steps of firstly, aligning a substrate silicon wafer with a micro-electromechanical element which is processed in advance with a cover plate silicon wafer which is processed in advance;
bonding the aligned cover plate silicon wafer and the substrate silicon wafer;
thirdly, forming solder balls on the top surface of the bonded cover plate silicon wafer;
fourthly, dividing the cover plate silicon wafer by scribing to form an elastic electric pin structure;
and fifthly, dividing the bonded silicon wafer by scribing to form a sealed micro-electromechanical system chip which is packaged in a wafer level and has an elastic electric pin structure.
6. The mems chip wafer level packaging process of claim 5, wherein: the processing of the cover plate silicon wafer further comprises the following steps:
forming an alignment mark on the top surface of the cover plate silicon wafer through photoetching and etching;
step two, forming a concave part on the bottom surface of the cover plate silicon wafer through photoetching and etching;
thirdly, depositing metal on the top surface of the cover plate silicon wafer;
and fourthly, depositing metal or germanium on the bottom surface of the cover plate silicon wafer.
7. The mems chip wafer level packaging process of claim 5, wherein: the cover plate silicon wafer and the substrate silicon wafer are bonded by one or more of the following bonding methods: the bonding of the silicon wafer is performed by an aluminum-germanium bonding, a metal bonding, a eutectic bonding, a solder bonding, a glass powder bonding, a silicon-silicon direct fusion bonding, or a thermal compression bonding method.
8. The manufacturing process as set forth in claim 6, wherein: the etching method is one or more of the following methods: a dry etch or a wet etch, the dry etch comprising: deep reactive ions of silicon, reactive ions, and gaseous xenon difluoride etching and reactive ions of silicon oxide, plasma, and gaseous hydrogen fluoride etching.
9. The manufacturing process as set forth in claim 6, wherein: the etchant for wet etching the silicon layer is one or a combination of more of the following etchants: potassium hydroxide, tetramethylammonium hydroxide, or ethylenediamine catechol etching solution.
10. The manufacturing process as set forth in claim 6, characterized in that: the etchant for wet etching the silicon oxide layer is one or a combination of a plurality of the following etchants: hydrofluoric acid and buffered hydrofluoric acid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110613510.6A CN113443602B (en) | 2021-06-02 | 2021-06-02 | Wafer level packaging structure of micro-electromechanical system chip and manufacturing process thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110613510.6A CN113443602B (en) | 2021-06-02 | 2021-06-02 | Wafer level packaging structure of micro-electromechanical system chip and manufacturing process thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113443602A CN113443602A (en) | 2021-09-28 |
| CN113443602B true CN113443602B (en) | 2023-12-08 |
Family
ID=77810703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110613510.6A Active CN113443602B (en) | 2021-06-02 | 2021-06-02 | Wafer level packaging structure of micro-electromechanical system chip and manufacturing process thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113443602B (en) |
Citations (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239497B1 (en) * | 1997-07-23 | 2001-05-29 | Nec Corporation | Substrate for packing semiconductor device and method for packing a semiconductor device in the substrate |
| WO2001057920A1 (en) * | 2000-02-01 | 2001-08-09 | Analog Devices, Inc. | Process for wafer level treatment to reduce stiction and passivate micromachined surfaces and compounds used therefor |
| WO2006097779A1 (en) * | 2005-03-16 | 2006-09-21 | Infineon Technologies Ag | Substrate, electronic component, electronic configuration and methods of producing the same |
| WO2010028884A2 (en) * | 2008-09-15 | 2010-03-18 | Robert Bosch Gmbh | Encapsulation, mems and encapsulation method |
| CN103523745A (en) * | 2013-10-21 | 2014-01-22 | 安徽北方芯动联科微系统技术有限公司 | Si conductive post based wafer-level packaging method and monolithic integrated MEMS (Micro Electro Mechanical System) chip for same |
| CN104009014A (en) * | 2014-04-26 | 2014-08-27 | 华进半导体封装先导技术研发中心有限公司 | Integrated passive device wafer-level packaging three-dimensional stacked structure and manufacturing method |
| FR3008690A1 (en) * | 2013-07-22 | 2015-01-23 | Commissariat Energie Atomique | DEVICE COMPRISING A FLUID CHANNEL PROVIDED WITH AT LEAST ONE MICRO OR NANOELECTRONIC SYSTEM AND METHOD OF MAKING SUCH A DEVICE |
| CN104392958A (en) * | 2014-11-23 | 2015-03-04 | 北京工业大学 | Semiconductor packaging method of wafer level silicon-based through hole |
| CN104795338A (en) * | 2015-04-13 | 2015-07-22 | 华进半导体封装先导技术研发中心有限公司 | Wafer-level low-cost packaging process and structure of backside-illuminated image chip |
| CN105277741A (en) * | 2014-07-16 | 2016-01-27 | 中国科学院地质与地球物理研究所 | Transverse MEMS acceleration sensitive chip and manufacturing process thereof |
| CN105668501A (en) * | 2016-01-28 | 2016-06-15 | 安徽北方芯动联科微系统技术有限公司 | Chip scale packaged MEMS (Micro-Electro-Mechanical Systems) chip with multifunctional cover board and manufacturing method of chip scale packaged MEMS chip with multifunctional cover board |
| CN205335241U (en) * | 2016-01-11 | 2016-06-22 | 华天科技（昆山）电子有限公司 | Low -cost wafer level chip size silicon through -hole interconnect structure |
| CN106124117A (en) * | 2016-06-14 | 2016-11-16 | 中国科学院地质与地球物理研究所 | A kind of double cavity pressure meter chip and manufacturing process thereof |
| CN107785278A (en) * | 2016-08-26 | 2018-03-09 | 上海微联传感科技有限公司 | The MEMS crystal oscillators and preparation method of a kind of wafer-level vacuum packaged |
| CN108267262A (en) * | 2016-12-30 | 2018-07-10 | 中国空气动力研究与发展中心超高速空气动力研究所 | A kind of temperature self-compensation semiconductor pressure resistance strain gauge |
| CN207973508U (en) * | 2017-12-29 | 2018-10-16 | 中芯长电半导体（江阴）有限公司 | A kind of MEMS wafer class encapsulation structure |
| CN109216301A (en) * | 2018-09-17 | 2019-01-15 | 中芯集成电路（宁波）有限公司 | Phase-change heat chip structure and preparation method thereof |
| CN109286385A (en) * | 2018-09-13 | 2019-01-29 | 中国电子科技集团公司第二十六研究所 | A kind of SAW device wafer level packaging structure and its packaging method |
| CN110729979A (en) * | 2019-09-30 | 2020-01-24 | 中国电子科技集团公司第二十六研究所 | Wafer-level packaging method and structure of film bulk acoustic wave filter |
| CN211004545U (en) * | 2019-11-18 | 2020-07-14 | 安徽北方芯动联科微系统技术有限公司 | MEMS chip with TSV structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7351609B2 (en) * | 2006-03-22 | 2008-04-01 | National Taiwan University | Method for wafer level package of sensor chip |
| US20160229684A1 (en) * | 2013-09-24 | 2016-08-11 | Motion Engine Inc. | Mems device including support structure and method of manufacturing |
-
2021
- 2021-06-02 CN CN202110613510.6A patent/CN113443602B/en active Active
Patent Citations (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239497B1 (en) * | 1997-07-23 | 2001-05-29 | Nec Corporation | Substrate for packing semiconductor device and method for packing a semiconductor device in the substrate |
| WO2001057920A1 (en) * | 2000-02-01 | 2001-08-09 | Analog Devices, Inc. | Process for wafer level treatment to reduce stiction and passivate micromachined surfaces and compounds used therefor |
| WO2006097779A1 (en) * | 2005-03-16 | 2006-09-21 | Infineon Technologies Ag | Substrate, electronic component, electronic configuration and methods of producing the same |
| WO2010028884A2 (en) * | 2008-09-15 | 2010-03-18 | Robert Bosch Gmbh | Encapsulation, mems and encapsulation method |
| FR3008690A1 (en) * | 2013-07-22 | 2015-01-23 | Commissariat Energie Atomique | DEVICE COMPRISING A FLUID CHANNEL PROVIDED WITH AT LEAST ONE MICRO OR NANOELECTRONIC SYSTEM AND METHOD OF MAKING SUCH A DEVICE |
| CN103523745A (en) * | 2013-10-21 | 2014-01-22 | 安徽北方芯动联科微系统技术有限公司 | Si conductive post based wafer-level packaging method and monolithic integrated MEMS (Micro Electro Mechanical System) chip for same |
| CN104009014A (en) * | 2014-04-26 | 2014-08-27 | 华进半导体封装先导技术研发中心有限公司 | Integrated passive device wafer-level packaging three-dimensional stacked structure and manufacturing method |
| CN105277741A (en) * | 2014-07-16 | 2016-01-27 | 中国科学院地质与地球物理研究所 | Transverse MEMS acceleration sensitive chip and manufacturing process thereof |
| CN104392958A (en) * | 2014-11-23 | 2015-03-04 | 北京工业大学 | Semiconductor packaging method of wafer level silicon-based through hole |
| CN104795338A (en) * | 2015-04-13 | 2015-07-22 | 华进半导体封装先导技术研发中心有限公司 | Wafer-level low-cost packaging process and structure of backside-illuminated image chip |
| CN205335241U (en) * | 2016-01-11 | 2016-06-22 | 华天科技（昆山）电子有限公司 | Low -cost wafer level chip size silicon through -hole interconnect structure |
| CN105668501A (en) * | 2016-01-28 | 2016-06-15 | 安徽北方芯动联科微系统技术有限公司 | Chip scale packaged MEMS (Micro-Electro-Mechanical Systems) chip with multifunctional cover board and manufacturing method of chip scale packaged MEMS chip with multifunctional cover board |
| CN106124117A (en) * | 2016-06-14 | 2016-11-16 | 中国科学院地质与地球物理研究所 | A kind of double cavity pressure meter chip and manufacturing process thereof |
| CN107785278A (en) * | 2016-08-26 | 2018-03-09 | 上海微联传感科技有限公司 | The MEMS crystal oscillators and preparation method of a kind of wafer-level vacuum packaged |
| CN108267262A (en) * | 2016-12-30 | 2018-07-10 | 中国空气动力研究与发展中心超高速空气动力研究所 | A kind of temperature self-compensation semiconductor pressure resistance strain gauge |
| CN207973508U (en) * | 2017-12-29 | 2018-10-16 | 中芯长电半导体（江阴）有限公司 | A kind of MEMS wafer class encapsulation structure |
| CN109286385A (en) * | 2018-09-13 | 2019-01-29 | 中国电子科技集团公司第二十六研究所 | A kind of SAW device wafer level packaging structure and its packaging method |
| CN109216301A (en) * | 2018-09-17 | 2019-01-15 | 中芯集成电路（宁波）有限公司 | Phase-change heat chip structure and preparation method thereof |
| CN110729979A (en) * | 2019-09-30 | 2020-01-24 | 中国电子科技集团公司第二十六研究所 | Wafer-level packaging method and structure of film bulk acoustic wave filter |
| CN211004545U (en) * | 2019-11-18 | 2020-07-14 | 安徽北方芯动联科微系统技术有限公司 | MEMS chip with TSV structure |
Non-Patent Citations (2)
| Title |
|---|
| BGA封装技术;杨兵,刘颖;电子与封装(第04期);全文 * |
| 杨兵,刘颖.BGA封装技术.电子与封装.2003,(第04期),全文. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113443602A (en) | 2021-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4548793B2 (en) | Semiconductor sensor device and manufacturing method thereof | |
| US9046546B2 (en) | Sensor device and related fabrication methods | |
| US8215176B2 (en) | Pressure sensor for harsh media sensing and flexible packaging | |
| US8089144B2 (en) | Semiconductor device and method for manufacturing the same | |
| US8084332B2 (en) | Method of fabrication of AI/GE bonding in a wafer packaging environment and a product produced therefrom | |
| TWI409885B (en) | Package structure having micromechanical element and method of making same | |
| EP2481703B1 (en) | Sensor protection | |
| TWI571428B (en) | Ic and method for manufacturing ic of sensor device | |
| EP2684837B1 (en) | Wafer level sensor package and method of forming same | |
| EP1167281A2 (en) | Chip scale surface-mountable packaging method for electronic and MEMS devices | |
| TWI417973B (en) | Method for forming package structure having mems component | |
| JP2011106955A (en) | Acceleration sensor and method of fabricating acceleration sensor | |
| US20110221455A1 (en) | Micromechanical component and method for its production | |
| JP2008132587A (en) | Method of manufacturing wafer-level vacuum packaged device | |
| US8288850B2 (en) | Method for packaging micromachined devices | |
| JP2009241164A (en) | Semiconductor sensor apparatus and manufacturing method therefor | |
| US9073750B2 (en) | Manufacturing method of micro-electro-mechanical system device and micro-electro-mechanical system device made thereby | |
| CN108751119B (en) | MEMS chip with stress buffer structure and manufacturing method thereof | |
| US20160152466A1 (en) | Micromechanical sensor device and corresponding manufacturing method | |
| US11161734B2 (en) | MEMS assembly and manufacturing method thereof | |
| US8866241B2 (en) | Pressure sensing device having contacts opposite a membrane | |
| CN113443602B (en) | Wafer level packaging structure of micro-electromechanical system chip and manufacturing process thereof | |
| CN210084937U (en) | Back hole lead wire type pressure sensor | |
| Chanchani et al. | A new wafer-level packaging technology for MEMS with hermetic micro-environment | |
| US20100320595A1 (en) | Hybrid hermetic interface chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |