CN109216301A - Phase-change heat chip structure and preparation method thereof - Google Patents
Phase-change heat chip structure and preparation method thereof Download PDFInfo
- Publication number
- CN109216301A CN109216301A CN201811081424.XA CN201811081424A CN109216301A CN 109216301 A CN109216301 A CN 109216301A CN 201811081424 A CN201811081424 A CN 201811081424A CN 109216301 A CN109216301 A CN 109216301A
- Authority
- CN
- China
- Prior art keywords
- wafer
- phase
- cover board
- chip
- cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/427—Cooling by change of state, e.g. use of heat pipes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/427—Cooling by change of state, e.g. use of heat pipes
- H01L23/4275—Cooling by change of state, e.g. use of heat pipes by melting or evaporation of solids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
A kind of phase-change heat chip structure and preparation method thereof, phase-change heat chip structure includes: cover board and chip；The lower surface of cover board is bonded with the back side of chip, and the lower surface of cover board is provided with cavity, and the back side of chip is provided with empty slot, and cavity is connected to empty slot, has phase-change material in cavity or empty slot；Phase-change material fills full cavity or empty slot, heat absorption becomes liquid or gaseous state, volume expansion, the phase-change material of volume expansion will generate pressure to chip and cover board, and then influence the reliability of chip, the cavity of cover board provides the space of phase-change material storage after volume expansion, reduces the stress between chip and cover board, improves the reliability of chip.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly, to a kind of phase-change heat chip structure and its single-chip
Wafer scale preparation method and wafer scale system encapsulate preparation method.
Background technique
Chip heat pipe reason mode is divided into active heat removal and passive heat dissipation, and passive heat dissipation includes: heat transfer (heat sink)；Actively dissipate
Heat includes: phase-change heat, liquid metal heat radiation, microchannel heat dissipation, thermoelectric radiating, air blast cooling；In power semiconductor, with list
The reduction of chips size, the raising of power, the unit heat flux generated therewith increase sharply.
In three-dimension packaging, with the integrated stacking of various chips, a large amount of heat is accumulated in packaging body.Traditionally, lead to
The heat sink air blast cooling for carrying out chip is crossed, the 60% of generated waste heat, and the power consumption that air-cooled needs are additional can only at most be discharged,
There are noises.
Phase-change heat technology is to discharge the technology of latent heat of phase change using substance phase-state change.Experimental data shows, phase transformation side
Formula is higher by several times or even dozens of times than the ability that the simple temperature difference radiates.Phase-change material can be stored in phase transition process or be discharged big
The heat of amount, and phase transition process approximation isothermal can carry out effective overheating protection to chip.Simultaneously have it is small in size, light-weight,
Reliable performance, economy and the advantages that do not consume energy.
Chip generates heat during the work time, and the phase-change material at close chip fever end is by solid-state in chip back cavity
Become liquid or steam state is become by liquid, absorb heat, solid-state is become by liquid close to the phase-change material of cover board cold end or by vapour
State becomes liquid, discharges heat, forms a heat conductive circulation.And so on constantly, the active heat removal process of chip is completed, height is led
Hot phase-change material plays the role of heat transfer, to rapidly realize the purpose to radiate to IC chip, has
Effect improves the speed of service and effect, improves operational reliability, prolongs the service life.
In the prior art, phase-change material is filled up in chip back, phase-change material, which is undergone phase transition, causes volume expansion, leads to core
Piece generates stress, easily causes the integrity problem of chip, and radiate using phase-change material, how to make to absorb heat hair
Heat release is quickly key points and difficulties by the material of raw phase transformation.
Summary of the invention
The purpose of the present invention is undergoing phase transition expansion for the filling phase-change material in chip in the prior art, it is easy to cause
Chip generates stress, and undergoes phase transition the problems such as how material of expansion quickly discharges heat, provides a kind of phase-change heat
Chip structure and preparation method thereof, the material for undergoing phase transition absorption heat quickly discharge heat, and chip interior is avoided to generate
Stress improves the reliability of chip.
To achieve the goals above, a kind of phase-change heat chip structure, including cover board and chip are proposed:
The lower surface of the cover board is bonded with the back side of the chip, and the lower surface of the cover board is provided with cavity, described
The back side of chip is provided with empty slot, and the cavity is connected to the empty slot, has phase-change material in the cavity or empty slot.
It optionally, further include heat sink, the heat sink upper surface for being set to the cover board.
Optionally, it is described it is heat sink between the upper surface of the cover board be equipped with heat transfer medium.
It optionally, further include conductive bump, the conductive bump is mounted on the front of the chip.
Optionally, the width of the cavity is greater than or equal to the width of the empty slot.
Optionally, the cavity is made of multiple cavities.
Optionally, the diameter in the cavity is greater than 1um.
Optionally, the cover board is made of bonding wafer.
Optionally, the cover board is equipped with solder with the place of bonding of the chip.
According to an aspect of the present invention, according to phase-change heat chip structure, a kind of wafer scale of phase-change heat chip is proposed
Preparation method, comprising:
One wafer is provided, to the back-etching of the wafer, forms multiple empty slots, and the depth of the empty slot is not touched
Close to the deep-well region of the wafer；
One cover board identical with the wafer size is provided, the lower surface of the cover board is etched, a plurality of cavities are formed；
Phase-change material is placed in the empty slot or cavity；
The cavity is corresponding with the position of the empty slot, and the lower surface of the cover board is bonded with the back side of the wafer.
Optionally, further includes: heat transfer medium is set in the upper surface of the cover board, heat is set on the heat transfer medium
It is heavy.
Optionally, before heat transfer medium is arranged in the upper surface of the cover board, further includes: to the upper surface of the cover board into
Row is thinned.
Optionally, to the back-etching of the wafer, formed before multiple empty slots, further includes: to the backside of wafer into
Row is thinned.
Optionally, further includes: in the front attachment conductive bump of the wafer.
Optionally, the structure of para-linkage is cut, to obtain multiple phase-change heat chip structures.
Optionally, the cavity is made of the cavity of multiple etchings.
Optionally, the phase-change material is set in empty slot or cavity by low speed spin coating mode.
Optionally, further includes: the hot spot region of the wafer is exposed.
Optionally, the empty slot is covered in the hot spot region.
Optionally, the etching is that plasma reaction etches.
According to another aspect of the invention, it is proposed that a kind of phase-change heat wafer scale system encapsulates preparation method, comprising:
One the first wafer and multiple bare dies are provided, inter-level dielectric is set at the back side of the first wafer, it is more by separately
A bare die front pastes the back side of first wafer；
To the back-etching of each bare die, empty slot is formed；
By molding material injection molding be its lower surface have a plurality of cavities structure the second wafer, the cavity with it is described
The position of empty slot is corresponding；
The lower surface of second wafer is bonded with the back side of the multiple bare die；
It in the front of first wafer, is performed etching with the weld pad corresponding position of the bare die, etching is deep to described the
One wafer exposes the weld pad of the bare die, forms through-hole；
It fills conductive material in the through-hole, forms conductive plunger, be electrically connected with realizing with the bare die.
Optionally, after multiple bare die fronts separately are pasted the back side of the first wafer, to each described naked
The back-etching of piece is formed before empty slot, further includes: to the gap mould filling between the bare die and bare die, forms covering
The plastic packaging layer of the side wall of the bare die and the inter-level dielectric.
Optionally, it is also wrapped before being performed etching with the weld pad corresponding position of the bare die in the front of first wafer
It includes: the front of first wafer being carried out to be thinned or remove first wafer.Optionally, it is filled in the through-hole conductive
Material is formed after conductive plunger, further includes: setting reroutes layer on the conductive plunger.
Optionally, further includes: dress patch conductive bump, the conduction on the conductive plunger or on the rewiring layer
Convex block is electrically connected with the bare die.
Optionally, further includes: heat transfer medium is set in the upper surface of second wafer, is arranged on the heat transfer medium
It is heat sink.
Optionally, before heat transfer medium is arranged in the upper surface of second wafer, further includes: to second wafer
Upper surface carries out thinned.
Optionally, the cavity is made of the cavity of multiple etchings.
Optionally, the phase-change material is set in empty slot or cavity by low speed spin coating mode.
Optionally, after the completion of phase-change heat wafer scale system encapsulation, being divided into several bare dies is one group multiple
Module, each module form a system for being capable of providing multiple functions.
The beneficial effects of the present invention are:
1, cavity is set in the lower surface of cover board, the back side of chip is provided with empty slot, and phase-change material fills full cavity or sky
In slot, when phase-change material heat absorption is undergone phase transition, heat is discharged, when volume expansion, is connected to by cavity with empty slot, increases phase transformation
The expandable space of material reduces the pressure after phase-change material expands to chip and cover board, improves the reliability of chip.
2, phase-change heat wafer scale system of the invention encapsulates preparation method, the method that wafer-level packaging and system are encapsulated
It combines, empty slot is formed to the multiple bare die back-etchings pasted on the first wafer inter-level dielectric, molding material is molded into
Type is the second wafer that its lower surface has a plurality of cavities structure, and cavity is corresponding with the position of empty slot, sets in cavity or empty slot
Phase-change material is set, the lower surface of the second wafer is bonded with the back side of multiple bare dies, is led in the weld pad corresponding position formation of bare die
Electric plug realizes the electric connection of bare die, and integrated multiple groups chip will be encapsulated on wafer, can reduce the area of encapsulating structure, can
To improve the radiating efficiency of wafer scale system packaging structure, optimize the electrical property of chip, reduces manufacturing cost.
The device of the invention has other characteristics and advantages, these characteristics and advantages from the attached drawing being incorporated herein and with
It will be apparent in specific embodiment afterwards, or will be in the attached drawing and subsequent specific embodiment being incorporated herein
Middle to be stated in detail, the drawings and the detailed description together serve to explain specific principles of the invention.
Detailed description of the invention
Exemplary embodiment of the present is described in more detail in conjunction with the accompanying drawings, of the invention is above-mentioned and other
Purpose, feature and advantage will be apparent, wherein in exemplary embodiments of the present invention, identical appended drawing reference is usual
Represent same parts.
Fig. 1 phase-change heat chip structure according to an embodiment of the invention.
A kind of Fig. 2 phase-change heat chip structure according to an embodiment of the invention.
Fig. 3 another phase-change heat chip structure according to an embodiment of the invention.
The flow chart of Fig. 4 phase-change heat wafer scale preparation method according to an embodiment of the invention.
Fig. 5 (A)~Fig. 5 (F) is in phase-change heat wafer scale preparation process according to an embodiment of the invention respectively
Different phase structural schematic diagram.
The flow chart of Fig. 6 phase-change heat wafer scale system encapsulation preparation method according to an embodiment of the invention.
Fig. 7 (A)~Fig. 7 (L) is phase-change heat wafer scale SIP preparation process according to an embodiment of the invention respectively
In different phase structural schematic diagram.
Specific embodiment
The present invention will be described in more detail below with reference to accompanying drawings.Although showing the preferred embodiment of the present invention in attached drawing,
However, it is to be appreciated that may be realized in various forms the present invention and should not be limited by the embodiments set forth herein.On the contrary, providing
These embodiments are of the invention more thorough and complete in order to make, and can will fully convey the scope of the invention to ability
The technical staff in domain.
According to an embodiment of the present invention, a kind of phase-change heat chip structure, including cover board and chip are provided:
Referring to Fig.1, the lower surface of cover board 5 is bonded with the back side of chip 6, and the lower surface of cover board 5 is provided with cavity 7, chip 6
The back side be provided with empty slot 8, cavity 7 is connected to empty slot 8, has phase-change material in cavity 7 or empty slot 8.
Improvement direction main for phase-change heat is the heat-transfer capability for improving phase-change material at this stage, according to phase transition temperature
Point, selects suitable phase-change material, and phase-change material, which absorbs, solid-state occurs after heat to liquid transformation or liquid to gaseous transformation,
To maintain the slow heating of chip.
Solid phase change material fills full cavity 7 or empty slot 8, and heat absorption becomes liquid, volume expansion, if cover board 5 is without cavity, shape
Pressure will be generated to chip 6 and cover board 5 at the phase-change material of liquid, and then influence the reliability of chip.If phase-change material becomes
After gaseous state, also equally exists and pressure is led to the problem of to chip 6 and cover board 5.After the cavity 7 of cover board 5 provides volume expansion
The space of phase-change material storage, reduces the stress between chip 6 and cover board 5, improves the reliability of chip.
Specifically, phase-change material has inorganic aqueous salt, inorganic matter, organic matter, inorganic composite materials etc..Wherein, positive two
Ten 50 degrees Celsius of alkane upper limit temperature controls；Paraffin melting point and electronic device operating temperature are close；Paraffin composite material is to add in paraffin
Highly heat-conductive material.
Optionally, further include heat sink 9, heat sink 9 being set to the upper surface of cover board 5, heat sink 9 with the upper table of cover board 5
Heat transfer medium is equipped between face.
Optionally, heat transfer medium is the epoxide-resin glue with silver ion.
Specifically, the upper end of cover board 5 is cold end, is sequentially prepared interface heat transfer medium and heat sink 9 in the upper surface of cover board 5,
Phase-change material and extraneous heat exchange are promoted, realizes that phase-change material efficiently radiates.
It optionally, further include conductive bump 11, conductive bump 11 is mounted on the front of chip 6.
Optionally, the width of cavity 7 can be greater than or equal to the width of empty slot 8, referring to Fig. 2.
Specifically, the width of cavity 7 is greater than 8 width of empty slot, therefore reduces the precision that wafer is bonded with cover board 5 and want
Ask, cavity 7 with heat sink 9 heat exchange area it is bigger, phase-change material and extraneous heat-exchange capacity after improving state transformation.
Specifically, according to actual chips size, the edge of cavity 7 and the border 1um or more of empty slot 8.
Optionally, cavity 7 is made of multiple cavities, referring to Fig. 3.
Specifically, multiple cavities can be uniformly distributed, and can also be divided at random in the big Density Distribution in hot spot concentration zones or other regions
Cloth.
Specifically, the depth in multiple cavities can be consistent, can also be different, such as the empty depth of hot spot concentration zones can be with
It is deep, the diameter in cavity can be determined according to the requirement of the size of chip and radiating efficiency.
Optionally, empty diameter is greater than 1um.
Optionally, cover board 5 can be fabricated by silicon, germanium, ceramics, glass, metal or organic material etc..
A kind of embodiment according to the present invention proposes a kind of phase-change heat chip according to phase-change heat chip structure
Wafer scale preparation method, includes the following steps:
Step 1: a wafer 201 is provided, to the back-etching of wafer 201, forms multiple empty slots 203, and empty slot 203
Depth is not touched close to the deep-well region of wafer 201, referring to Fig. 5 (A)；
Optionally, it to the back-etching of wafer 201, is formed before multiple empty slots 203, further includes: to wafer 201
The back side carries out being thinned to predetermined thickness.
Photoetching is carried out to the back side of wafer 201；Using patterned mask layer as exposure mask, mask layer may include: hard exposure mask
Material and photoresist mask material.Figure on mask plate, is scribed processed crystalline substance by the hot spot region exposure to wafer 201
201 surfaces of circle, then etch wafer 201 by dry or wet etch technique.
Specifically, plasma dry etch process can be used in etching, and generating containing chlorine or fluoro-gas electric discharge has chemistry
Active plasma etching gas, etching gas contain a large amount of living radical, these active groups deposit to exposed crystalline substance
It when on circle 201, is combined with silicon atom and forms volatile silicon chloride or silicon fluoride molecule, so that the figure of photoresist be turned
It moves on on its lower wafer 201.
For example, by using such as CF4、CF3、C4F6Equal fluoro-gas are the lithographic method of etching gas.
In one example, using reactive ion dry etch process: etching gas includes CF4、CF3It is one or two kinds of and
Helium, wherein the flow of etching gas is 10~800sccm, and etching air pressure is 200~800mtorr, radio-frequency power for 300~
1000w can be in the smooth surface for making etching using the lithographic method.
Specifically, the size of single empty slot 203 is covered in hot spot region no more than the size or empty slot 203 of one single chip,
The depth of empty slot 203 does not touch deep-well area.
Step 2: a cover board 202 identical with 201 size of wafer being provided, the lower surface of cover board 202 is etched, is formed more
A cavity 204, referring to Fig. 5 (B)；
Specifically, cover board 202 is identical as 201 size of wafer, and in one example, cover board 202 is made of silicon circle.
Photoetching is carried out to cover board 202 first；In one example, patterned photoetching is formed in the lower surface of cover board 202
Glue-line is irradiated using the ultraviolet light that photoresist layer carries out certain time to cover board 202 as mask layer, and is passed through gluing, exposure, shown
The photoetching process of the completion cover board 202 such as shadow, drying.
Then the cover board of photoetching 202 is performed etching；Etching can select the methods of wet, dry etching or laser, in cover board
Lower surface formed have certain depth a plurality of cavities 204.
Specifically, using plasma dry etch process, in one example, etching air pressure are 200~800mtorr,
Radio-frequency power is 300~1000w, and etching gas is CF4、CF3One or both of, wherein the flow of etching gas be 10~
50sccm。
The depth of cavity 204 is preset, the width of cavity 204 is equal with the width of empty slot 203 or greater than empty slot 203
Width, when 204 width of cavity of cover board 202 is greater than 203 width of empty slot, the edge phase at the edge and empty slot 203 of cavity 204
Away from 1um or more, reduce required precision when being bonded of the wafer 201 with cover board 202, increase contact surface, improve phase-change material with
Extraneous heat-exchange capacity.
Optionally, cavity 204 is made of the cavity of multiple etchings.It is performed etching, is formed by the lower surface to cover board 202
Multiple cavities of certain depth, empty depth is consistent with the depth of cavity, and empty diameter is greater than 1um.And under cover board 202
The bonding face on surface carries out plasma-activated processing, improves surface adhesion force.
Specifically, multiple cavities can be uniformly distributed, and can also be divided at random in the big Density Distribution in hot spot concentration zones or other regions
Cloth.
Specifically, 204 depth of cavity is determined according to the thickness of cover board.
Optionally, eight inches of cover board 202 with a thickness of 725um, cover sheet thickness corresponding to the top of cavity 204 is small
In 50um.
Step 3: phase-change material is placed in empty slot 203 or cavity 204, referring to Fig. 5 (C)；
In the present embodiment, liquid state phase change material is set in empty slot 202 or cavity 204 by modes such as low speed spin coatings,
After solid phase change material is by first heating liquefaction, then low speed spin coating is carried out, and the mode cooled and solidified is uniformly arranged on empty slot 203
Or in cavity 204.
Step 4: cavity 204 is corresponding with the position of empty slot 203, by the back side key of the lower surface of cover board 202 and wafer 201
It closes, referring to Fig. 5 (D).
Plasma-activated processing first is carried out to the bonding face of 202 lower surface of cover board, improves surface adhesion force.
The lower surface of cover board 202 is aligned with the back side of wafer 201, and each cavity 204 uniformly with each empty slot 203
Position it is corresponding, carry out vacuum and low temperature bonding.
Optionally, depending on material of the juncture at the lower surface of cover board 202 and the back side of wafer 201 by cover board 202.
Optionally, cover board 202 is bonded with wafer 201 by vacuum and low temperature or the mode of alloy congruent melting engagement is welded.
Step 5: the upper surface of cover board 202 is carried out it is thinned, and the upper surface of cover board 202 be arranged heat transfer medium, passing
Heat sink 205 are arranged on thermal medium, referring to Fig. 5 (E).
The upper surface of cover board 202 is thinned, and can be improved phase-change material and extraneous heat-exchange capacity, by cover board 202
Upper surface setting heat transfer medium and heat sink 205 can further promote phase-change material and extraneous heat exchange, realize phase transformation material
Expect efficient heat dissipation performance.
Any suitable mechanical milling tech, chemical mechanical milling tech or etching technics can be used in reduction process
Deng.The thickness of wafer 201 or cover board 202 after being thinned can carry out reasonable set according to actual process.
Step 6: in the front attachment conductive bump 206 of wafer 201, referring to Fig. 5 (F).
Specifically, it is convex by material difference can be divided into the spherical salient point of solder, au bump, polymer for the conductive bump 206 of formation
Point, or other suitable 206 structures of conductive bump.
The manufacturing technology of solder bump can be by mounting salient point to plating, printing and metal injection mode on wiring layer.
Step 7: the structure of para-linkage is cut, to obtain the chip structure of multiple phase-change heats.
Specifically, the wafer level structure for the phase-change heat chip completed to preparation is cut, to obtain phase-change heat
Chip structure.
Another embodiment according to the present invention proposes a kind of phase-change heat wafer scale system encapsulation preparation method.
It is by multiple active components with different function, passive element, MEMS (MEMS) that system, which encapsulates (SIP),
And the other elements such as optical element are combined in a unit, form the system or subsystem that can provide multiple functions,
It allows heterogeneous IC (integrated circuit) integrated, is best encapsulation integration mode.Compared to upper piece system SOC, SIP is integrated to be had
Relatively easy, design cycle and the advantages of the period of appearing on the market is shorter and cost is relatively low, and SIP may be implemented more complicated be
System.Compared with traditional SIP, the encapsulation of wafer scale system is that the integrated processing procedure of encapsulation is completed on wafer, has and substantially reduces envelope
The area of assembling structure reduces the advantages such as manufacturing cost, optimization electrical property, batch manufacture, can significantly reduce workload and equipment
Demand.
Include the following steps:
Step 1: providing first wafer 102 and multiple bare dies 101, setting interlayer is situated between at the back side of the first wafer 102
101 front of multiple bare dies separately is pasted the back side of the first wafer 102 by matter 112, referring to Fig. 7 (A)；
Specifically, inter-level dielectric 112 is set between first wafer 102 and bare die 101, which is insulating layer.
Silica, boron-phosphorosilicate glass, phosphosilicate glass, high molecular material, silicon nitride etc. can be used in inter-level dielectric 112.
Specifically, bare die 101 is pasted on the first wafer 102 by the arrangement of 110 spaced array of crystal-bonding adhesive.
Can have between multiple bare dies 101 can have phase between identical or different function and multiple bare dies 101
Same or different size.Actual number, function and the size of bare die 101 are determined and unrestricted by design requirement.
Optionally, right after the back side that 101 front of multiple bare dies separately is pasted to the first wafer 102
The back-etching of each bare die 101 is formed before empty slot 103, further includes: is molded to the gap between bare die 101 and bare die 101
Filling forms the side wall of covering bare die 101 and the plastic packaging layer 113 of inter-level dielectric 112, and repairs to surface formed after injection molding
It is whole.
Specifically, the first wafer 102 for pasting bare die 101 is put into injection molding machine, is infused with thermosetting plastic (epoxy resin)
Be moulded into type, can to the gap mould filling on the first wafer 102 between bare die 101 and bare die 101, after injection molding to its surface into
Row finishing, referring to Fig. 7 (B).
Injection molding process uses the plastic packaging material (MoldCompound) of liquid or the plastic packaging material of solid, wherein preferably
The plastic packaging material for using liquid is obtained, so that the plastic packaging material of liquid can be filled in front of curing in the gap between adjacent die 101,
Increase the caking property between adjacent die 101, improves the stability of encapsulation.
Step 2: to the back-etching of each bare die 101, empty slot 103 is formed, referring to Fig. 7 (C)；
Specifically, it is covered on each bare die 101 with patterned mask layer, and is operated by exposure, development, drying etc.,
Photoetching is carried out to the background of each bare die 101；Plasma reaction etching is carried out to the bare die 101 after photoetching, forms empty slot 103,
And the depth of empty slot 103 does not touch the deep-well region of bare die 101.
Step 3: it is the second wafer 105 that its lower surface has 104 structure of a plurality of cavities by molding material injection molding, it is empty
Chamber 104 is corresponding with the position of empty slot 103, referring to Fig. 7 (D)；
Specifically, the diameter dimension of the first wafer 102 is identical as the diameter dimension of the second wafer 105.
Specifically, molding material passes through mold before curing and prepares 104 structure of a plurality of cavities, and in the second wafer 105
Upper surface paste carrier wafer 109, be used to support and fix the second wafer 105, it is ensured that the second wafer 105 of injection molding it is flat
Whole degree.
In one example, cavity 104 is made of the cavity of multiple etchings.
Specifically, multiple cavities can be uniformly distributed, and can also be divided at random in the big Density Distribution in hot spot concentration zones or other regions
Cloth, empty depth is consistent with the depth of cavity 104, and empty diameter is greater than 1um.
Specifically, 104 depth of cavity is determined according to the thickness of the second wafer 105.
Step 4: phase-change material is set in cavity 104 or empty slot 103, referring to Fig. 7 (E)；
Liquid state phase change material is set in empty slot 103 or cavity 104 by modes such as low speed spin coatings, and solid phase change material is logical
After first heating liquefaction, then low speed spin coating is carried out, and the mode cooled and solidified is set in empty slot 103 or cavity 104.
Step 5: the lower surface of the second wafer 105 being bonded with the back side of multiple bare dies 101, referring to Fig. 7 (F)；
The lower surface of second wafer 105 is aligned with the back side of bare die 101, the position pair of each empty slot 103 and cavity 104
It answers, and carries out vacuum and low temperature bonding.
Step 6: the front of the first wafer 102 being carried out to be thinned or remove the first wafer 102, referring to Fig. 7 (G).
Specifically, the first wafer 102 is used to support fixed multiple bare dies 101 separately and pastes 102 circle back of the first crystalline substance
On the inter-level dielectric 112 in face.
Step 7: in the front of the first wafer 102, being performed etching with the weld pad corresponding position of bare die 101, etching is deep to the
One wafer 102 exposes the weld pad of bare die 102, forms through-hole 106, referring to Fig. 7 (H)；
Specifically, corresponding with each bare die 101 in the first wafer 102 after the front of the first wafer 102 being thinned
Position etched recesses, etching depth include the etching to the inter-level dielectric 112 between the first wafer 102 and bare die 101.
Specifically, specific as follows to 112 using plasma dry etching of inter-level dielectric: etching air pressure be 100~
1000mtorr, radio-frequency power are 1000~3000W, etching gas C4F6, carrier gas is argon gas.Wherein, the flow of etching gas
For 10~500sccm, the flow of argon gas is 200~1500sccm.
Specifically, etching gas further includes CF4, CF4The flow of gas is 10~1000sccm, can reduce inter-level dielectric
The polymeric layer formed in 112 etching processes, erosion are deep to the weld pad that the first wafer 102 exposes bare die 101, guarantee through-hole 106
Etching depth.
In one example, the diameter of through-hole 106 is less than 500um.
Step 8: the 106 filling conductive material in through-hole forms conductive plunger 107, is electrically connected with realizing with bare die 101
It connects.
Specifically, first depositing metal oxide or passivation layer, rear deposited metal in through-hole 106.
Specifically, deposited metal is peptide or copper, and fills through-hole 106 by electroplating technology, forms conductive plunger 107.
Optionally, the formation process of the conductive plunger and conventional complementary metal-oxide semiconductor (MOS) (CMOS) technique
Unanimously.
Optionally, conductive material is filled in through-hole 106, is formed after conductive plunger 107, further includes: leading
Setting reroutes layer, the conductive material electrical communication that will be filled in through-hole 106 in electric plug 107.
Step 9: dress patch conductive bump 108, conductive bump 108 and bare die on conductive plunger 107 or on rerouting layer
101 are electrically connected, referring to Fig. 7 (I).
Specifically, using through silicon via technology, production vertically penetrates the electrical connecting passage of wafer, is drawn by electrical connecting passage
Electrode makes bare die 101 be electrically connected with conductive bump 108.
Step 10: removing the carrier wafer 109 of 105 upper surface of the second wafer, referring to Fig. 7 (J), and to the second wafer 105
Upper surface be thinned to preset thickness, keep the heat transfer property of cavity 104 or 103 phase change material inside of empty slot, reference
Fig. 7 (K).
Step 11: heat transfer medium being set in the upper surface of the second wafer 105, heat sink 114 are arranged on heat transfer medium, and right
The encapsulation of wafer scale system is cut, referring to Fig. 7 (L).
Step 12: after the completion of the encapsulation of phase-change heat wafer scale system, being divided into several bare dies is one group of multiple modules,
Each module forms a system for being capable of providing multiple functions.
Specifically, the encapsulation of phase-change heat wafer scale system is completed, the first wafer 102 can be cut along Cutting Road
The multiple bare dies 101 being integrated on the first wafer 102 are divided into module independent by technique, such as each module is equal
Structure including phase-change heat and heat sink heat dissipation, the module form the system or subsystem that can provide multiple functions, the function
It can depend on the function of actually integrated chip.
Embodiment 1
Fig. 1 phase-change heat chip structure according to an embodiment of the invention, Fig. 2 is according to one embodiment of present invention
A kind of phase-change heat chip structure, Fig. 3 another phase-change heat chip structure according to an embodiment of the invention.
As shown in Figure 1, embodiment provides a kind of phase-change heat chip structure, including cover board 5 and chip 6:
The lower surface of cover board 5 is bonded with the back side of chip 6, and the lower surface of cover board 5 is provided with cavity 7, and the back side of chip 6 is set
It is equipped with empty slot 8, cavity 7 is connected to empty slot 8, has phase-change material in cavity 7 or empty slot 8.
The structure further includes heat sink 9, heat sink 9 being set to the upper surface of cover board 5；It further include conductive bump 11, conductive bump
11 are mounted on the front of chip 6.Cover board 5 is made of silicon circular wafer, and cover board 5 is equipped with solder 4 with the place of bonding of chip 6.
As shown in Fig. 2, the width of cavity 7 is greater than the width of empty slot 8.
As shown in figure 3, cavity 7 is made of multiple cavities, empty diameter is greater than 1um.
By the way that cavity 7 is arranged in the lower surface of cover board 5, empty slot 8, the full sky of phase-change material filling are set at the back side of chip 6
After in chamber 7 or empty slot 8, phase-change material heat absorption is undergone phase transition, volume expansion, and the expandable space of phase-change material increases, reduction
To the pressure of chip 6 and cover board 5 after phase-change material expansion, to improve the reliability of chip.
Embodiment 2
The flow chart of Fig. 4 phase-change heat wafer scale preparation method according to an embodiment of the invention.Fig. 5 (A)~Fig. 5
(F) be respectively different phase in phase-change heat wafer scale preparation process according to an embodiment of the invention structural representation
Figure.
As shown in figure 4, including the following steps: the present embodiment provides a kind of phase-change heat wafer scale preparation method
Step 101: a wafer 201 being provided, multiple empty slots 103, and empty slot 203 are formed to the back-etching of wafer 101
Depth do not touch the deep-well region close to wafer 201, as shown in Fig. 5 (A)；
It to the back-etching of wafer 201, is formed before multiple empty slots 203, needs to carry out the back side of wafer 201 thinned；
Step 102: a cover board 202 identical with 201 size of wafer being provided, the lower surface of cover board 202 is etched, is formed
A plurality of cavities 204, as shown in Fig. 5 (B)；
The operation such as it is exposed, develops, drying by the hot spot region to wafer 201 and cover board 202, to 201 He of wafer
Cover board 202 carries out photoetching, then carries out plasma reaction etching.
Photoresist is filled on wafer 201 and cover board 202 first, and covers mask plate on wafer 201 and cover board 102,
Then the irradiation for carrying out certain time to wafer across mask plate with ultraviolet light makes wafer 201 and cover board using ultraviolet light irradiation
The photoresist of 202 specific parts chemically reacts, and comes out the surface exposure of Partial wafer.Then, by containing chlorine or fluorine-containing
Etching gas carries out plasma reaction dry etch process to wafer 201 and cover board 202, the pattern transfer of photoresist is arrived
On its lower wafer.
Step 103: phase-change material is placed in empty slot 203, as shown in Fig. 5 (C)；
Liquid state phase change material is set in empty slot 203 by modes such as low speed spin coatings, and solid phase change material is by first heating up
After liquefaction, then low speed spin coating is carried out, and the mode cooled and solidified is set in empty slot 203.
Step 104: cavity 204 is corresponding with the position of empty slot 203, by the back side key of the lower surface of cover board 202 and wafer 201
It closes, as shown in Fig. 5 (D).
Plasma-activated processing first is carried out to the bonding face of 202 lower surface of cover board, improves surface adhesion force.
The lower surface of cover board 202 is aligned with the back side of wafer 201, carries out vacuum and low temperature bonding.
Step 105: the upper surface of cover board 202 is carried out it is thinned, and the upper surface of cover board 202 be arranged heat transfer medium,
Heat sink 205 are arranged on heat transfer medium, as shown in Fig. 5 (E).
Step 106: in the front attachment conductive bump 206 of wafer 201, as shown in Fig. 5 (F).
When conductive bump 206 is soldered ball (such as tin ball), soldered ball can be placed in wafer 201 just by planting ball technique
Face.
Step 107: the structure of para-linkage is cut, to obtain the chip structure of multiple phase-change heats.
The wafer level structure for preparing the phase-change heat chip completed is cut, to obtain the chip structure of phase-change heat.
Embodiment 3
The flow chart of Fig. 6 phase-change heat wafer scale system encapsulation preparation method according to an embodiment of the invention, Fig. 7
(A)~Fig. 7 (L) is the difference in phase-change heat circle grade system encapsulation preparation process according to an embodiment of the invention respectively
The structural schematic diagram in stage.
As shown in fig. 6, embodiment provides a kind of phase-change heat wafer scale system encapsulation preparation method, comprising:
Step 201: first wafer 102 and multiple bare dies 101 being provided, layer is set at the back side of the first wafer 102
Between medium 112,101 front of multiple bare dies separately is pasted to the back side of the first wafer 102；
As shown in Fig. 7 (A), inter-level dielectric 112 is set, bare die 101 passes through die bond between first wafer 102 and bare die 101
Glue 110 pastes on wafer 102, and inter-level dielectric 112 uses earth silicon material.
To the gap mould filling between bare die 101 and bare die 101, the side wall and inter-level dielectric of covering bare die 101 are formed
112 plastic packaging layer 113, and surface formed after injection molding is modified, as shown in Fig. 7 (B).
The mode of its injection molding are as follows: the first wafer for pasting bare die is put into injection molding machine, with thermosetting plastic (asphalt mixtures modified by epoxy resin
Rouge) injection molding plastic packaging layer 113, its surface is modified after injection molding.
Step 202: the back side of each bare die 101 being performed etching, empty slot 103 is formed.
As shown in Fig. 7 (C), to the carry out plasma reaction etching of each bare die 101, empty slot 103, and empty slot are formed
103 depth does not touch the deep-well region of bare die 101.
Step 203: it is the second wafer 105 that its lower surface has 104 structure of a plurality of cavities by molding material injection molding,
Cavity 104 is corresponding with the position of empty slot 103；
Molding material passes through mold before curing and prepares 104 structure of cavity, is arranged in the upper surface of the second wafer 105 and carries
Body wafer 109, as shown in Fig. 7 (D).
Step 204: phase-change material is set in empty slot 103.
As shown in Fig. 7 (E), liquid state phase change material is set in empty slot 103 by modes such as low speed spin coatings, phase transformation material
Material carries out low speed spin coating the liquefaction that first heats up, again and is set in empty slot 103 by way of cooling and solidifying.
Step 205: the lower surface of the second wafer 105 is bonded with the back side of multiple bare dies 101.
As shown in Fig. 7 (F), the lower surface of the second wafer 105 is aligned with the back side of bare die 101, and carry out vacuum and low temperature
Bonding.
Step 206: after the front of the first wafer 102 is thinned, in the front of the first wafer 102, with bare die 101
Weld pad corresponding position performs etching, and etching is deep to the weld pad that the first wafer 102 exposes bare die 101, forms through-hole 106；
As shown in Fig. 7 (G) and as shown in Fig. 7 (H), the front of the first wafer 102 is carried out it is thinned, in the first wafer 102
Front, performed etching with the weld pad corresponding position of bare die 101, etching depth include to the first wafer 102 and bare die 101 it
Between inter-level dielectric 113 etching, the diameter of through-hole 106 is less than 500um.
Step 207: filling conductive material in through-hole 106, form conductive plunger 107, be electrically connected with realizing with bare die 101
It connects.
Setting reroutes layer on conductive plunger 107, the dress patch conductive bump on conductive plunger 107 or on rerouting layer
108, conductive bump 108 is electrically connected with bare die 101, shown in Fig. 7 (I).
Step 208: removing the carrier wafer 109 of 105 upper surface of the second wafer, as shown in Fig. 7 (J), and to the second wafer
105 upper surface carries out being thinned to preset thickness, as shown in Fig. 7 (K).
Step 209: heat transfer medium being set in the upper surface of the second wafer 105, heat sink 114 are arranged on heat transfer medium, such as
Shown in Fig. 7 (L).
Step 210: after the completion of the encapsulation of phase-change heat wafer scale system, being divided into several bare dies 101 is one group multiple
Module, each module form a system for being capable of providing multiple functions.
Phase-change heat wafer scale system of the invention encapsulates preparation method, the method phase that wafer-level packaging and system are encapsulated
In conjunction with will encapsulate integrated multiple groups chip on wafer, the area of encapsulating structure can be reduced, the encapsulation of wafer scale system can be improved
The radiating efficiency of structure optimizes the electrical property of chip, reduces manufacturing cost.
Various embodiments of the present invention are described above, above description is exemplary, and non-exclusive, and
It is not limited to disclosed each embodiment.Without departing from the scope and spirit of illustrated each embodiment, for this skill
Many modifications and changes are obvious for the those of ordinary skill in art field.
Claims (21)
1. a kind of phase-change heat chip structure, which is characterized in that including cover board and chip:
The lower surface of the cover board is bonded with the back side of the chip, and the lower surface of the cover board is provided with cavity, the chip
The back side be provided with empty slot, the cavity is connected to the empty slot, has phase-change material in the cavity or empty slot.
2. phase-change heat chip structure according to claim 1, which is characterized in that further include heat sink, the heat sink setting
In the upper surface of the cover board.
3. phase-change heat chip structure according to claim 1, which is characterized in that the heat sink upper table with the cover board
Heat transfer medium is equipped between face.
4. phase-change heat chip structure according to claim 1, which is characterized in that it further include conductive bump, the conduction
Convex block is mounted on the front of the chip.
5. phase-change heat chip structure according to claim 1, which is characterized in that the width of the cavity is greater than or equal to
The width of the empty slot.
6. phase-change heat chip structure according to claim 1, which is characterized in that the cavity is made of multiple cavities.
7. a kind of wafer scale preparation method of phase-change heat chip characterized by comprising
One wafer is provided, to the back-etching of the wafer, forms multiple empty slots, and the depth of the empty slot do not touch it is close
The deep-well region of the wafer；
One cover board identical with the wafer size is provided, the lower surface of the cover board is etched, a plurality of cavities are formed；
Phase-change material is placed in the empty slot or cavity；
The cavity is corresponding with the position of the empty slot, and the lower surface of the cover board is bonded with the back side of the wafer.
8. the wafer scale preparation method of phase-change heat chip according to claim 7, which is characterized in that further include: in institute
The upper surface setting heat transfer medium for stating cover board, is arranged heat sink on the heat transfer medium.
9. the wafer scale preparation method of phase-change heat chip according to claim 7, which is characterized in that in the cover board
Upper surface is arranged before heat transfer medium, further includes: carries out to the upper surface of the cover board thinned.
10. the wafer scale preparation method of phase-change heat chip according to claim 7, which is characterized in that the wafer
Back-etching, formed before multiple empty slots, further includes: the backside of wafer is carried out thinned.
11. the wafer scale preparation method of phase-change heat chip according to claim 7, which is characterized in that further include: in institute
State the front attachment conductive bump of wafer.
12. the wafer scale preparation method of phase-change heat chip according to claim 7, which is characterized in that the knot of para-linkage
Structure is cut, to obtain the chip structure of multiple phase-change heats.
13. a kind of phase-change heat wafer scale system encapsulates preparation method, comprising:
One the first wafer and multiple bare dies are provided, inter-level dielectric is set at the back side of the first wafer, it is multiple naked by separately
Piece front pastes the back side of first wafer；
To the back-etching of each bare die, empty slot is formed；
It is the second wafer that its lower surface has a plurality of cavities structure, the cavity and the empty slot by molding material injection molding
Position it is corresponding；
Phase-change material is set in the cavity or empty slot；
The lower surface of second wafer is bonded with the back side of the multiple bare die；
It in the front of first wafer, is performed etching with the weld pad corresponding position of the bare die, it is brilliant that etching is deep to described first
Circle exposes the weld pad of the bare die, forms through-hole；
It fills conductive material in the through-hole, forms conductive plunger, be electrically connected with realizing with the bare die.
14. phase-change heat wafer scale system according to claim 13 encapsulates preparation method, which is characterized in that will be alternate
Every multiple bare die fronts paste the back side of the first wafer after, to the back-etching of each bare die, formed empty slot it
Before, further includes: to the gap mould filling between the bare die and bare die, form the side wall and the interlayer for covering the bare die
The plastic packaging layer of medium.
15. phase-change heat wafer scale system according to claim 13 encapsulates preparation method, which is characterized in that described the
The front of one wafer, before being performed etching with the weld pad corresponding position of the bare die, further includes: to the front of first wafer
It carries out being thinned or removing first wafer.
16. phase-change heat wafer scale system according to claim 13 encapsulates preparation method, which is characterized in that described logical
Conductive material is filled in hole, is formed after conductive plunger, further includes: setting reroutes layer on the conductive plunger.
17. phase-change heat wafer scale system described in 3 or 16 encapsulates preparation method according to claim 1, which is characterized in that also wrap
Include: dress patch conductive bump, the conductive bump are electrically connected with the bare die on the conductive plunger or on the rewiring layer
It is logical.
18. phase-change heat wafer scale system according to claim 13 encapsulates preparation method, which is characterized in that further include:
Heat transfer medium is set in the upper surface of second wafer, is arranged on the heat transfer medium heat sink.
19. phase-change heat wafer scale system according to claim 18 encapsulates preparation method, which is characterized in that described the
Before the upper surface setting heat transfer medium of two wafers, further includes: carried out to the upper surface of second wafer thinned.
20. phase-change heat wafer scale system according to claim 13 encapsulates preparation method, which is characterized in that the phase transformation
Material is set in empty slot or cavity by low speed spin coating mode.
21. phase-change heat wafer scale system according to claim 18 encapsulates preparation method, which is characterized in that further include:
After the completion of the phase-change heat wafer scale system encapsulation, being divided into several bare dies is one group of multiple modules, each module shape
The system for being capable of providing multiple functions at one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811081424.XA CN109216301B (en) | 2018-09-17 | 2018-09-17 | Phase-change heat dissipation chip structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811081424.XA CN109216301B (en) | 2018-09-17 | 2018-09-17 | Phase-change heat dissipation chip structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109216301A true CN109216301A (en) | 2019-01-15 |
| CN109216301B CN109216301B (en) | 2020-09-25 |
Family
ID=64984593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811081424.XA Active CN109216301B (en) | 2018-09-17 | 2018-09-17 | Phase-change heat dissipation chip structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109216301B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112146060A (en) * | 2020-09-27 | 2020-12-29 | 安徽工业大学 | Low-melting-point alloy phase-change heat dissipation LED automobile headlamp |
| CN113443602A (en) * | 2021-06-02 | 2021-09-28 | 中国科学院地质与地球物理研究所 | Wafer level packaging structure of micro electro mechanical system chip and manufacturing process thereof |
| TWI744195B (en) * | 2021-02-24 | 2021-10-21 | 創意電子股份有限公司 | Thermal peak suppression device |
| US11754343B2 (en) | 2019-11-05 | 2023-09-12 | Toyota Motor Engineering & Manufacturing North America, Inc. | Phase change heat-storing mechanisms for substrates of electronic assemblies |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050280162A1 (en) * | 2004-06-18 | 2005-12-22 | International Business Machines Corporation | Thermal interposer for thermal management of semiconductor devices |
| US20110156245A1 (en) * | 2009-12-31 | 2011-06-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and Apparatus for Cooling an Integrated Circuit |
| CN105451506A (en) * | 2014-08-29 | 2016-03-30 | 富葵精密组件(深圳)有限公司 | Thin cooling fin and manufacturing method thereof |
| CN107195603A (en) * | 2017-06-30 | 2017-09-22 | 中国电子科技集团公司第五十八研究所 | A kind of preparation method of the encapsulating structure based on high heat conduction phase-change material phase-change heat technology |
| CN108148554A (en) * | 2016-12-02 | 2018-06-12 | 臻鼎科技股份有限公司 | Cooling fin filled compositions, cooling fin and preparation method thereof |
-
2018
- 2018-09-17 CN CN201811081424.XA patent/CN109216301B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050280162A1 (en) * | 2004-06-18 | 2005-12-22 | International Business Machines Corporation | Thermal interposer for thermal management of semiconductor devices |
| US20110156245A1 (en) * | 2009-12-31 | 2011-06-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and Apparatus for Cooling an Integrated Circuit |
| CN105451506A (en) * | 2014-08-29 | 2016-03-30 | 富葵精密组件(深圳)有限公司 | Thin cooling fin and manufacturing method thereof |
| CN108148554A (en) * | 2016-12-02 | 2018-06-12 | 臻鼎科技股份有限公司 | Cooling fin filled compositions, cooling fin and preparation method thereof |
| CN107195603A (en) * | 2017-06-30 | 2017-09-22 | 中国电子科技集团公司第五十八研究所 | A kind of preparation method of the encapsulating structure based on high heat conduction phase-change material phase-change heat technology |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11754343B2 (en) | 2019-11-05 | 2023-09-12 | Toyota Motor Engineering & Manufacturing North America, Inc. | Phase change heat-storing mechanisms for substrates of electronic assemblies |
| CN112146060A (en) * | 2020-09-27 | 2020-12-29 | 安徽工业大学 | Low-melting-point alloy phase-change heat dissipation LED automobile headlamp |
| CN112146060B (en) * | 2020-09-27 | 2022-06-28 | 安徽工业大学 | Low-melting-point alloy phase-change heat dissipation LED automobile headlamp |
| TWI744195B (en) * | 2021-02-24 | 2021-10-21 | 創意電子股份有限公司 | Thermal peak suppression device |
| CN113443602A (en) * | 2021-06-02 | 2021-09-28 | 中国科学院地质与地球物理研究所 | Wafer level packaging structure of micro electro mechanical system chip and manufacturing process thereof |
| CN113443602B (en) * | 2021-06-02 | 2023-12-08 | 中国科学院地质与地球物理研究所 | Wafer level packaging structure of micro-electromechanical system chip and manufacturing process thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109216301B (en) | 2020-09-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109216301A (en) | Phase-change heat chip structure and preparation method thereof | |
| US10636678B2 (en) | Semiconductor die assemblies with heat sink and associated systems and methods | |
| CN104600064B (en) | Chip structure and method on packaging part | |
| KR102643053B1 (en) | semiconductor device assembly | |
| CN105679718B (en) | Semiconductor package part and forming method thereof | |
| CN104037153B (en) | 3D packaging parts and forming method thereof | |
| CN110060935A (en) | Semiconductor devices and its manufacturing method | |
| CN110299351A (en) | Semiconductor package part and forming method thereof | |
| US8466486B2 (en) | Thermal management system for multiple heat source devices | |
| CN104752367B (en) | Wafer level packaging structure and forming method thereof | |
| CN108155153A (en) | For the manufacturing method of the encapsulating structure of heat dissipation | |
| CN109314093A (en) | With the semiconductor device assemblies for wearing mould cooling duct | |
| CN107768351A (en) | Semiconductor package part with heat engine electrical chip and forming method thereof | |
| CN109786268A (en) | Metallization pattern in semiconductor package part and forming method thereof | |
| CN105304613A (en) | Semiconductor device and method | |
| CN105895623B (en) | Substrate design and forming method thereof for semiconductor package part | |
| CN102222625A (en) | Manufacturing method of light-emitting diode (LED) packaging structure and base thereof | |
| KR20090092292A (en) | High thermal performance packaging for circuit dies | |
| US10566270B2 (en) | Enhanced thermal transfer in a semiconductor structure | |
| CN110416094A (en) | Semiconductor devices and forming method thereof | |
| CN109560076A (en) | Integrated fan-out package | |
| CN109786274A (en) | Semiconductor devices and its manufacturing method | |
| CN218867084U (en) | Derived type heat radiation structure, fan-out type packaging structure and integrated circuit | |
| CN111293093B (en) | Intelligent power module and preparation method thereof | |
| CN115312406A (en) | Chip packaging structure and preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |