CN113327924B - Semiconductor device, display substrate and display device - Google Patents

Semiconductor device, display substrate and display device Download PDF

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Publication number
CN113327924B
CN113327924B CN202110573677.4A CN202110573677A CN113327924B CN 113327924 B CN113327924 B CN 113327924B CN 202110573677 A CN202110573677 A CN 202110573677A CN 113327924 B CN113327924 B CN 113327924B
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electrode
substrate
cantilever
gate
display
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CN113327924A (en
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郭威
韩天洋
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BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

The disclosure provides a semiconductor device, a display substrate and a display device, and belongs to the technical field of display. The semiconductor device of the present disclosure includes: a substrate, a thin film transistor and a switching element on the substrate; the thin film transistor includes: a gate electrode, a gate insulating layer, an active layer, a first electrode as a drain electrode, and a second electrode as a source electrode; the first electrode and the second electrode are respectively connected with the active layer; the switching element includes: a third electrode on the substrate; the switching element further includes: a fourth electrode and a fifth electrode respectively positioned at two sides of the third electrode, and a cantilever structure suspended on the third electrode; wherein the fourth electrode is electrically connected with the second electrode; the orthographic projection of the cantilever beam structure on the substrate is at least partially overlapped with the orthographic projections of the third electrode, the fourth electrode and the fifth electrode on the substrate.

Description

Semiconductor device, display substrate and display device
Technical Field
The disclosure belongs to the technical field of display, and in particular relates to a semiconductor device, a display substrate and a display device.
Background
The thin film transistor is used as an important electrical device in a display device, and the performance of the thin film transistor directly influences the display effect and the service life of the display device.
In the current display device, the thin film transistor has larger leakage current in the off state, is easy to cause the heating of the device and wastes larger power consumption. In the display process of the display device, due to the existence of leakage current, the display picture is easy to generate residual shadow and bad, and the display effect is affected.
Disclosure of Invention
The present disclosure is directed to at least solving one of the technical problems in the prior art, and provides a semiconductor device, a display substrate, and a display device.
In a first aspect, embodiments of the present disclosure provide a semiconductor device, including: a substrate, a thin film transistor and a switching element on the substrate;
the thin film transistor includes: a gate electrode, a gate insulating layer, an active layer, a first electrode as a drain electrode, and a second electrode as a source electrode; the first electrode and the second electrode are respectively connected with the active layer;
the switching element includes: a third electrode on the substrate; the switching element further includes: the fourth electrode, the fifth electrode and the cantilever beam structure are respectively positioned at two sides of the third electrode and are suspended on the third electrode; wherein the fourth electrode is electrically connected with the second electrode;
And the orthographic projection of the cantilever structure on the substrate is at least partially overlapped with the orthographic projections of the third electrode, the fourth electrode and the fifth electrode on the substrate.
Optionally, the gate insulating layer extends to an area where the switching element is located, where the gate insulating layer is disposed in a hollow manner at the third electrode, the gate insulating layer is located between the fourth electrode and the substrate, and the gate insulating layer is located between the fifth electrode and the substrate.
Optionally, the cantilever structure includes: a support portion and a cantilever portion;
the supporting part is fixed on the substrate, and one end of the supporting part is connected with one end of the cantilever part;
one end of the cantilever beam part is connected with one end of the supporting part, and the other end of the cantilever beam part is suspended.
Optionally, the cantilever structure includes: a support portion and a cantilever portion;
the support part is fixed on the fifth electrode, and one end of the support part is connected with one end of the cantilever part;
one end of the cantilever beam part is connected with one end of the supporting part, and the other end of the cantilever beam part is suspended.
Optionally, the fourth electrode and the second electrode are in an integrally formed structure.
Optionally, the cantilever structure is a gold/aluminum/gold laminate structure.
Optionally, the material of the active layer includes: a carbon nanotube material.
In a second aspect, embodiments of the present disclosure provide a display substrate including a semiconductor device as provided above.
Optionally, the display substrate further includes: the passivation layer is positioned on one side of the first electrode and the second electrode away from the substrate, and the first via penetrates through the passivation layer;
the orthographic projection of the first via hole on the substrate at least partially overlaps with the orthographic projection of the fourth electrode on the substrate;
the orthographic projection of the first via hole on the substrate at least partially overlaps with the orthographic projection of the fifth electrode on the substrate;
the orthographic projection of the first via on the substrate at least partially overlaps with the orthographic projection of the cantilever structure on the substrate.
Optionally, the display substrate further includes: the first conductor layer, the second conductor layer and the third conductor layer are positioned on the substrate and are sequentially and insulated along the direction deviating from the substrate;
the first conductor layer includes: the grid electrode and the third electrode;
the second conductor layer includes: the first electrode, the second electrode, the fourth electrode, and the fifth electrode;
The third conductor layer includes: the cantilever beam structure.
Optionally, the display substrate further includes: a plurality of gate lines and a plurality of data lines disposed to cross.
Optionally, a plurality of the semiconductor devices are arranged in an array;
at least part of the grid electrodes of the semiconductor devices in the same row are electrically connected with the same grid line and are of an integrated structure;
at least part of the fifth electrodes of the semiconductor devices in the same column are electrically connected with the same data line and are in an integrated structure, or when the supporting parts are fixed on the fifth electrodes, at least part of the fifth electrodes of the semiconductor devices in the same column are electrically connected with the same data line, and the data line and the supporting parts are in an integrated structure.
Optionally, the display substrate further includes: a first voltage signal line having the same direction as the gate line; the first voltage signal line is positioned between the adjacent grid lines;
the first conductor layer further includes: the first voltage signal line.
Optionally, at least part of the third electrodes of the semiconductor devices in the same row are electrically connected with the same first voltage signal line and are in an integrated structure.
Optionally, the display substrate further includes: a second voltage signal line having the same direction as the gate line;
the third conductor layer further includes: the second voltage signal line.
Optionally, at least part of the cantilever structures of the semiconductor devices in the same row are electrically connected with the same second voltage signal line and are integrally formed.
In a third aspect, embodiments of the present disclosure provide a display device including a display substrate as provided above.
Drawings
Fig. 1 is a schematic structural diagram of an exemplary thin film transistor;
FIG. 2 is a schematic diagram of a partial structure of an exemplary display substrate;
fig. 3A is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure;
fig. 3B is a schematic structural diagram of another semiconductor device according to an embodiment of the present disclosure;
fig. 4A is a schematic cross-sectional structure of the semiconductor device shown in fig. 3A in the A-A' direction;
fig. 4B is a schematic cross-sectional structure of the semiconductor device shown in fig. 3B in the B-B' direction;
FIG. 5 is a schematic illustration of a cantilever structure;
fig. 6 is a schematic structural diagram of yet another semiconductor device provided in an embodiment of the present disclosure;
fig. 7 is a schematic cross-sectional structure of the semiconductor device shown in fig. 6 in the C-C direction;
Fig. 8A is a schematic structural diagram of a display substrate according to an embodiment of the disclosure;
fig. 8B is a schematic structural diagram of another display substrate according to an embodiment of the disclosure;
FIG. 9A is a schematic cross-sectional view of the display substrate shown in FIG. 8A in the direction D-D';
FIG. 9B is a schematic cross-sectional view of the display substrate shown in FIG. 8B in the E-E' direction;
fig. 10 is a schematic structural diagram of a display substrate according to another embodiment of the disclosure;
fig. 11 is a schematic cross-sectional structure of the display substrate shown in fig. 10 in the F-F' direction.
Detailed Description
In order that those skilled in the art will better understand the technical solutions of the present disclosure, the present disclosure will be described in further detail with reference to the accompanying drawings and detailed description.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
Fig. 1 is a schematic structural diagram of an exemplary thin film transistor, which is formed on a substrate 101 as shown in fig. 1, and includes: a gate electrode 102, a gate insulating layer 103, an active layer 104, a first electrode 105, and a second electrode 106; the first electrode 105 and the second electrode 106 are connected to the active layer 103, respectively; one of the first electrode 105 and the second electrode 106 is a source electrode, and the other is a drain electrode. The thin film transistor may be applied to a liquid crystal display (Liquid Crystal Display, LCD) substrate, and may also be applied to an Organic Light-Emitting Diode (OLED) display substrate, and in the embodiments of the present disclosure, the thin film transistor is described as being applied to the LCD display substrate. Here, the thin film transistor may be a field effect transistor or the same device with other characteristics, and the source and the drain of the thin film transistor are symmetrical, so that the source and the drain are not different. In order to distinguish between the source and drain of the thin film transistor, in the embodiment of the present disclosure, the first electrode 105 may be the drain and the second electrode 106 may be the source. In addition, the transistors can be divided into N-type and P-type according to the characteristic distinction of the thin film transistor, the N-type transistor is used in the following embodiments, when the N-type transistor is adopted, the first electrode is the drain electrode of the N-type transistor, the second electrode is the source electrode of the N-type transistor, and when the gate electrode inputs a high level, the source electrode and the drain electrode are conducted; and when the grid electrode inputs a low level, the source electrode and the drain electrode are conducted. In the embodiments of the present disclosure, an N-type transistor will be described as an example.
Fig. 2 is a schematic view showing a partial structure of an exemplary display substrate, as shown in fig. 2, the display panel includes a plurality of common electrode lines (not shown), a plurality of Gate lines Gate and a plurality of Data lines Data, and a plurality of pixel units are defined by crossing the plurality of Gate lines Gate and the plurality of Data lines Data, each pixel unit includes a thin film transistor T and a pixel electrode 107, each pixel electrode 107 corresponds to one common electrode, or each pixel electrode 107 corresponds to one integral common electrode in all pixel units. The thin film transistor T has a Gate electrode connected to the Gate line Gate, a source electrode connected to the Data line Data, and a drain electrode connected to the pixel electrode 107. It can be understood that the pixel unit may further include a storage capacitor, other transistors, and other devices, which may be connected according to a connection manner in the related art, which is not described herein. For a liquid crystal display panel, in some embodiments, the pixel electrode 107 and the common electrode may be disposed opposite to each other, with a liquid crystal layer disposed between the pixel electrode 107 and the common electrode, and the common electrode may be connected to a common electrode line through a via hole; in other embodiments, for example, in advanced super-dimensional field switching (Advanced Super Dimension Switch, ADS) technology, the pixel electrode 107 may be located on the same side of the liquid crystal layer as the common electrode, and an electric field (e.g., a horizontal electric field) is formed between the pixel electrode 107 and the common electrode to control the deflection of the liquid crystal to achieve the display effect.
When the pixel unit displays, a scan signal can be loaded on the Gate line Gate and input to the Gate electrode 102 of the thin film transistor T, so that the thin film transistor T is turned on. The Data line Data is applied with a Data voltage, so that the Data voltage is input to the pixel electrode 107. The common electrode line is applied with a common voltage, and the common voltage is inputted to the common electrode. The liquid crystal molecules in the liquid crystal layer can deflect under the drive of an electric field formed by the data voltage and the public voltage, the deflected liquid crystal molecules can transmit light rays with certain brightness, and the transmittance of the liquid crystal molecules is changed by adjusting the electric field intensity between the pixel electrode 107 and the public electrode, so that different gray scale display can be realized. When the pixel unit does not display, the Gate line Gate is not loaded with a signal, so that the thin film transistor is turned off. However, due to the semiconductor characteristics of the material of the active layer 104, the thin film transistor still has a certain leakage current passing through in the off state, for example, when the active layer 104 is made of carbon nanotubes, the leakage current may be large, so that the thin film transistor cannot be in a completely off state, which is easy to cause heating of the device and wastes large energy consumption. In the display process of the display substrate, due to the existence of leakage current, the display picture is easy to generate residual shadow and bad, and the display effect is affected.
Carbon nanotubes are considered as ideal active layer materials for constructing sub-nano transistors, and the atomic-level pipe diameter ensures that the device has excellent gate electrostatic control capability, so that short channel effect can be overcome more easily; theoretical research shows that the carbon nanotube device has 5-10 times of advantages in speed and power consumption compared with a silicon-based device, the carbon nanotube is easy to obtain and low in cost, and when the carbon nanotube is used for manufacturing an active layer, modes such as coating and the like can be used, so that the process is simple, and the development requirement of an integrated circuit in the 'post-molar age' is hopeful to be met. In the long term, the carbon nanotube material device is expected to replace the silicon-based material device.
In one embodiment, the material of the active layer 104 includes single-walled carbon nanotubes (SWCNTs). Specifically, single-walled carbon nanotubes are classified into semiconductor-type single-walled carbon nanotubes (semiconducting single-walled carbon nanotubes, s-SWCNTs) and metal-type single-walled carbon nanotubes (m-SWCNTs). The optimal material for the active layer 104 is s-SWCNTs, which can greatly reduce the leakage current of the thin film transistor. However, subject to current manufacturing techniques, there are about 1/3 of m-SWCNTs in the preparation of s-SWCNTs, and further purification of semiconductor-type single-walled carbon nanotubes using various purification techniques is required. However, according to the current purification process, even if the molar ratio of s-SWCNTs in SWCNTs is increased to 99.99%, the leakage current value of the prepared thin film transistor is still relatively large, and it is difficult to meet the increasingly stringent requirements brought by the continuous development of the driving technology.
In order to solve at least one of the above technical problems, the present disclosure provides a semiconductor device, a display substrate, and a display device, and the semiconductor device, the display substrate, and the display device provided by the embodiments of the present disclosure will be described in further detail below with reference to the detailed description and the accompanying drawings.
In a first aspect, an embodiment of the present disclosure provides a semiconductor device, fig. 3A is a schematic structural diagram of the semiconductor device provided in the embodiment of the present disclosure, and fig. 4A is a schematic structural diagram of a cross-section of the semiconductor device shown in fig. 3A on an A-A' path, as shown in fig. 3A and fig. 4A, where the semiconductor device includes: a substrate 101, and a thin film transistor and a switching element on the substrate 101; the thin film transistor includes: a gate electrode 102, a gate insulating layer 103, an active layer 104, a first electrode 105 serving as a drain electrode, and a second electrode 106 serving as a source electrode; the first electrode 105 and the second electrode 106 are connected to the active layer 104, respectively. Note that, the thin film transistor may have a top gate structure or a bottom gate structure, and fig. 3A and fig. 4A illustrate the bottom gate structure as an example. Specifically, when the thin film transistor is of a bottom gate structure, the gate electrode 102, the gate insulating layer 103, the active layer 104, the first electrode 105 as a drain electrode, and the second electrode 106 as a source electrode are sequentially disposed on the substrate 101, the first electrode 105 and the second electrode 106 are respectively connected to the active layer 104, wherein the first electrode 105 and the second electrode 106 may be disposed in the same layer. The switching element includes: a third electrode 201 on the substrate 101; the switching element further includes: a fourth electrode 202 and a fifth electrode 203 respectively positioned at two sides of the third electrode 201, and a cantilever structure 204 suspended on the third electrode 201; wherein the fourth electrode 202 is electrically connected to the second electrode 106; the orthographic projection of the cantilever structure 204 on the substrate 101 at least partially overlaps with the orthographic projections of the third electrode 201, the fourth electrode 202, and the fifth electrode 203 on the substrate 101. For ease of illustration, the gate insulating layer 103 is not shown in fig. 3A.
For example, the substrate 101 may be made of a rigid material such as glass, which may increase the load bearing capacity of the substrate 101 for other layers thereon. Of course, the substrate 101 may also be made of flexible materials such as Polyimide (PI), so as to improve the bending resistance and tensile resistance of the semiconductor device, and avoid the breakage of the substrate 101 caused by stress generated during bending, stretching and twisting, which results in poor circuit breaking. In practical applications, the material of the substrate 101 may be reasonably selected according to practical needs, so as to ensure that the semiconductor device has good performance.
For example, the material of the gate 102 may include a metal material or an alloy material, for example, may include molybdenum, aluminum, or titanium metal material or an alloy including one or more of molybdenum, aluminum, and titanium; the gate electrode 102 may be formed by a process such as vapor deposition. The gate insulating layer 103 may be formed of a single layer structure of silicon nitride or silicon oxide, or may be formed of a multi-layer structure of silicon nitride and silicon oxide, so as to ensure that the gate insulating layer covers the gate 102 and avoid shorting the gate 102 with other film layers thereon. For ease of illustration, the gate insulating layer 103 is not shown in fig. 3A. The material of the active layer 104 may be a metal oxide, a low-temperature polysilicon, or a carbon nanotube material. In one particular embodiment of the present disclosure, the material of the active layer 104 includes SWCNTs. Preferably, the molar ratio of s-SWCNTs is greater than m-SWCNTs in the active layer 104 material. Further preferably, the molar ratio of s-SWCNTs to m-SWCNTs is greater than or equal to 4:1. optionally, the molar ratio of s-SWCNTs to m-SWCNTs is greater than or equal to 99:1. in some embodiments, the molar ratio of s-SWCNTs to m-SWCNTs is less than or equal to 999.5:1, a step of; in some embodiments, the molar ratio of s-SWCNTs to m-SWCNTs is less than or equal to 999:1. the design of the semiconductor device can save the production cost under the condition of ensuring the performance of the device without the ultra-high purification of s-SWCNTs.
For example, the first electrode 105 and the second electrode 106, i.e., the source electrode and the drain electrode, may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of a metal material including molybdenum, aluminum, or titanium, or an alloy including one or more of molybdenum, aluminum, and titanium, for example, the multi-layer structure is a multi-metal layer stack, such as titanium, aluminum, titanium three-layer metal stack (Al/Ti/Al), or the like.
For example, fig. 3B is a schematic structural diagram of another semiconductor device according to an embodiment of the present disclosure, fig. 4B is a schematic sectional structure of the semiconductor device shown in fig. 3B on a B-B' path, and referring to fig. 3B and fig. 4B, the gate insulating layer 103 extends to a region where the switching element is located and is hollowed out at a position of the third electrode 201; in one embodiment, the gate insulating layer 103 is located between the fourth electrode 202 and the substrate, and the gate insulating layer 103 is located between the fifth electrode 203 and the substrate 101. The gate insulating layer 103 is disposed in a hollow manner at the position of the third electrode 201, which can be understood that at least a part of non-overlapping area exists between the orthographic projection of the gate insulating layer 103 on the substrate 101 and the orthographic projection of the third electrode 201 on the substrate 101, so as to expose the third electrode 201, so that the normal operation of the switching element can be ensured. Preferably, the orthographic projection of the gate insulating layer 103 on the substrate 101 does not overlap with the orthographic projection of the third electrode 201 on the substrate 101. The fourth electrode 202 and the fifth electrode 203 are disposed on two sides of the third electrode 201, respectively, and due to the presence of the gate insulating layer 103, the third electrode 201 and the fourth electrode 202 are located in different layers, the fourth electrode 202 and the fifth electrode 203 are located in the same layer, and the height of the third electrode 201 is lower than the heights of the fourth electrode 202 and the fifth electrode 203. The cantilever structure 204 is a conductive structure, and its orthographic projection on the substrate 101 at least partially overlaps with orthographic projections of the third electrode 201, the fourth electrode 202, and the fifth electrode 203 on the substrate 101. For ease of illustration, the gate insulating layer 103 is not shown in fig. 3B.
When the entire semiconductor device is in an on state, a voltage signal is input to the gate electrode 102 in the thin film transistor, and carriers may be formed in the active layer 104, at this time, the first electrode 104 and the second electrode 105, that is, the source and the drain of the thin film transistor are turned on through the active layer 104. The third electrode 201 and the cantilever structure 204 in the switching element can respectively input opposite voltage signals, so that the third electrode 201 and the cantilever structure 204 are attracted to each other, and the cantilever structure 204 is in contact with the fourth electrode 202 and the fifth electrode 203 and always keeps a certain gap with the third electrode 201 because the height of the third electrode 201 is lower than the heights of the fourth electrode 202 and the fifth electrode 203, so that the fourth electrode 202 and the fifth electrode 203 are conducted through the cantilever structure 204. And, the fourth electrode 202 is connected to the second electrode 105, i.e., the drain electrode of the thin film transistor, so that the voltage signal inputted from the fifth electrode 203 of the switching element can be transmitted between the thin film transistor and the switching element, so that the entire semiconductor device is in an on state. Alternatively, the third electrode 201 in the switching element inputs a voltage signal, and the cantilever structure 204 may generate an induced charge by inputting the voltage signal through the third electrode 201 instead of inputting the voltage signal, so that the third electrode 201 and the cantilever structure 204 attract each other, and the fourth electrode 202 and the fifth electrode 203 are conducted through the cantilever structure 204.
When the entire semiconductor device is in an off state, the first electrode 104 and the second electrode 105 in the thin film transistor, that is, between the source and the drain of the thin film transistor are disconnected. The third electrode 201 and the cantilever structure 204 in the switching element also do not input voltage signals, and the cantilever structure 204 is restored to the original state, at this time, the fourth electrode 202 and the fifth electrode 203 are disconnected, so that the whole semiconductor device is disconnected, even if a certain carrier exists in the active layer 104 of the thin film transistor, the whole semiconductor device cannot form a finished current loop, no leakage current is generated, and therefore the generation of the leakage current can be avoided. Alternatively, the third electrode 201 and the cantilever structure 204 in the switching element may be input with the same voltage signal (for example, both input positive voltage signals, both input negative voltage signals, or both input voltage signals are 0V), and the cantilever structure 204 and the fourth electrode 202 are not conductive, so that the entire semiconductor device is broken.
As can be seen from the foregoing, the semiconductor device provided in the embodiments of the present disclosure is composed of a thin film transistor and a switching element, and in the off state, no leakage current is generated therein, so that the problems of device heating, waste of large energy consumption, and the like caused by the leakage current can be avoided. When the method is applied to the drive of the LCD display substrate, the problems of poor residual shadow and the like of a display picture can be avoided, and the display effect is improved. Furthermore, the semiconductor device provided in the embodiment of the present disclosure has a simple structure, and may not need to optimize the material of the active layer 104 to increase the process cost in order to avoid generating leakage current (for example, when SWCNTs are used as the active layer material, high purification of s-SWCNTs is not needed, so that the cost is saved), and the process difficulty is reduced, so that the manufacturing and developing costs may be saved.
In some embodiments, as shown in fig. 3A, 3B, 4A, 4B, and 5, the cantilever structure 204 may include: a support portion 2041 and a cantilever portion 2042; the support portion 2041 is fixed on the base 101, and one end is connected with one end of the cantilever portion 2042; one end of the suspended beam portion 2042 is connected to the other end of the supporting portion 2041, and the other end is suspended. The support portion 2041 is fixed to the substrate 101, which means that the support portion 2041 is in direct contact with the substrate 101, or that the support portion 2041 is fixed to the substrate 101 by other film layers or structures, for example, the support portion 2041 is fixed to the gate insulating layer 103, that is, the support portion 2041 is fixed to the substrate 101 by the gate insulating layer 103. In one embodiment, when the support portion 2041 is fixed on the gate insulating layer 103, opposite voltage signals can be respectively input to the third electrode 201 and the cantilever portion 2041 through independent signal lines, so as to facilitate the control of opening and closing of the semiconductor device.
In some embodiments, as shown in fig. 5, 6, and 7, the cantilever structure 204 includes: a support portion 2041 and a cantilever portion 2042; the support portion 2041 is fixed on the fifth electrode 203, and one end is connected with one end of the cantilever portion 2042; one end of the suspended beam portion 2042 is connected to the other end of the supporting portion 2041, and the other end is suspended.
Unlike the semiconductor device described above, in the semiconductor device provided in the embodiment of the present disclosure, the support portion 2041 of the cantilever structure 204 is connected to the fifth electrode 203 and is fixed on the fifth electrode 203, so that the voltage signal input on the fifth electrode 203 can directly act on the cantilever portion 2042, and the voltage signal on the third electrode 201 is controlled to make the cantilever portion 2042 and the third electrode 201 attract each other, so that it is unnecessary to separately provide a signal line to provide the voltage signal for the cantilever portion 2042 when the semiconductor device is applied to the display substrate, thereby reducing the number of wirings, reducing the wiring difficulty, and improving the manufacturing efficiency.
In one embodiment, the orthographic projection of the cantilever portion 2042 onto the substrate 101 at least partially overlaps with the orthographic projections of the third electrode 201, the fourth electrode 202, and the fifth electrode 203 onto the substrate 101.
In some embodiments, for example, as shown in fig. 4B and 7, the fourth electrode 202 is integrally formed with the second electrode 106.
The fourth electrode 202 and the second electrode 106 are electrically connected together, in the preparation process, the fourth electrode 202 and the second electrode 106 can be made of the same material through one process, and can be in an integrated structure, so that connection wires between the fourth electrode 202 and the second electrode 106 are not needed, the preparation steps are reduced, the preparation cost is saved, a certain gap between the thin film transistor and the switching element can be avoided, the space occupied by the semiconductor device can be reduced, and the aperture ratio of the pixel unit can be improved when the pixel unit is applied to a display substrate.
In some embodiments, for example, as shown in fig. 3A, 4A, and 3B, 4B, the semiconductor device further includes a gate lead 109. For example, the gate lead 109 may be made of the same material as the gate 102, and the gate lead 109 may be formed integrally with the gate 102 by a single process. The gate wire 109 is used to transmit a signal to the gate electrode 102 to control the turning on and off of the thin film transistor in the semiconductor device.
In some embodiments, the cantilever structure 204 is a gold/aluminum/gold laminate structure.
The cantilever structure 204 may be formed by a gold/aluminum/gold stack structure, wherein the thickness of the gold film may be 5nm, the thickness of the aluminum film may be 1um, and the cantilever switching time is about 100ns. The outer layer of gold can prevent the oxidation of the inner layer of aluminum, so that the influence of the oxidation of the suspended beam structure 204 on the conductive effect can be avoided, and the service life of the suspended beam structure 204 can be prolonged.
A process for manufacturing a semiconductor device according to an alternative embodiment of the present application will be described in detail below:
s1, the gate electrode 102 and the third electrode 201 are fabricated on the substrate 101 through a patterning process, and the gate electrode 102 and the third electrode 201 may be fabricated through one process (the film layer including the gate electrode 102 and the third electrode 201 may be referred to as a first conductor layer). The material of the substrate 101 may be glass, and the material of the first conductor layer includes, but is not limited to, molybdenum and/or aluminum, and in this embodiment, the material of the first metal layer may be Mo, and its thickness may be 200nm.
S2, forming the gate 102 and the third electrode 201 by photolithography and etching, and then depositing the gate insulating layer 103 on the whole surface, wherein the material of the gate insulating layer 103 can be SiO 2 . It should be noted that the thickness of the gate insulating layer 103 of the thin film transistor needs to be strictly balanced, and too large a thickness of the gate insulating layer 103 may causeThe regulation capability of the grid electrode 102 is reduced, and the leakage current is increased; too small a thickness of the gate insulating layer 103 increases the risk of breakdown between the source and drain and the gate 102; the thickness of the gate insulating layer 103 in the embodiments of the present disclosure needs to satisfy the on-state current requirement. For example, siO is used 2 As a material of the gate insulating layer 103, the thickness thereof may be 150nm.
S3, preparing an active layer 104. The s-SWCNTs solution used in the examples of the present disclosure may have a purity of less than 80%, a pipe diameter equal to or about equal to 1.55nm, and a length equal to or about equal to 1.5um, and then a glass sample is put into the s-SWCNTs dilution, taken out after 10 hours and dried with nitrogen, put into an oven for heat treatment at 150 ℃ for 30 minutes, and then the carbon tube film is etched using an inductively coupled plasma etching apparatus (ICP: inductively Coupled Plasma) to form the active layer 104, using a s-SWCNTs solution having a concentration of 50ug/ml diluted 15 times with toluene or xylene and performing ultrasonic dispersion in a water area.
S4, the first electrode 105 and the second electrode 106 are fabricated using a patterning process, and the first electrode 105 and the second electrode 106 may be fabricated by one process (the film layer including the first electrode 105 and the second electrode 106 may be referred to as a second conductor layer). Wherein the first electrode 105 and the second electrode 106 are made of titanium metal layers and palladium metal layers sequentially, and the optional thickness range of the titanium metal layers is [5nm,10nm ]; the palladium metal layer has an optional thickness in the range of 15nm,35 nm.
S5, manufacturing a switching element. The sacrificial layer is formed by using a photoresist-coated manner, and the cantilever structure 204 is fabricated using a semi-permeable mask in combination with a photolithographic process. Specifically, after the photolithography process is completed, the sacrificial layer corresponding to the position of the support portion 2041 is completely etched, and the sacrificial layer having a certain thickness is still provided at the position corresponding to the cantilever portion 2042. The cantilever structure 204 is then fabricated using deposition or sputtering of a material that is either an Au/Al/Au stack or a Ti/Al/Ti stack or a Mo/Al/Mo stack. Au/Al/Au stack means a three-stack structure of Au, al, au, the material written in front being closer to the substrate 101 than the material written in back. The Ti/Al/Ti stack and the Mo/Al/Mo stack can be explained in analogy. Wherein the thickness of the Au layer can be 5nm, the thickness of the Ti layer can be 10nm, the thickness of the Mo layer can be 50nm, and the thickness of the Al layer can be 1um. The Au, ti or Mo metal layer serves to prevent oxidation of Al. Finally, the residual sacrificial layer is removed, and the whole semiconductor device is manufactured.
It is understood that the cantilever structure 204 may also be implemented by an electron beam exposure process. In the electron beam exposure process, resist residue can be controlled by controlling electron beam exposure dose at different positions to prepare the support portion 2041 and the cantilever portion 2042.
In a second aspect, embodiments of the present disclosure provide a display substrate including a semiconductor device provided in any one of the embodiments described above. Fig. 8A is a schematic structural diagram of a display substrate according to an embodiment of the disclosure, and fig. 9A is a schematic structural diagram of a cross-section of the display substrate shown in fig. 8A in a C-C' direction, where, as shown in fig. 9A, the display substrate further includes a passivation layer 301 located on a side of the first electrode 105 and the second electrode 106 away from the substrate 101, and a first via 3011 penetrating the passivation layer 301; the front projection of the first via 3011 onto the substrate 101 at least partially overlaps with the front projection of the fourth electrode 202 onto the substrate 101; the front projection of the first via 3011 onto the substrate 101 at least partially overlaps with the front projection of the fifth electrode 203 onto the substrate 101; the front projection of the first via 3011 onto the substrate 101 at least partially overlaps with the front projection of the cantilever structure 204 onto the substrate 101. For ease of illustration, the gate insulating layer 103 and the passivation layer 301 are not shown in fig. 8A.
For example, the passivation layer 301 is an insulating material. Specifically, the passivation layer 301 is made of Y 2 O 3 With Al 2 O 3 Lamination, Y 2 O 3 Compared with Al 2 O 3 Closer to the substrate 101, wherein Y 2 O 3 May have a thickness of 5nm, al 2 O 3 The thickness may be 50nm.
For example, the front projection of the passivation layer 301 onto the substrate 101 at least partially overlaps the front projection of the fourth electrode 202 onto the substrate 101.
For example, the front projection of the passivation layer 301 onto the substrate 101 at least partially overlaps the front projection of the fifth electrode 203 onto the substrate 101.
The passivation layer 301 can prevent the corrosion of each electrode caused by the invasion of gas such as water vapor, and the like, and influence the conductivity. Wherein the first via 3011 may expose the fourth electrode 204 and the fifth electrode 203 to facilitate connection of the fourth electrode 202 and/or the fifth electrode 203 to other structures (e.g., the cantilever structure 204) and signal transmission. It can be understood that the semiconductor device provided in the embodiment of the present disclosure may further include a buffer layer, an interlayer gate insulating layer, a planarization layer, and other film layers, and the arrangement manner of the buffer layer, the interlayer gate insulating layer, the planarization layer, and other film layers may be the same as that of the film layers in the related art, which is not described herein.
For example, the display substrate further includes: the first conductor layer, the second conductor layer and the third conductor layer are positioned on the substrate 101 and are sequentially and insulated along the direction away from the substrate 101; the first conductor layer includes: a gate electrode 102 and a third electrode 201; the second conductor layer includes: a first electrode 105, a second electrode 106, a fourth electrode 202, and a fifth electrode 203; the third conductor layer includes a cantilever structure 204. The structures in the first conductor layer can be made of the same material by adopting a one-time process; the structures in the second conductor layer can be respectively made of the same material and prepared by adopting a one-time process; the structures in the third conductor layer can be respectively made of the same material and prepared by adopting a one-time process; the preparation process can reduce the preparation steps and save the preparation cost.
In some embodiments, the display substrate further comprises: a plurality of Gate lines Gate and a plurality of Data lines Data disposed to cross.
In some embodiments, the plurality of Gate lines Gate are located on the first conductor layer; the plurality of Data lines Data are located in the second conductor layer.
In one embodiment, a plurality of semiconductor devices are arranged in an array; at least part of grid 102 of the semiconductor devices in the same row is electrically connected with the same grid line Gate and is in an integrated structure; specifically, the Gate wire 109 may be a Gate line Gate or the Gate wire 109 may be a portion of the Gate line Gate.
In one embodiment, at least part of the fifth electrodes 203 of the semiconductor devices in the same column are electrically connected to the same Data line Data and are integrally formed.
Specifically, the Gate electrode 102 and the Gate line Gate of the semiconductor device may be made of the same material by a single process, and the fifth electrode 203 and the Data line Data may be made of the same material by a single process, so that the manufacturing steps may be reduced and the manufacturing cost may be saved. In addition, at least part of the grid electrodes 102 of the same row of semiconductor devices are electrically connected with the same grid line Gate and are of an integrated structure, so that the space occupied by the grid electrodes 102 and the grid line Gate can be reduced; at least part of the fifth electrodes 203 of the semiconductor devices in the same row are electrically connected with the same Data line Data and are in an integrated structure, so that the space occupied by the fifth electrodes 203 and the Data line Data can be reduced, the aperture opening ratio of the pixel units is improved, and the display effect is improved. In some embodiments, the display substrate further comprises: the first voltage signal line 401 extends in the same direction as the Gate line Gate. In one embodiment, the first voltage signal line 401 is located in the first conductor layer. In one embodiment, the first voltage signal line 401 is located between adjacent Gate lines Gate. In one embodiment, at least a portion of the third electrodes 201 of the same row of semiconductor devices are electrically connected to the same first voltage signal line 401 and form an integral structure. The first voltage signal line 401 may provide a voltage signal to the third electrode 201, so that the third electrode 201 and the cantilever structure 204 attract each other to control the on and off of the semiconductor device. Thus, the preparation steps can be reduced, and the preparation cost can be saved. At least part of the third electrodes 201 of the same row of semiconductor devices are electrically connected with the same first voltage signal line 401 and are in an integrated structure, so that the space occupied by the third electrodes 201 and the first voltage signal line 401 can be reduced, the aperture opening ratio of the pixel units is improved, and the display effect is improved. In some embodiments, as shown in fig. 8A, 9A, and 8B, 9B, the support portion 2041 of the cantilever structure 204 may be fixed on the fifth electrode 203 to provide a voltage signal to the cantilever structure 204 through the fifth electrode 203.
In one embodiment, as shown in fig. 8B and fig. 9B, a plurality of the semiconductor devices are arranged in an array; at least part of the fifth electrodes 203 of the semiconductor devices in the same column are electrically connected with the same Data line Data, the supporting portion 2041 of the cantilever structure 204 is fixed on the fifth electrodes 203, and the Data line Data and the supporting portion 2041 are an integrated structure. Specifically, the Data line Data may be located in the third conductor layer and may be prepared in the same process as the suspended beam structure 204, so that the preparation steps are reduced and the preparation cost is saved while the space occupied by the Data line Data is reduced. For ease of illustration, the gate insulating layer 103 and the passivation layer 301 are not shown in fig. 8B.
In some embodiments, fig. 10 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure, fig. 11 is a schematic structural diagram of a cross-section of the display substrate shown in fig. 10 in a D-D' direction, and the display substrate shown in fig. 10 is different from the display substrates shown in fig. 8A and 8B in that the display substrate further includes: a second voltage signal line 402 extending in the same direction as the Gate line Gate; alternatively, on the extended surface of the substrate 101, the second voltage signal line 402 is located between the first voltage signal line 401 and the Gate line Gate corresponding to the adjacent row. Preferably, the second voltage signal line 402 is located in the third conductor layer. Specifically, at least part of the cantilever structures 204 of the same row of semiconductor devices are electrically connected to the same second voltage signal line 402 and are integrally formed. It should be noted that the extended surface of the substrate 101 may be understood as a surface perpendicular to the thickness direction of the substrate 101.
The first voltage signal line 401 may provide a voltage signal to the third electrode 201, and the second voltage signal line 402 may provide a voltage signal to the cantilever structure 204, so that the third electrode 201 and the cantilever structure 204 attract each other to control the turn-on of the semiconductor device. Accordingly, the support portion 2041 of the cantilever structure 204 may be fixed on the passivation layer 301. At least part of the cantilever structures 204 of the semiconductor devices in the same row are electrically connected with the same second voltage signal line 402 and are in an integrated structure, so that the space occupied by the cantilever structures 204 and the second voltage signal line 402 can be reduced, the aperture opening ratio of the pixel unit can be improved, and the display effect can be improved. Preferably, at least part of the third electrodes 201 of the same row of semiconductor devices are electrically connected to the same first voltage signal line 401 and are integrally formed. For ease of illustration, the gate insulating layer 103 and the passivation layer 301 are not shown in fig. 10 for ease of illustration.
In some embodiments, the supporting portion 2041 of the suspended beam structure 204 may be multiplexed as a part of the second voltage signal line 402, in which case, the suspended beam portion 2042 may be directly connected to the second voltage signal line 402, so as to further save the space occupied by the suspended beam structure 204 and improve the aperture ratio.
In some embodiments, as shown in fig. 8-11, the display substrate further includes a second via 3012 extending through the passivation layer 301, the orthographic projection of the second via 3012 on the substrate 101 at least partially overlapping with the orthographic projection of the first electrode 105 on the substrate 101; the second via 3012 may expose the first electrode 105 so that the first electrode 105 is electrically connected to other structures and performs signal transmission. In a specific embodiment, the display substrate further comprises a pixel electrode 107. The pixel electrode 107 may be electrically connected to the first electrode 105 through the second via 3012. Optionally, the pixel electrode 107 is located on the third conductor layer. Preferably, the pixel electrode 107 and the cantilever structure 204 are made of the same material through one process to reduce the process cost.
In a third aspect, the present disclosure provides a display device, which includes a display substrate provided in any one of the foregoing embodiments, where the display device may be, for example, an electronic device having a display function, such as a mobile phone, a tablet computer, an electronic watch, a sports bracelet, a notebook computer, or the like. The implementation principle and technical effect of the display device can be referred to the above discussion of the implementation principle and technical effect of the display substrate and the semiconductor device, and will not be repeated here.
It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.

Claims (15)

1. A semiconductor device, comprising: a substrate, a thin film transistor and a switching element on the substrate;
the thin film transistor includes: a gate electrode, a gate insulating layer, an active layer, a first electrode as a drain electrode, and a second electrode as a source electrode; the first electrode and the second electrode are respectively connected with the active layer;
the switching element includes: a third electrode on the substrate; the switching element further includes: the fourth electrode, the fifth electrode and the cantilever beam structure are respectively positioned at two sides of the third electrode and are suspended on the third electrode; wherein the fourth electrode is electrically connected with the second electrode;
the orthographic projection of the cantilever structure on the substrate is at least partially overlapped with the orthographic projections of the third electrode, the fourth electrode and the fifth electrode on the substrate;
The grid electrode is connected with the third electrode through different signal lines;
the cantilever structure includes: a support portion and a cantilever portion;
the supporting part is fixed on the substrate or the fifth electrode, and one end of the supporting part is connected with one end of the cantilever part;
one end of the cantilever beam part is connected with one end of the supporting part, and the other end of the cantilever beam part is suspended;
when the supporting part is fixed on the substrate, the thin film transistor is in a closed state, and the other end of the cantilever part is contacted with the fourth electrode and the fifth electrode; when the supporting part is fixed on the fifth electrode, the thin film transistor is in a closed state, and the other end of the cantilever part is only contacted with the fourth electrode.
2. The semiconductor device according to claim 1, wherein the gate insulating layer extends to a region where the switching element is located, wherein the gate insulating layer is hollowed out at the third electrode position, the gate insulating layer is located between the fourth electrode and the substrate, and the gate insulating layer is located between the fifth electrode and the substrate.
3. The semiconductor device of claim 1, wherein the fourth electrode and the second electrode are of an integrally formed structure.
4. The semiconductor device of claim 1, wherein the cantilever structure is a gold/aluminum/gold stack structure.
5. The semiconductor device of claim 1, wherein the material of the active layer comprises: a carbon nanotube material.
6. A display substrate comprising the semiconductor device according to any one of claims 1 to 5.
7. The display substrate of claim 6, further comprising: the passivation layer is positioned on one side of the first electrode and the second electrode away from the substrate, and the first via penetrates through the passivation layer;
the orthographic projection of the first via hole on the substrate at least partially overlaps with the orthographic projection of the fourth electrode on the substrate;
the orthographic projection of the first via hole on the substrate at least partially overlaps with the orthographic projection of the fifth electrode on the substrate;
the orthographic projection of the first via on the substrate at least partially overlaps with the orthographic projection of the cantilever structure on the substrate.
8. The display substrate of claim 6, further comprising: the first conductor layer, the second conductor layer and the third conductor layer are positioned on the substrate and are sequentially and insulated along the direction deviating from the substrate;
The first conductor layer includes: the grid electrode and the third electrode;
the second conductor layer includes: the first electrode, the second electrode, the fourth electrode, and the fifth electrode;
the third conductor layer includes: the cantilever beam structure.
9. The display substrate of claim 8, wherein the display substrate further comprises: a plurality of gate lines and a plurality of data lines disposed to cross.
10. The display substrate according to claim 9, wherein a plurality of the semiconductor devices are arranged in an array;
at least part of the grid electrodes of the semiconductor devices in the same row are electrically connected with the same grid line and are of an integrated structure;
at least part of the fifth electrodes of the semiconductor devices in the same column are electrically connected with the same data line and are in an integrated structure, or when the supporting parts are fixed on the fifth electrodes, at least part of the fifth electrodes of the semiconductor devices in the same column are electrically connected with the same data line, and the data line and the supporting parts are in an integrated structure.
11. The display substrate of claim 9, wherein the display substrate further comprises: a first voltage signal line having the same direction as the gate line; the first voltage signal line is positioned between the adjacent grid lines;
The first conductor layer further includes: the first voltage signal line.
12. The display substrate according to claim 11, wherein at least part of the third electrodes of the semiconductor devices in the same row are electrically connected to the same first voltage signal line and are integrally formed.
13. The display substrate of claim 11, wherein the display substrate further comprises: a second voltage signal line having the same direction as the gate line;
the third conductor layer further includes: the second voltage signal line.
14. The display substrate according to claim 13, wherein at least part of the cantilever structures of the semiconductor devices in the same row are electrically connected to the same second voltage signal line and are integrally formed.
15. A display device comprising a display substrate according to any one of claims 6-14.
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