JP2007134482A - Thin film transistor device, its manufacturing method, thin film transistor array using the same and thin film transistor display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor device which has a large on current, a small off current, and a good characteristic at a decreased frequency of photolithography at a low cost, and further to provide a thin film transistor array using this thin film transistor device, and a thin film transistor display with a stable image at a light weight. <P>SOLUTION: In this structure, a source electrode is formed as a substantially independent island pattern as seen from a vertical direction with respect to an insulating substrate, a drain electrode surrounds it, and a gate electrode contains their gaps. Thus, the off-current is reduced between the source electrode and the drain electrode by a gate potential. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a thin film transistor device used for an image display device and the like, a manufacturing method thereof, and a thin film transistor array and a thin film transistor display using the thin film transistor device.

A thin film transistor (Thin Film Transistor: TFT) of amorphous silicon (a-Si) or polysilicon is manufactured on a glass substrate on the basis of a transistor using a semiconductor itself as a substrate and integrated circuit technology, and is applied to a liquid crystal display.

In these transistors, the semiconductor layer in the operating region is formed by performing photo-etching after forming a silicon film by CVD or PVD, so that the process is complicated and the manufacturing cost is inevitable. .

An example of a conventional TFT display device is shown in FIGS. FIG. 17 is a plan view, and FIG. 18 is a cross-sectional view taken along line E-E '.

The outline of the manufacturing method of this display device will be described. First, the gate electrode 2 and the capacitor lower electrode 10 are formed on the insulating substrate 1 by metal film formation, photolithography, and etching.

Next, the SiNx insulating layer 3 and the semiconductor layer 6 made of amorphous silicon (a-Si) are formed by plasma CVD.
A thin n + doping layer 6 'is formed on the top of amorphous silicon (a-Si).
Then, the semiconductor layer 6 made of a-Si is patterned into an island shape by photolithography.

Next, an ITO (Indium Tin Oxide) film is formed as the pixel electrode 8 and patterned into a predetermined shape by photolithography and etching.

Next, a metal film for the source electrode 4 and the drain electrode 5 is formed, patterned by photolithography and etching, and the n + -Si layer in the channel portion is etched.

As described above, the current semiconductor manufacturing process uses a vacuum process and a photo process many times, and the apparatus becomes large, so that the manufacturing cost is high.

In recent years, IC cards, RFID tags, and the like have attracted attention.
For these, semiconductor devices are used.
Semiconductor devices are becoming more and more multifunctional year by year, but conversely, they are becoming thinner and lighter, and in order to achieve this, integration in a limited space and thinner elements are required. .

If the substrate used in the semiconductor device is thinned to reduce the thickness, the element is easily broken. For example, an IC card is stored and carried in a card holder or a wallet, but is often broken by being bent or twisted by an external force in a pocket or a bag.
In addition, wire bonding wiring often breaks due to bending or twisting.

Recently, TFTs using oxide semiconductors and organic semiconductors have appeared, and the formation temperature of the semiconductor layer can be lowered from room temperature to about 200 ° C., so that it is possible to use a plastic substrate, and a lightweight and flexible display. Is expected to be obtained at low cost (see, for example, Patent Document 1).

However, in the shape of the conventional semiconductor device (FIG. 17), the upper limit of the channel width is the length of one side of the pixel, and the on-current cannot be increased.

In addition, since a leakage current flows between the source electrode and the drain electrode or between other pixels, the off current cannot be reduced.

Alternatively, in order to increase the on-current, it is necessary to reduce the channel length, the off-current increases, the variation in semiconductor characteristics due to the variation in channel length increases, and there is a risk of a short circuit between the source electrode and the drain electrode. Rise.

As described above, in the shape of the conventional semiconductor device, the on-current cannot be increased and the off-current cannot be decreased, and it is difficult to obtain good characteristics.

In addition, in the conventional semiconductor device, there is a problem that electric charges leak even when the TFT is in an off state. In addition, charge may leak inside the capacitance, but leakage from the TFT is generally about one digit larger.
When this leak is severe, a phenomenon called flicker occurs in which the brightness of an image changes at the same cycle as the frame frequency.

By the way, in the TFT having the top gate structure, the leak current is generated at the portion where the edge portion of the semiconductor layer of the TFT intersects with the gate electrode.
As a cause of this, the gate electrode causes the source electrode and the drain electrode to be short-circuited due to poor insulation of the gate electrode at this edge portion.
Alternatively, the periphery of the semiconductor layer may not have a crystal structure due to damage caused by etching or ion doping.

In order to obtain a TFT with a small leakage current, a liquid crystal display including a TFT in which a source electrode and a gate electrode are arranged in a circular shape has been proposed (for example, see Patent Document 2). As shown in FIG. 19, in the thin film transistor of this liquid crystal display, the gate electrode 502 is disposed so as to surround the source electrode 501, and the drain electrode 503 is disposed outside the gate electrode 502 so as to substantially surround the gate electrode 502. Have a structure.

In the figure, reference numeral 504 denotes a semiconductor layer.
In other words, electrodes having a substantially similar outer shape of the TFT are arranged concentrically on the semiconductor layer. A gate electrode and an electrode having a part of a ring are disposed so as to surround the outer side of the circular electrode.

The electrode having a shape lacking a part of the ring is arranged in a layer different from the wiring metal constituting the gate electrode, and the two electrodes are made of the same wiring metal.
As a result, since the edge portion of the semiconductor layer does not exist on the line connecting the source electrode and the drain electrode, the drain electrode and the source electrode are not short-circuited by the gate electrode. It is said that can be reduced.
This phenomenon is peculiar to a TFT having a top gate structure when it has a patterned semiconductor layer.

As a technique that eliminates the need for semiconductor patterning, there is a structure in which an operation layer is provided around a source (or drain), a drain electrode (or source electrode) is provided around the source layer (or drain), and a shielding electrode is provided around the operation layer (for example, Patent Document 3). reference).
However, since silicon is used as a semiconductor, ion implantation and etching for forming a contact layer are necessary. Even if patterning of a semiconductor is not required, a corresponding process remains, which is still complicated. .
Further, the shielding electrode complicates the structure.

Republished patent WO 98-29261 Japanese Patent Laid-Open No. 08-160469 JP 08-139336 A

An object of the present invention is to provide a thin film transistor device having a large on-state current and a small off-state current and having good characteristics with little variation.
Another object of the present invention is to provide a thin film transistor device at a low cost by reducing the number of times of photolithography.
A further object of the present invention is to provide a thin film transistor array using the thin film transistor device as described above, thereby providing a light and thin thin film transistor display having a stable image.

According to the first aspect of the present invention, at least a gate electrode formed on an insulating substrate, a capacitor lower electrode, a gate insulating film formed thereon, and a source formed on the gate insulating film A thin film transistor device having an electrode, a drain electrode, a capacitor upper electrode, and a semiconductor layer connecting the source electrode and the drain electrode, wherein the shape viewed from a direction perpendicular to the insulating substrate is an isolated island pattern The source electrode, a C-shaped drain electrode viewed from a direction perpendicular to the insulating substrate so as to substantially surround the source electrode, the source electrode and the source electrode viewed from a direction perpendicular to the insulating substrate The gate electrode disposed so as to include a gap between the drain electrodes, and the presence of the drain electrode when viewed from a direction perpendicular to the insulating substrate; It is a thin film transistor device according to claim in which the source electrode and the capacitor upper electrode is connected by a wiring disposed in free portion.

The invention according to claim 2 includes at least a gate electrode formed on an insulating substrate, a capacitor lower electrode, a gate insulating film formed thereon, and a source formed on the gate insulating film. An electrode, a drain electrode, and a capacitor upper electrode; a semiconductor layer connecting the source electrode and the drain electrode; an interlayer insulating film formed thereon; and a via hole penetrating the interlayer insulating film to form the source electrode or A thin film transistor device having the pixel electrode connected to the capacitor upper electrode, the source electrode having a substantially isolated island pattern as viewed from a direction perpendicular to the insulating substrate, and substantially surrounding the source electrode A C-shaped drain electrode viewed from the direction perpendicular to the insulating substrate, and the source electrode viewed from the direction perpendicular to the insulating substrate. And the gate electrode disposed so as to include a gap between the drain electrodes, and when viewed from a direction perpendicular to the insulating substrate, the source electrode and a wiring disposed in a portion where the drain electrode does not exist A thin film transistor device having a capacitor upper electrode connected thereto.

According to a third aspect of the present invention, in the thin film transistor device according to the first or second aspect, the source electrode has a quadrangular shape when viewed from a direction perpendicular to the insulating substrate.

According to a fourth aspect of the present invention, the capacitor upper electrode has an isolated island pattern and the capacitor lower electrode is larger than the capacitor upper electrode and includes the capacitor upper electrode when viewed from a direction perpendicular to the insulating substrate. The thin film transistor device according to any one of claims 1 to 3, wherein the thin film transistor device is formed as described above.

The invention according to claim 5 is the thin film transistor device according to any one of claims 1 to 4, wherein the semiconductor layer is made of an oxide semiconductor or an organic semiconductor.

A sixth aspect of the present invention is the thin film transistor device according to any one of the first to fifth aspects, wherein the semiconductor layer is formed over the entire surface of the insulating substrate.

A seventh aspect of the present invention is a thin film transistor array in which a plurality of thin film transistor devices according to any one of the first to sixth aspects are arranged in a matrix on an insulating substrate. This thin film transistor device is electrically connected by a gate wiring, a drain wiring and a capacitor wiring.

The invention according to claim 8 is a thin film transistor display using the thin film transistor array according to claim 7.

The invention according to claim 9 is a gate electrode and capacitor lower electrode forming step of forming a gate electrode and a capacitor lower electrode made of a conductive film on an insulating substrate,
A gate insulating film forming step of forming a gate insulating film on the gate electrode and the capacitor lower electrode;
A source electrode formed of a conductive film on the gate insulating film, a drain electrode, a source electrode for forming a capacitor upper electrode, a drain electrode, a capacitor upper electrode forming step;
A semiconductor layer forming step of forming a semiconductor layer in contact with the gate insulating film, the source electrode, and the drain electrode;
Forming an interlayer insulating film having an opening on the source electrode or the upper capacitor electrode on the semiconductor layer, the source electrode, the drain electrode, and the gate insulating film;
A method of manufacturing a thin film transistor device having a pixel electrode forming step of forming a pixel electrode on the opening and the interlayer insulating film, the step of forming a semiconductor layer, and forming the source electrode, drain electrode, and capacitor upper electrode At least one of the step, the step of forming the interlayer insulating film, and the step of forming the pixel electrode is a printing method.

When viewed from the direction perpendicular to the insulating substrate, the source electrode has a substantially isolated island pattern, the drain electrode surrounds it, and the gate electrode includes the gap between them. The off-state current can be reduced.

Further, when viewed from the direction perpendicular to the insulating substrate, the capacitor upper electrode has a substantially isolated island pattern, and the capacitor lower electrode is larger than the capacitor upper electrode and includes the capacitor upper electrode. Thus, a thin film transistor device is provided.
This is because the capacitor lower electrode shuts out the current flowing into the capacitor upper electrode.
The source electrode and the capacitor upper electrode are connected only at the chipped portion of the C-shaped drain electrode, and the current flow into this connection is very small.
As a result, it is possible to provide a thin film transistor device having low characteristics and low off-state current.

Further, in the thin film transistor device of the present invention, as viewed from the direction perpendicular to the insulating substrate, the source electrode is square, the gate electrode is square-shaped, and the drain electrode is partly square-shaped. A thin film transistor device having a C-shape was obtained.
With such a structure, the source electrode and the channel width can be increased, and a thin film transistor device having a large on-state current can be obtained.

In the thin film transistor device of the present invention, the semiconductor layer is preferably made of an oxide semiconductor or an organic semiconductor.
Oxide semiconductors and organic semiconductors do not require processes such as ion implantation required for silicon semiconductors, and the process is simple.
In addition, since low temperature film formation is possible, a thin film transistor can be formed over a plastic substrate.

Here, the oxide semiconductor and the organic semiconductor are generally unipolar, the oxide semiconductor is usually n-channel, the organic semiconductor is usually p-channel, and the opposite carrier can be ignored.
Therefore, if n is applied to the gate and the capacitor lower electrode in the n-channel TFT and + is applied to the gate and the capacitor lower electrode in the p-channel TFT, carriers are not induced around the channel portion and the capacitor upper electrode, and the off-current Can be reduced.
The semiconductor layer may be formed not only on the channel portion between the source electrode and the drain electrode but also on the entire surface.
The fact that the semiconductor layer may be formed on the entire surface eliminates the need for a patterning process and simplifies the process.
In addition to being able to be manufactured by a method such as spin coating or die coating that cannot be patterned, even when a patternable method such as inkjet is used, it is not necessary to strictly align alignment and manufacturing conditions.

The thin film transistor array of the present invention is formed by arranging a plurality of thin film transistor devices of the present invention in a matrix on an insulating substrate and electrically connecting the plurality of thin film transistor devices by gate wiring, drain wiring and capacitor wiring. is there.

The thin film transistor display of the present invention is a display using a thin film transistor array, for example, the thin film transistor array and the counter substrate are bonded together by a substantially rectangular frame-shaped sealing material when viewed from the vertical direction with respect to the insulating substrate, A liquid crystal layer is sealed in a region surrounded by the sealing material.

In addition, since the thin film transistor display of the present invention uses the thin film transistor device of the present invention, there is an advantage that an image is stable, and a thin and lightweight display is provided at low cost.

A method of manufacturing a thin film transistor device according to the present invention includes a gate electrode and capacitor lower electrode forming step of forming a gate electrode and a capacitor lower electrode made of a conductive film on an insulating substrate,
A gate insulating film forming step of forming a gate insulating film on the gate electrode and the capacitor lower electrode;
A source electrode formed of a conductive film on the gate insulating film, a drain electrode, a source electrode for forming a capacitor upper electrode, a drain electrode, a capacitor upper electrode forming step;
A semiconductor layer forming step of forming a semiconductor layer in contact with the gate insulating film, the source electrode, and the drain electrode;
Forming an interlayer insulating film having an opening on the source electrode or the upper capacitor electrode on the semiconductor layer, the source electrode, the drain electrode, and the gate insulating film;
A method of manufacturing a thin film transistor device having a pixel electrode forming step of forming a pixel electrode on the opening and the interlayer insulating film, the step of forming a semiconductor layer, and forming the source electrode, drain electrode, and capacitor upper electrode At least one of the step, the step of forming the interlayer insulating film, and the step of forming the pixel electrode can be performed by printing.

Specifically, ink jetting can be used in the step of forming a semiconductor. Here, it is not essential to pattern each pixel.
This is because if the gate electrode, source electrode, and drain electrode of the present invention are used, the off current can be reduced even if the semiconductor is not patterned.
Screen printing, gravure printing, flexographic printing, offset printing, reversal printing, or the like can be used for forming the source electrode, drain electrode, and capacitor upper electrode.
Screen printing can also be used for interlayer insulating films and pixel electrodes.
According to such a manufacturing method, a thin film transistor device including an effective capacitor with little leakage current can be reliably manufactured.
If the printing method is adopted, a pattern can be formed only in a necessary portion, so that the manufacturing process is greatly reduced, and a large amount can be manufactured at low cost.

In the present invention, a thin film transistor device with reduced off-current can be obtained by surrounding the source electrode with a gate electrode in a substantially isolated island pattern.

In the present invention, since the source electrode is square, the source electrode and the channel width can be increased, so that a thin film transistor device with a large on-current can be obtained.

Further, according to the present invention, since the number of times of photolithography can be reduced, an inexpensive thin film transistor device can be provided.

Furthermore, according to the present invention, a thin, thin-film transistor display with stable images can be obtained.

A thin film transistor device and a thin film transistor array of the present invention will be described with reference to FIGS.
FIG. 1 is a plan view showing one pixel region of a thin film transistor array, and FIG. 2 is a cross-sectional view taken along line AA ′.

In the thin film transistor device 50, the source electrode 4 has a substantially isolated island pattern, the drain electrode 5 has a C shape substantially surrounding the gate electrode 2, and the gate electrode 2 is the source electrode as viewed from the direction perpendicular to the insulating substrate. 4 and the drain electrode 5 are formed to include the gap.
The source electrode 4 has a quadrangular shape, and the drain electrode 5 has a rectangular C shape with a uniform width. The source electrode 4 and the capacitor upper electrode 11 are connected to each other at the notch of the drain electrode.
The capacitor upper electrode 11 is included in the capacitor lower electrode when viewed from the direction perpendicular to the insulating substrate.

When viewed from the horizontal direction with respect to the insulating substrate, the gate electrode 2 and the capacitor lower electrode 10 are formed on the insulating substrate 1, and the top is covered with the gate insulating film 3.
A source electrode 4, a drain electrode 5, and a capacitor upper electrode 11 are formed thereon.
A semiconductor layer 6 is formed at least in a channel portion between the source electrode 4 and the drain electrode 5 to form a transistor.
The semiconductor layer 6 may be formed on the entire surface.

4, 5, 7, and 8, an interlayer insulating film 7 is formed on FIGS. 1 and 2, a pixel electrode 8 is formed thereon, and a via hole in the interlayer insulating film 7 is formed. 9, the pixel electrode 8 and the source electrode 4 or the capacitor upper electrode 11 are connected.

As described above, the source electrode 4 is formed in an isolated island pattern when viewed from the direction perpendicular to the insulating substrate, the drain electrode 5 surrounds it, and the gate electrode 2 includes the gap therebetween. The off-current between 4 and the drain electrode 5 can be reduced.

In addition, since the capacitor upper electrode is included in the capacitor lower electrode when viewed from the direction perpendicular to the insulating substrate, the current flowing into the capacitor upper electrode by appropriately setting the potential of the capacitor lower electrode (also off-state current) Cause) can be suppressed.

By doing so, the cause of the off-current is mainly the current flowing into the connection portion 12, and this also increases the shape of the gate electrode 2 on the side of the notch portion of the drain electrode 5, that is, FIG. As shown in FIG. 7, it can be suppressed by extending to the outside of the drain electrode 5.

Further, the source electrode 4 has a rectangular shape, the drain electrode 5 has a rectangular C shape surrounding the source electrode 4, and the gate electrode 2 has a shape including the gap between the source electrode 4 and the drain electrode 5. The channel width can be increased.
Since the channel width is large, the on-current can be increased.
Alternatively, by increasing the channel width, the channel length can be increased without reducing the on-current, the off-current can be reduced, and the variation in channel length can be reduced, so that the gap between the source electrode 4 and the drain electrode 5 can be reduced. Can reduce the risk of short circuit.

(First embodiment)
An example of a method for forming a thin film transistor device according to the first embodiment of the present invention will be described with reference to FIGS.

First, the gate electrode 2 and the capacitor lower electrode 10 are formed on the insulating substrate 1. (Fig. 3 (a))

In addition to quartz and glass, the insulating substrate 1 may be made of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polyimide (PI), polyetherimide (PEI), polystyrene (PS). ), Polyvinyl chloride (PVC), polyethylene (PE), polypropylene (PP), nylon (Ny), and other plastics.
These plastic substrates have the advantage that they can be used as an insulating substrate in the form of a thin film.

As a material of the gate electrode 2 and the capacitor lower electrode 10, a metal film having good conductivity such as Al, Cr, Au, Ag, Cu, Ti, Ni, or a transparent conductive film such as ITO can be used.

As a method for forming the gate electrode 2 and the capacitor lower electrode 10, an evaporation method, a sputtering method, or the like can be used.

In addition, as a material for the gate electrode 2 and the capacitor lower electrode 10, conductive ink such as Ag ink, Ni ink Cu ink, or the like can be used.

As a method for forming the gate electrode 2 and the capacitor lower electrode 10 at this time, Ag ink, Ni ink, and Cu ink are used by screen printing, flexographic printing, gravure printing, offset printing, reversal printing, and the like. A method of firing after printing can be used.

Next, the gate insulating film 3 is formed on the insulating substrate 1, the gate electrode 2, and the capacitor lower electrode 10. (Fig. 3 (b))

As a material of the gate insulating film 3, inorganic substances such as SiN, SiO ₂ and Al ₂ O ₃ and organic substances such as polyvinyl phenol, epoxy and polyimide can be used.

As a method for forming the gate insulating film 3, a CVD method or a PVD method can be used for forming the inorganic material film, and a spin coating method or a printing method such as inkjet printing can be used for forming the organic material film.

Next, the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11 are formed on the gate insulating film 3. (Fig. 3 (c))

As a material for the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11, a metal film having good conductivity such as Al, Cr, Au, Ag, Cu, Ti, Ni, or a transparent conductive film such as ITO is used. it can.

As a method for forming the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11, a vapor deposition method or a sputtering method can be used.

In addition, as a material for the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11, a conductive paste such as an Ag paste, Ni paste, or Cu paste can be used.

At this time, the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11 can be formed by using Ag paste, Ni paste, or Cu paste by screen printing, flexographic printing, gravure printing, offset printing, and reversal printing. The method of baking after printing using the method etc. can be used.

Next, a semiconductor layer 6 is formed on the gate insulating film 3, the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11 to obtain a thin film transistor device. (Fig. 3 (d))

Examples of the material for the semiconductor layer 6 include InGaZnO-based, InZnO-based, ZnGaO-based, InGaO-based, ZnO, SnO ₂ and In ₂ O ₃ oxides of one or more, polythiophene derivatives, polyphenylene vinylene derivatives, polythieny. Organic substances such as a lembinylene derivative, a polyallylamine derivative, a polyacetylene derivative, an acene derivative, and an oligothiophene derivative can be used.

As a manufacturing method of the semiconductor layer 6, a method of forming an oxide film by metal organic chemical vapor deposition, sputtering, or laser ablation, a method of baking after applying an oxide raw material, or applying an organic raw material is applied. A method of baking later or a method of depositing an organic substance can be used.

When an oxide semiconductor or an organic semiconductor is formed, a printing method can be used, and a temperature required for forming a semiconductor layer is 200 ° C. or lower, which has an advantage that a plastic film can be used as an insulating substrate.

Next, an interlayer insulating film 7 is formed on the semiconductor layer 6. (Fig. 3 (e))

As a material of the interlayer insulating film 7, inorganic substances such as SiN, SiO ₂ and Al ₂ O ₃ and organic substances such as polyvinyl phenol, epoxy and polyimide can be used.

As a method for forming the interlayer insulating film 7, a CVD method or a PVD method can be used for forming the inorganic material film, and a spin coating method, a printing method such as inkjet printing or screen printing can be used for forming the organic material film. .

Next, a hole for a via hole 9 is formed in the interlayer insulating film 7. (See FIG. 6 (e) and FIG. 9 (e))

As a method for forming a hole for the via hole 9, a method of processing a UV-YAG laser beam on the interlayer insulating film 7, a method of exposing and developing using a photosensitive resin for the interlayer insulating film 7, and an interlayer insulating film having a hole are used. A screen printing method can be used.
Particularly, screen printing is preferable because it can be easily and thickly patterned at low cost, and the interlayer insulating film 7 and the hole for the via hole 9 can be formed simultaneously.

Finally, a pixel electrode 8 was formed on the interlayer insulating film 7 to obtain a thin film transistor device. (Fig. 5)

As a material of the pixel electrode 8, Al, Ag, Ag ink, Ni ink, Cu ink, or the like can be used.

As a method for forming the pixel electrode 8, a method of sputtering Al or Ag, or a method of screen printing Ag ink, Ni ink, or Cu ink can be used.

It is also possible to use the source electrode 4 and the upper capacitor electrode 11 as a substitute for the pixel electrode without forming the interlayer insulating film 7 and the pixel electrode 8.

An image display display such as a liquid crystal display can be manufactured using such a TFT.
For example, an oxide semiconductor is used for the semiconductor layer 6, a transparent electrode such as ITO is used for the gate electrode 2, the capacitor lower electrode 10, the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11, and SiO ₂ or the like is used for the gate insulating film 3. A thin film transistor display having a large aperture ratio can be manufactured by using an inorganic substance and a transparent epoxy resin or polyimide resin for the interlayer insulating film 7.
Moreover, TFT used for a non-transparent guest-host liquid crystal display etc. can be obtained by using Ag paste for the source electrode 4 and the drain electrode 5 or the like.

(Second Embodiment)
An example of a method for forming a thin film transistor device according to the second embodiment of the present invention will be described with reference to FIGS.
FIG. 10 is a plan layout view showing one pixel region of the thin film transistor array, and FIG. 11 is a cross-sectional view taken along line DD ′.

The thin film transistor device 60 according to the second embodiment is different from the thin film transistor device 50 according to the first embodiment in the cross-sectional structure.
The thin film transistor device 60 of the second embodiment viewed from the direction perpendicular to the insulating substrate is the same as the thin film transistor device 50 shown in the first embodiment.

First, the gate electrode 2 and the capacitor lower electrode 10 are formed on the insulating substrate 1. (Fig. 12 (a))

In addition to quartz and glass, the insulating substrate 1 may be made of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polyimide (PI), polyetherimide (PEI), polystyrene (PS). ), Polyvinyl chloride (PVC), polyethylene (PE), polypropylene (PP), nylon (Ny), and other plastics.
These plastic substrates have the advantage that they can be used as an insulating substrate in the form of a thin film.

As a material of the gate electrode 2 and the capacitor lower electrode 10, a metal film having good conductivity such as Al, Cr, Au, Ag, Cu, Ti, Ni, or a transparent conductive film such as ITO can be used.

As a method for forming the gate electrode 2 and the capacitor lower electrode 10, vapor deposition, sputtering, or the like can be used.

In addition, as a material for the gate electrode 2 and the capacitor lower electrode 10, conductive ink such as Ag ink, Ni ink, or Cu ink can be used.

As a method for forming the gate electrode 2 and the capacitor lower electrode 10 at this time, a screen printing method, a flexographic printing method, a gravure printing method, an offset printing method, a reverse printing method, or the like is used for Ag ink, Ni ink, Cu ink, or the like. The method of baking after printing can be used.

Next, the gate insulating film 3 is formed on the insulating substrate 1, the gate electrode 2, and the capacitor lower electrode 10. (Fig. 12 (b))

As a material of the gate insulating film 3, inorganic substances such as SiN, SiO ₂ and Al ₂ O ₃ and organic substances such as polyvinyl phenol, epoxy and polyimide can be used.

As a method for forming the gate insulating film 3, a CVD method or a PVD method can be used for forming the inorganic material film, and a spin coating method or a printing method such as inkjet printing can be used for forming the organic material film.

Next, the semiconductor layer 6 is formed on the gate insulating film 3. (Fig. 12 (c))

Examples of the material for the semiconductor layer 6 include InGaZnO-based, InZnO-based, ZnGaO-based, InGaO-based, ZnO, SnO ₂ and In ₂ O ₃ oxides of one or more, polythiophene derivatives, polyphenylene vinylene derivatives, polythieny. Organic substances such as a lembinylene derivative, a polyallylamine derivative, a polyacetylene derivative, an acene derivative, and an oligothiophene derivative can be used.

As a manufacturing method of the semiconductor layer 6, a method of forming an oxide film by metal organic chemical vapor deposition, sputtering, or laser ablation, a method of baking after applying an oxide raw material, or applying an organic raw material is applied. A method of baking later or a method of depositing an organic substance can be used.

When an oxide semiconductor or an organic semiconductor is formed, a printing method can be used, and a temperature required for forming a semiconductor layer is 200 ° C. or lower, which has an advantage that a plastic film can be used as an insulating substrate.

Next, the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11 are formed on the semiconductor layer 6. (Fig. 12 (d))

As a material for the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11, a metal film having good conductivity such as Al, Cr, Au, Ag, Cu, Ti, Ni, or a transparent conductive film such as ITO is used. it can.

As a method for forming the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11, an evaporation method, a sputtering method, or the like can be used.

In addition, as a material for the source electrode 4, the drain electrode 5, and the capacitor upper electrode 11, conductive ink such as Ag ink, Ni ink, Cu ink can be used.

At this time, the source electrode 4, drain electrode 5, and capacitor upper electrode 11 are formed by screen printing, flexographic printing, gravure printing, offset printing, reverse printing using Ag ink, Ni ink, Cu ink or the like. A method of firing after printing using a method or the like can be used.

Further, an interlayer insulating film 7 and a pixel electrode 8 may be provided. (Fig. 14)

(Third embodiment)
FIG. 15 is a diagram showing a planar configuration of the thin film transistor array 80 of the present invention.
In the thin film transistor array 80 of the present invention, a plurality of thin film transistor devices 50 of the present invention are arranged in a matrix on an insulating substrate 1, and the plurality of thin film transistor devices 50 are connected to a gate wiring 2 ', a drain wiring 5' and a capacitor wiring. 10 'electrically connected.

(Fourth embodiment)
FIG. 16 is a sectional view showing a guest-host liquid crystal display 90 which is a kind of thin film transistor display of the present invention.

In the guest-host liquid crystal display 90 of the present invention, a thin film transistor array 80 including the thin film transistor device 60 according to the second embodiment, and a counter substrate 81 composed of the transparent substrate 13 and the counter electrode 14 have a substantially rectangular frame shape in plan view. The guest host liquid crystal layer 15 is sealed in a region surrounded by a sealing material (not shown) and surrounded by the sealing material.

Since the guest-host liquid crystal display 90 of the present invention uses the thin film transistor device of the present invention, there is an advantage that an image is stable and a thin and light-weight one is provided at low cost. The same applies to the thin film transistor according to the first embodiment.

First, a polyethylene naphthalate (PEN) having a thickness of 125 μm was prepared, and Al was formed on the entire surface by sputtering.
The thickness of the Al film was 100 nm.

Next, the Al film was subjected to photolithography and etching to form a gate electrode, a capacitor lower electrode, a gate wiring, and a capacitor wiring 10 ′.
The external shape of the gate electrode was 300 μm in length, 180 μm in width, and the width of the gate electrode was 35 μm. The size of the capacitor lower electrode was 450 μm in length and 240 μm in width.

Next, a polyvinyl phenol solution was spin-coated and baked to form a gate insulating film having a thickness of 1 μm.

Next, a source electrode, a drain electrode, a capacitor upper electrode, and a drain wiring 5 ′ were formed by screen printing using Ag conductive ink.
The thickness of the source electrode, drain electrode, and capacitor upper electrode was about 10 μm, and the source electrode was a quadrangle with a length of 290 μm and a width of 130 μm.
The drain electrode was C-shaped with a width of 25 μm.
The channel length was 25 μm.

The capacitor upper electrode was a quadrangle having a length of 430 μm and a width of 240 μm.
The source electrode and the capacitor upper electrode were connected by a connection part having a width of 25 μm.

Next, a polythiophene solution was applied to the entire surface including the gap between the source electrode and the drain electrode by ink jet printing, and baked to form a semiconductor layer.

Next, an epoxy resin was spin-coated to form an interlayer insulating film having a thickness of 20 μm.

Next, UV-YAG laser beam processing was performed to form a via hole having an inner diameter of 100 μm.

Finally, Ag ink was screen-printed to form pixel electrodes in a square of about 490 μm square to obtain a thin film transistor device.

First, polyethylene naphthalate (PEN) having a thickness of 125 μm was prepared, and a sputter film was formed on the entire surface, and then a gate electrode, a capacitor lower electrode, a gate wiring, and a capacitor wiring were formed by photolithography and etching.
The thickness of Al was 100 nm.
The gate electrode was 300 μm in length, 180 μm in width, and 35 μm in width.
The size of the capacitor lower electrode was 450 μm in length and 240 μm in width.

Next, SiO ₂ was formed by sputtering, and InGaZnO ₄ to be the semiconductor layer 6 was formed thereon.
The thickness of SiO ₂ was 500 nm, and the thickness of InGaZnO ₄ was 200 nm.

Next, a source electrode, a drain electrode, a capacitor upper electrode, and a drain wiring 5 ′ were formed by screen printing using Ag conductive ink.
The thickness of the source electrode, drain electrode, capacitor upper electrode, and drain wiring 5 ′ was about 10 μm, and the source electrode was a quadrangle with a length of 290 μm and a width of 130 μm.
The drain electrode had a rectangular C shape with a width of about 25 μm.
The channel length was 25 μm.
The capacitor upper electrode was a quadrangle having a size of 430 μm in length and 240 μm in width.
The source electrode and the capacitor upper electrode were connected by a connection portion having a width of about 25 μm.

Next, an epoxy resin was screen printed to form an interlayer insulating film having a thickness of 20 μm.

Next, UV-YAG laser beam processing was performed to form a via hole having an inner diameter of 100 μm.

Finally, Ag ink was screen-printed to form pixel electrodes in a square of about 490 μm square to obtain a thin film transistor device.

A thin film transistor array including the thin film transistor device according to the first embodiment having the structure shown in FIGS. 1 and 2 was manufactured according to the process diagram shown in FIG.

First, polyethylene naphthalate (PEN) having a thickness of 125 μm was prepared, and a sputter film was formed on the entire surface, and then a gate electrode, a capacitor lower electrode, a gate wiring, and a capacitor wiring were formed by photolithography and etching.
The thickness of Al was 100 nm.
The outer shape of the gate electrode was 350 μm in length and 215 μm in width, and the inner shape was 280 μm in length and 120 μm in width.
The capacitor lower electrode had a length of 455 μm and a width of 240 μm.
A large number of gate electrodes and capacitor lower electrodes are arranged in a matrix on an insulating substrate, and the gate wiring and the capacitor wiring are formed so as to connect them.

Next, a polyvinyl phenol solution was spin-coated and baked to form a gate insulating film having a thickness of 1 μm.

Next, a 10 μm thick source electrode, drain electrode, capacitor upper electrode, and drain wiring were formed by screen printing of Ag ink.
The source electrode was a quadrangle whose outer shape was 290 μm in length and 130 μm in width.
The drain electrode had a rectangular C shape with a width of 25 μm.
The capacitor upper electrode was a quadrangle having a length of 425 μm and a width of 230 μm.
The source electrode and the capacitor upper electrode were connected via a connection portion between the source electrode having a width of 25 μm and the capacitor upper electrode.
The channel length was 25 μm and the channel width was 815 μm.

Finally, a polythiophene solution was applied to the entire surface including the gap (channel portion) between the source electrode and the drain electrode by inkjet, and a semiconductor layer was formed by baking.

In this way, a thin film transistor array having a planar structure shown in FIG.
In this thin film transistor array, the channel length is the same as that of the comparative example described later and the channel width can be increased to 5 times that of the prior art, so the on-current is 5 times 0.5 μA.
Further, since the gate electrode substantially covers the source electrode when viewed from the direction perpendicular to the insulating substrate, the off-current can be suppressed to 50 pA or less.

The thin film transistor array produced in Example 3 was subsequently subjected to the process of FIG. 6 to produce the thin film transistor array of FIGS.

First, polyethylene naphthalate (PEN) having a thickness of 125 μm was prepared, and a sputter film was formed on the entire surface, and then a gate electrode, a capacitor lower electrode, a gate wiring, and a capacitor wiring were formed by photolithography and etching.
The thickness of Al was 100 nm.
The outer shape of the gate electrode was 350 μm in length and 215 μm in width, and the inner shape was 280 μm in length and 120 μm in width.
The capacitor lower electrode had a length of 455 μm and a width of 240 μm.
A large number of gate electrodes and capacitor lower electrodes are arranged in a matrix on an insulating substrate, and the gate wiring and the capacitor wiring are formed so as to connect them.

Next, a polyvinyl phenol solution was spin-coated and baked to form a gate insulating film having a thickness of 1 μm.

Next, a 10 μm thick source electrode, drain electrode, capacitor upper electrode, and drain wiring were formed by screen printing of Ag ink.
The source electrode was a quadrangle whose outer shape was 290 μm in length and 130 μm in width.
The drain electrode had a rectangular C shape with a width of 25 μm.
The capacitor upper electrode was a quadrangle having a length of 425 μm and a width of 230 μm.
The source electrode and the capacitor upper electrode were connected via a connection portion between the source electrode having a width of 25 μm and the capacitor upper electrode.
The channel length was 25 μm and the channel width was 815 μm.

Next, a polythiophene solution was applied to the entire surface including the gap (channel portion) between the source electrode and the drain electrode by inkjet, and a semiconductor layer was formed by baking.

Next, an epoxy resin was screen printed and then baked to form an interlayer insulating film having a thickness of 20 μm and a hole diameter of 100 μm.

Next, Ag ink was screen-printed to form 490 μm square pixel electrodes.

A guest-host liquid crystal display having the structure shown in FIG. 16 was fabricated using the fabricated thin film transistor array 80 and confirmed to operate.

The thin film transistor array produced in Example 3 was subsequently subjected to the process of FIG. 9 to produce the thin film transistor array of FIGS.

First, polyethylene naphthalate (PEN) having a thickness of 125 μm was prepared, and a sputter film was formed on the entire surface, and then a gate electrode, a capacitor lower electrode, a gate wiring, and a capacitor wiring were formed by photolithography and etching.
The thickness of Al was 100 nm.
The outer shape of the gate electrode was 350 μm in length and 215 μm in width, and the inner shape was 280 μm in length and 120 μm in width.
The capacitor lower electrode had a length of 455 μm and a width of 240 μm.
A large number of gate electrodes and capacitor lower electrodes are arranged in a matrix on an insulating substrate, and the gate wiring and the capacitor wiring are formed so as to connect them.

Next, a polyvinyl phenol solution was spin-coated and baked to form a gate insulating film having a thickness of 1 μm.

Next, a 10 μm thick source electrode, drain electrode, capacitor upper electrode, and drain wiring were formed by screen printing of Ag ink.
The source electrode was a quadrangle whose outer shape was 290 μm in length and 130 μm in width.
The drain electrode had a rectangular C shape with a width of 25 μm.
The capacitor upper electrode was a quadrangle having a length of 425 μm and a width of 230 μm.
The source electrode and the capacitor upper electrode were connected via a connection portion between the source electrode having a width of 25 μm and the capacitor upper electrode.
The channel length was 25 μm and the channel width was 815 μm.

Next, a polythiophene solution was applied to the entire surface including the gap (channel portion) between the source electrode and the drain electrode by inkjet, and a semiconductor layer was formed by baking.

Next, an epoxy resin was screen printed and then baked to form an interlayer insulating film having a thickness of 20 μm and a hole diameter of 100 μm.

Next, Ag ink was screen-printed to form 490 μm square pixel electrodes.

A guest-host liquid crystal display was fabricated using the fabricated thin film transistor array 80 and confirmed to operate.

A thin film transistor array including the thin film transistor device according to the second embodiment having the structure shown in FIGS. 10 and 11 was manufactured according to the process chart shown in FIG.

First, polyethylene naphthalate (PEN) with a thickness of 125 μm was prepared, and Al was formed on the entire surface by sputtering, and then a gate electrode, a capacitor lower electrode, a gate wiring, and a capacitor wiring were formed by photolithography and etching.
The thickness of Al was 100 nm.

The outer shape of the gate electrode was 350 μm in length and 215 μm in width, the inner shape was 280 μm in length and 120 μm in width, and the capacitor lower electrode was 455 μm in length and 240 μm in width.
In addition, a large number of gate electrodes and capacitor lower electrodes are arranged in a matrix on the insulating substrate 1, and the gate wiring and the capacitor wiring connect them.

Next, after depositing SiO ₂ (gate insulating film) having a thickness of 500 nm by sputtering, InGaZnO ₄ (semiconductor layer) having a thickness of 200 nm was formed.

Next, a 10 μm-thick source electrode, drain electrode, capacitor upper electrode, and drain wiring were formed by screen printing of Ag.
The source electrode was a quadrangle whose outer shape was 290 μm in length and 130 μm in width.
The drain electrode had a rectangular C shape with a width of 25 μm.
The capacitor upper electrode was a quadrangle having a length of 425 μm and a width of 230 μm.

Compared to Comparative Example 2 described later, the channel length is the same and the channel width can be increased to 5 times that of the prior art, so the on-current is 5 times 15 μA.
Further, when viewed from the direction perpendicular to the insulating substrate, the gate electrode substantially covers the source electrode, so that the off-current can be suppressed to 5 nA or less.

For the element of Example 6, the interlayer insulating film 7 and the pixel electrode 8 are formed by the same process as in Example 4 or 5, and the thin film transistor device shown in FIGS. 13 and 14 is provided. A thin film transistor array 80 having a planar structure was obtained.
As a result of using the produced thin film transistor array as a guest-host liquid crystal display having the structure shown in FIG. 16 using a counter substrate using a PET film as a transparent substrate and ITO as a counter electrode, a stable and clear image is displayed. I was able to confirm.

<Comparative Example 1>
A thin film transistor array having the same structure as that of FIG. 17 as viewed from the direction perpendicular to the insulating substrate was manufactured. (However, the semiconductor 6 is formed on the entire surface, and the pixel electrode 8 is also used as the source electrode 4)

First, a polyethylene naphthalate (PEN) having a thickness of 125 μm was prepared, and after sputtering Al, a rectangular gate electrode having a thickness of 100 nm and a rectangular capacitor lower electrode, a gate wiring, and a capacitor wiring were formed by photolithography and etching. Produced.
The gate electrode was 50 μm wide and 250 μm long.
The capacitor lower electrode had a width of 200 μm and a length of 150 μm.
Further, a large number of these gate electrodes and capacitor lower electrodes are arranged in a matrix on the insulating substrate, and the gate wiring and the capacitor wiring connect them.

Next, a polyvinyl phenol solution was spin-coated and baked to form a gate insulating film having a thickness of 1 μm.

Next, a 10 μm thick source electrode, drain electrode, and drain wiring were formed by screen printing of Ag ink.
The channel length between the source electrode and the drain electrode was 25 μm, and the channel width was 150 μm.

Next, a polythiophene solution was spin-coated on the entire surface including the gap between the source electrode and the drain electrode, and a semiconductor layer was formed by baking to obtain a thin film transistor. (Fig. 17)

The thin film transistor thus obtained had an on-current (drain voltage = drain voltage when the gate voltage = −40V) was 100 nA, and an off-current (drain voltage = −40V, drain current when the gate voltage = 0V) was 10 nA.

<Comparative example 2>
A polyethylene naphthalate (PEN) with a thickness of 125 μm was prepared, and after sputtering Al, a rectangular gate electrode having a thickness of 100 nm, a capacitor lower electrode, a gate wiring, and a capacitor wiring were formed by photolithography and etching.
The gate electrode had a width of 50 μm and a length of 250 μm.
The area with the capacitor lower electrode was 30000 μm ² .
A large number of gate electrodes and capacitor lower electrodes are arranged in a matrix on the insulating substrate, and the gate wiring and the capacitor wiring connect them.

Next, after depositing SiO ₂ (gate insulating film) having a thickness of 500 nm by sputtering, InGaZnO ₄ (semiconductor layer) having a thickness of 200 nm was formed.

Next, the source and drain electrodes 5 and the drain wiring having a thickness of 10 μm were formed by screen printing with Ag ink.
The channel length between the source electrode and the drain electrode was 25 μm, and the channel width was 150 μm.

The thin film transistor obtained had an on-current (drain voltage = drain voltage at a gate voltage = 5 V) of about 3 μA and an off-current (drain current at a drain voltage = 5 V and a gate voltage = 0 V) of 100 nA.

In the thin film transistor, it is needless to say that the term “drain” and the term “source” are distinguished for convenience and may be called in reverse.

It is the figure seen from the orthogonal | vertical direction with respect to the insulated substrate of the thin-film transistor apparatus concerning the 1st Embodiment of this invention. It is a figure which shows the cross-sectional structure along line A-A 'of FIG. FIG. 3 is a cross-sectional process diagram illustrating a manufacturing process of the thin film transistor device of FIG. 1. It is the figure seen from the orthogonal | vertical direction with respect to the insulated substrate of the thin-film transistor apparatus concerning the 1st Embodiment of this invention. FIG. 5 is a diagram showing a cross-sectional structure taken along line B-B ′ in FIG. 4. FIG. 5 is a cross-sectional process diagram illustrating a manufacturing process of the thin film transistor device of FIG. 4 and is a continuation of FIG. 3. It is the figure seen from the orthogonal | vertical direction with respect to the insulated substrate of the thin-film transistor apparatus concerning the 1st Embodiment of this invention. FIG. 8 is a diagram showing a cross-sectional structure taken along line C-C ′ in FIG. 7. FIG. 8 is a cross-sectional process diagram illustrating a manufacturing process of the thin film transistor device of FIG. 7 and is a continuation of FIG. 3. It is the figure seen from the orthogonal | vertical direction with respect to the insulated substrate of the thin-film transistor apparatus concerning the 2nd Embodiment of this invention. It is a figure which shows the cross-sectional structure along line D-D 'of FIG. FIG. 11 is a cross-sectional process diagram illustrating a manufacturing process of the thin film transistor device of FIG. 10. It is a figure which shows the cross-sectional structure of the thin-film transistor apparatus concerning the 2nd Embodiment of this invention. It is a figure which shows the cross-sectional structure of the thin-film transistor apparatus concerning the 2nd Embodiment of this invention. It is a figure explaining the planar structure of the thin-film transistor array of this invention. It is a figure explaining the cross-section of an example of the thin-film transistor display of this invention. It is the figure seen from the perpendicular direction with respect to the insulated substrate of the conventional thin-film transistor. It is sectional drawing along line E-E 'of FIG. It is the figure seen from the perpendicular direction with respect to the other insulated substrate of the conventional thin-film transistor.

Explanation of symbols

1 .... Insulating substrate 2 ... Gate electrode 2 '... Gate wiring 3 ... Gate insulating film 4 ... Source Electrode 5... Drain electrode 5 ′... Drain wiring 6... Semiconductor layer 7... Interlayer insulating film 8. Pixel electrode 9 ... via hole 10 ... capacitor lower electrode 10 '... capacitor wiring 11 ... capacitor upper electrode 12 ... (source electrode) Connection portion 13 (... and capacitor upper electrode) ... Counter substrate 15 ... Guest host liquid crystal 50, 60 ... Thin film transistor device 51 ... Thin film transistor 52 ... Capacitor 80 ... Thin film transistor array 90 ... Guest host liquid crystal display Lee

Claims (9)

At least a gate electrode formed on an insulating substrate, a capacitor lower electrode, a gate insulating film formed thereon, a source electrode, a drain electrode formed on the gate insulating film, and an upper portion of the capacitor A thin film transistor device having an electrode and a semiconductor layer connecting the source electrode and the drain electrode, the source electrode having a substantially isolated island pattern when viewed from a direction perpendicular to the insulating substrate, and the source electrode A C-shaped drain electrode as viewed from a direction perpendicular to the insulating substrate and a gap between the source electrode and the drain electrode as viewed from a direction perpendicular to the insulating substrate. Wiring having the gate electrode arranged and arranged in a portion where the drain electrode does not exist when viewed from a direction perpendicular to the insulating substrate Thus a thin film transistor device, characterized in that the source electrode and the capacitor upper electrode is connected. At least a gate electrode formed on an insulating substrate, a capacitor lower electrode, a gate insulating film formed thereon, a source electrode, a drain electrode formed on the gate insulating film, and an upper portion of the capacitor An electrode, a semiconductor layer connecting the source electrode and the drain electrode, an interlayer insulating film formed thereon, and a via hole penetrating the interlayer insulating film connected to the source electrode or the capacitor upper electrode A thin film transistor device having a pixel electrode, the source electrode having a substantially isolated island pattern as viewed from a direction perpendicular to the insulating substrate, and a direction perpendicular to the insulating substrate so as to substantially surround the source electrode A C-shaped drain electrode as viewed, and the source electrode and the drain electrode as viewed from a direction perpendicular to the insulating substrate The gate electrode disposed so as to include a gap, and the source electrode and the capacitor upper electrode are connected by a wiring disposed in a portion where the drain electrode does not exist when viewed from a direction perpendicular to the insulating substrate. A thin film transistor device characterized by the above. 3. The thin film transistor device according to claim 1, wherein the source electrode has a quadrangular shape when viewed from a direction perpendicular to the insulating substrate. When viewed from the direction perpendicular to the insulating substrate, the capacitor upper electrode has a substantially isolated island pattern, and the capacitor lower electrode is larger than the capacitor upper electrode and includes the capacitor upper electrode. The thin film transistor device according to claim 1, wherein the thin film transistor device is a thin film transistor device. The thin film transistor device according to claim 1, wherein the semiconductor layer is made of an oxide semiconductor or an organic semiconductor. The thin film transistor device according to claim 1, wherein the semiconductor layer is formed over the entire surface of the insulating substrate. 7. The thin film transistor device according to claim 1, wherein a plurality of thin film transistor devices are arranged in a matrix on an insulating substrate, and the plurality of thin film transistor devices includes gate wirings and drain wirings. And a thin film transistor array electrically connected by capacitor wiring. A thin film transistor display using the thin film transistor array according to claim 7. A gate electrode and capacitor lower electrode forming step of forming a gate electrode and a capacitor lower electrode made of a conductive film on an insulating substrate;
A gate insulating film forming step of forming a gate insulating film on the gate electrode and the capacitor lower electrode;
A source electrode formed of a conductive film on the gate insulating film, a drain electrode, a source electrode for forming a capacitor upper electrode, a drain electrode, a capacitor upper electrode forming step;
A semiconductor layer forming step of forming a semiconductor layer in contact with the gate insulating film, the source electrode, and the drain electrode;
Forming an interlayer insulating film having an opening on the source electrode or the upper capacitor electrode on the semiconductor layer, the source electrode, the drain electrode, and the gate insulating film;
A method of manufacturing a thin film transistor device having a pixel electrode forming step of forming a pixel electrode on the opening and the interlayer insulating film, the step of forming a semiconductor layer, and forming the source electrode, drain electrode, and capacitor upper electrode A method of manufacturing a thin film transistor device, wherein at least one of the step, the step of forming the interlayer insulating film, and the step of forming the pixel electrode is a printing method.

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