CN113300829A - Hardware implementation device of SM3 algorithm - Google Patents

Hardware implementation device of SM3 algorithm Download PDF

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CN113300829A
CN113300829A CN202110552612.1A CN202110552612A CN113300829A CN 113300829 A CN113300829 A CN 113300829A CN 202110552612 A CN202110552612 A CN 202110552612A CN 113300829 A CN113300829 A CN 113300829A
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CN113300829B (en
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冯炫博
张亚国
李正卫
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Shenzhen Smart Microelectronics Technology Co ltd
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Spl Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms

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Abstract

The invention relates to a hardware implementation device of SM3 algorithm, belonging to the technical field of information security. The device comprises: 16 basic message word registers, storing first the 16 initial message words and then operating on the 16 basic message word registers in 64 rounds of extended calculations in the SM3 algorithm, the operations comprising: the non-reassignment operation of the 0 th round to the 11 th round and the dynamic assignment operation of the 12 th round to the 63 rd round are as follows: coding the 16 basic message word registers in sequence, assigning the message word in the next basic message word register to the previous basic message word register, and assigning the message word in the third dynamic message word register to the last basic message word register; and 3 dynamic message word registers for dynamically storing the message words in each round of extended computation, and dynamically updating the message words in each round. The device reduces the number of registers, further reduces the area of a hardware device, saves cost and power consumption, and has more practical engineering application value.

Description

Hardware implementation device of SM3 algorithm
Technical Field
The invention relates to a hardware implementation device of SM3 algorithm, belonging to the technical field of information security.
Background
The hash function is formally introduced into cryptography in the late seventies of the twentieth century, and is mainly applied to message authentication in the early stage. The method is a unidirectional cryptographic algorithm, has the characteristics of compression, simplicity, primitive root resistance, collision resistance and the like, and has wide application of the hash function in the fields of cryptography and information security. The hash functions commonly used include SHA-1, SHA-2, MD4, MDS, SM2, and SM 3.
The SM3 cryptographic hash algorithm can meet the security requirements of a variety of cryptographic algorithm applications, such as: the message verification code is generated and verified through the SM3 hash algorithm, the digital signature and verification are generated through the SM3 hash algorithm, meanwhile, the required hash function can be provided for the digital signature of the SM2 cryptographic algorithm, and the like. Due to the high safety of the SM3, in 2018, in 10 months, the SM3 formally becomes an international standard and is widely applied.
At present, information security technology is integrated into social economy, life and other aspects, and information security becomes a safe box for guaranteeing normal operation of the whole society at present. With the improvement and attention of various fields and industries on information security requirements and the high-speed development of integrated circuits, the chip for realizing information security in a hardware form is widely applied to the internet of things security industry and the intelligent hardware market, and compared with encryption in a software form, the chip for realizing information security in a hardware form has the advantages of higher security and higher encryption operation speed, and has the defect that the chip cost and power consumption are increased when hardware encryption is realized.
In conclusion, the hardware implementation of the SM3 has a great practical engineering application value for the current internet of things security industry and the intelligent hardware market. However, due to the characteristic of message expansion based on the SM3 cryptographic hash algorithm, 132 message words need to be expanded, so that the algorithm needs 132 message word registers with 32 bits implemented in hardware, which results in too large hardware area during hardware design and too large chip cost.
Disclosure of Invention
The application aims to provide a hardware implementation device of an SM3 algorithm, which is used for solving the problems of overlarge hardware area and overhigh cost when the existing SM3 algorithm is implemented on hardware.
In order to achieve the above object, the present application proposes a hardware implementation apparatus of a first SM3 algorithm, where the apparatus includes:
16 basic message word registers, storing first the 16 initial message words and then operating on the 16 basic message word registers in 64 rounds of extended calculations in the SM3 algorithm, the operations comprising: the non-reassignment operation of the 0 th round to the 11 th round and the dynamic assignment operation of the 12 th round to the 63 rd round are carried out, and the dynamic assignment rule is as follows: coding the 16 basic message word registers in sequence, assigning the message word in the next basic message word register to the previous basic message word register, and assigning the message word in the third dynamic message word register to the last basic message word register;
3 dynamic message word registers for dynamically storing message words in each round of extended computation, wherein the dynamic updating process of the message words in the 0 th round to the 11 th round is as follows:
Figure BDA0003075744470000021
the dynamic updating process of the message words of the 12 th round to the 63 rd round is as follows:
Figure BDA0003075744470000022
wherein Wt1 is a first dynamic message word register; wt2 is a second dynamic message word register; w16 is a third dynamic message word register; WJ is the basic message word register, J ═ 0, 1, … …, 15.
The hardware implementation device of the first SM3 algorithm has the following beneficial effects: the device only needs to set 19 registers comprising 16 basic message word registers and 3 dynamic message word registers, completes the SM3 algorithm through the rule of dynamic assignment, reduces the number of registers, further reduces the area of a hardware device, saves the cost and the power consumption, and has more practical engineering application value.
Further, each message word is 32 bits.
Further, before assigning values to the 16 basic message word registers, the method further comprises the step of judging the bit number of the original message data:
judging whether the bit number of the original message data meets the set bit, and if not, performing complementation; if the number of the messages exceeds the preset number, the message blocks are grouped according to the set bit, and the surplus messages do not meet the complement of the set bit.
Further, an interface module is included for receiving the original message data and outputting the encrypted result of the SM3 algorithm.
Further, the system also comprises an FIFO storage module, wherein the FIFO storage module is connected with the interface module and is used for storing the original message data.
In addition, the present application also provides a technical solution of a hardware implementation apparatus of a second SM3 algorithm, where the apparatus includes:
16 basic message word registers, storing first the 16 initial message words and then operating on the 16 basic message word registers in 64 rounds of extended calculations in the SM3 algorithm, the operations comprising: the non-reassignment operation of the 0 th round to the 11 th round and the dynamic assignment operation of the 12 th round to the 63 rd round are carried out, and the dynamic assignment rule is as follows: the 16 basic message word registers are encoded according to the sequence, the message word in the next basic message word register is assigned to the previous basic message word register, and the 16 basic message word registers are encoded according to the sequence
Figure BDA0003075744470000031
Assigning the result of (a) to the last basic message word register;
2 dynamic message word registers for dynamically storing message words in each round of extended computation, wherein the dynamic updating process of the message words in the 0 th round to the 11 th round is as follows:
Figure BDA0003075744470000032
the dynamic updating process of the message words of the 12 th round to the 63 rd round is as follows:
Figure BDA0003075744470000033
wherein Wt1 is a first dynamic message word register; wt2 is a second dynamic message word register; WJ is the basic message word register, J ═ 0, 1, … …, 15.
The hardware implementation device of the second SM3 algorithm has the following beneficial effects: the device only needs to set 18 registers comprising 16 basic message word registers and 2 dynamic message word registers, completes the SM3 algorithm through the rule of dynamic assignment, reduces the number of one register on the basis of the first technical scheme, further reduces the area of a hardware device, further saves the cost and the power consumption, and has more practical engineering application value.
Further, each message word is 32 bits.
Further, before assigning values to the 16 basic message word registers, the method further comprises the step of judging the bit number of the original message data:
judging whether the bit number of the original message data meets the set bit, and if not, performing complementation; if the number of the messages exceeds the preset number, the message blocks are grouped according to the set bit, and the surplus messages do not meet the complement of the set bit.
Further, an interface module is included for receiving the original message data and outputting the encrypted result of the SM3 algorithm.
Further, the system also comprises an FIFO storage module, wherein the FIFO storage module is connected with the interface module and is used for storing the original message data.
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FIG. 1 is a block diagram of a hardware implementation of the SM3 algorithm of the present invention;
FIG. 2 is a schematic diagram of the initial assignment of the 16 basic message word registers, dynamic message word registers Wt1 and Wt2 of the present invention;
FIG. 3 is a diagram of the dynamic assignment of registers according to the present invention.
Detailed Description
Hardware implementation of the SM3 algorithm example 1:
the main idea of the invention is that the device uses 16 basic message word registers and 3 dynamic message word registers, based on the characteristics of the SM3 algorithm itself: in 64 rounds of calculation, 16 basic message word registers are not assigned again in the 0 th to 11 th rounds of calculation, and the 16 basic message word registers are dynamically assigned from the 12 th round of calculation.
The SM3 algorithm hardware implementation device, as shown in fig. 1, includes an interface module (AHB interface) for receiving original Message data (Message) and outputting an encrypted Result (Result), and the module can mount an SM3 module on an AHB bus, and can access an SM3 module through the AHB bus;
further comprising: the Data processing system comprises an FIFO storage module for storing original message Data, a Read Data & Shift Byte module for reading the original message Data and splicing the original message Data, a Padding module Padding1&0 for Data Padding, a Padding length for Padding a plaintext length, and an A valid block Data module for performing 512-bit segmentation on the Data, wherein the modules judge the Data written in an AHB bus and then correspondingly perform Data operation (such as Data Padding) required by an SM3 algorithm, so that the operational Data to be input into the SM3 module conforms to the algorithm requirement of SM 3; further inputting the effective operation data to the SM3 module;
after the valid operation data is processed by performing SM3 calculation extension in the SM3 module, the Result (Finnal Result) after calculation encryption is output through the AHB interface module. The SM3 module includes 16 basic message word registers W0, W1, W2, W3, … …, and W15, where in the following calculations, the basic message word registers are represented by WJ, J being 0, 1, … …, and 15. The 3 dynamic message word registers are W16 (third dynamic message word register), Wt1 (first dynamic message word register), Wt2 (second dynamic message word register).
Specifically, the hardware implementation apparatus implements the SM3 algorithm as follows:
1) input raw message data is acquired.
As required by the SM3 algorithm: into message blocks of 512 bits, a group of message blocks comprising 16 message words of 32 bits each. The SM3 algorithm requires expansion of 16 message words to 132 message words, i.e. expansion of 116 message words, with 64 rounds of computation in the expansion process.
The original 16 message words are calculated through assignment and are respectively W0、W1、W2、W3、……、W15The expanded 116 message words are respectively W16、W17、W18、W19、……、W67、W0'、W1'、W2'、W3'、……、W63'. Of the 64 round calculations, the 0 th round calculates W 0'1 st round of calculation of W1'… …, round 11 calculation of W16And W11'12 th calculation of W17And W12'13 th calculation of W18And W13'And so on, the 62 nd round calculates W67And W62'The 63 st round calculates W63'Subsequently with Wj、Wj'Representing 132 message words.
2) Judging whether the input message data has 512 bits (namely set bits which are set according to the bit number of the message word), and supplementing according to the requirements of an SM3 algorithm when the input message data has less than 512 bits; over 512 bits, the packets are grouped in 512 bits by one message block, and less than 512 bits remain to be filled in according to the requirements of the SM3 algorithm.
3) A 512-bit message block is divided into 16 message words and the initial 16 message words are assigned to the 16 basic message word registers W0, W1, W2, W3, … …, W15 as shown in fig. 2.
The assignment mode is as follows:
Figure BDA0003075744470000051
where "msg" denotes a 512-bit message block.
4) 64 rounds of spread calculation are performed, and the 64 rounds of spread calculation include two operations:
to be unified with the subscript j of the message word, 64 rounds of calculation are defined as 0 th to 63 th rounds, i.e. j may represent the number of rounds of calculation, the first of which is 16 basic message word register un-reassignment operations.
After the 0 th to 11 th calculation, 16 basic message word registers of W0, W1, W2, W3, … … and W15 are not assigned again, and 2 dynamic message word registers of Wt1 and Wt2 are assigned again after each calculation; the value in the dynamic message word register of W16 may be calculated according to the values in the several basic message word registers of W0, W7, W13, W3, and W10, specifically:
Figure BDA0003075744470000052
since these several basic message registers are not reassigned, the assigned size in the dynamic message word register of W16 in round 0 to round 11 is:
Figure BDA0003075744470000053
W16will calculate W in round 1212' used (the process assignment in the hardware implementation adopts non-blocking assignment, and the non-blocking assignment adopted in the hardware design is assigned in the current round and has effect in the next round).
The 2 dynamic message word registers Wt1, Wt2 have a relationship to the values in the 16 base message registers:
Figure BDA0003075744470000061
that is, the assignment of the 2 dynamic message word registers Wt1 and Wt2 is calculated as:
Figure BDA0003075744470000062
after the 0 th round of calculation, W0Assign a value to Wt1 to W0'Assigning W to Wt2, … …, and calculating W after 11 th round11Assign a value to Wt1 to W11'Assigned to Wt 2.
Where j is 0, 1, … …, and 11 are subscripts of the message word, and may also be used to indicate the number of rounds of calculation, and j is 0, indicating the 0 th round of calculation.
Second is a dynamic assignment operation for 16 basic message word registers
In the 12 th calculation, the relationship between the 2 dynamic message word registers Wt1 and Wt2 and the values in the other registers is:
Figure BDA0003075744470000063
as shown in FIG. 3, the 2 dynamic message word registers Wt1 and Wt2 respectively assign W12And W12'The specific assignment process is as follows:
w stored in dynamic message word register W1616And W stored in a basic message word register W1212Obtaining W through XOR12'Assigned to Wt2, and stored in basic message word register W1212Direct assignment to Wt 1; simultaneously, values in registers W1, W2, W3, … … and W16 are shifted to the left by one register and are respectively reassigned to registers W0, W1, W2, W3, … … and W15;
the reassigned size W in W16 is then calculated from the values in the several basic message word registers W0, W7, W13, W3, W1017Since the value in the basic message register has been shifted left and reassigned, the calculation formula of the specific message word is:
Figure BDA0003075744470000064
further calculate W17Assigned to the dynamic message word register W16.
In the 13 th calculation, the 2 dynamic message word registers Wt1 and Wt2 respectively store W13And W13'The specific assignment process is as follows:
w stored in dynamic message word register W1617And W stored in a basic message word register W1213Obtaining W through XOR13'Assigned to Wt2, and stored in basic message word register W1213Direct assignment to Wt 1; simultaneously, values in registers W1, W2, W3, … … and W16 are shifted to the left by one register and are respectively reassigned to registers W0, W1, W2, W3, … … and W15;
then according to
Figure BDA0003075744470000065
Calculating W18Assigned to the dynamic message word register W16.
By analogy, in the 62 nd calculation, the W stored in the dynamic message word register W1666And W stored in a basic message word register W1262Obtaining W through XOR62'Assigned to Wt2, and stored in basic message word register W1262Direct assignment to Wt 1; simultaneously, values in registers W1, W2, W3, … … and W16 are shifted to the left by one register and are respectively reassigned to registers W0, W1, W2, W3, … … and W15;
then according to
Figure BDA0003075744470000071
Calculating W67Assigned to the dynamic message word register W16.
In the 63 rd calculation, W stored in the dynamic message word register W1667And W stored in a basic message word register W1263Obtaining W through XOR63', assigned to Wt2, W stored in basic message word register W1263Direct assignment to Wt 1; and simultaneously, shifting values in registers W1, W2, W3, … … and W16 to the left by one register, respectively reassigning the values to registers W0, W1, W2, W3, … … and W15, and finishing the calculation, thus finishing 64 rounds of expansion of 132 message words.
To sum up, the rules for dynamically assigning the 16 basic message word registers of the 12 th round to the 63 rd round are summarized as follows: the 16 basic message word registers are encoded in sequence, the value in the next basic message word register is assigned to the previous basic message word register, and the message word of W16 in the dynamic message word register is assigned to the last basic message word register.
The procedure for the 3 dynamic message word registers W16, Wt1, Wt2 and their relationship to other basic message word registers, and for calculating assignments from message words, is as follows:
Figure BDA0003075744470000072
Figure BDA0003075744470000073
where j is 12, 13, … …, and 63 are subscripts of the message word, and may also be used to indicate the number of rounds of calculation, j is 12, indicating the 12 th round of calculation, and P1 is a permutation function.
The stored values of the 16 basic message word registers W0, W1, W2, W3, … …, W15, and the 3 dynamic message word registers W16, Wt1, Wt2, which are calculated in round 12, are:
Figure BDA0003075744470000081
after the 13 th calculation, 16 basic message word registers of W0, W1, W2, W3, … … and W15 and 3 dynamic message word registers of W16, Wt1 and Wt2 store the following values:
Figure BDA0003075744470000082
and so on, completing 64 rounds of message word expansion.
The value of output A, B, C, D, E, F, G, H is calculated from the message words stored in the registers before each round of calculation assignment, the calculation formula is as follows:
SS1＝((A＜＜＜12)+E+(Tj＜＜＜j))＜＜＜7；
Figure BDA0003075744470000091
TT1＝FFj(A,B,C)+D+SS2+Wt2；
TT2＝GGj(E,F,G)+H+SS1+Wt1；
A＝TT1；
B＝A；
C＝B＜＜＜9；
D＝C；
E＝P0(TT2)；
F＝E；
G＝F＜＜＜19；
H＝G；
Wt1＝Wj；
Figure BDA0003075744470000092
wherein, TjIs a constant value, FFj(A,B,C)、GGj(E, F, G) is a Boolean function, P0, P1 are permutation functions, as shown below, "<" is a cycle left-shift symbol,
Figure BDA0003075744470000093
is an xor sign.
Figure BDA0003075744470000094
Figure BDA0003075744470000095
Figure BDA0003075744470000096
Figure BDA0003075744470000097
Figure BDA0003075744470000098
For example: after the 12 th calculation, W is stored in 2 dynamic message word registers Wt1 and Wt212And W12'13 th wheel first according to W12And W12'Calculate A, B, C, D, E, F, G, H, then calculate W13'Then, the assignment operation of each register is performed, the 13 th calculation is finished, and W is stored in Wt1 and Wt213And W13'。
5) Finally, the calculated W according to the 63 rd round67And W63'And outputting the final A, B, C, D, E, F, G, H in the 64 th round to perform exclusive-or calculation with the initialization parameters, and splicing the obtained results to obtain the final encryption result.
W calculated due to round 00'A, B, C, D, E, F, G, H will be calculated in round 1; therefore, A, B, C, D, E, F, G, H of one round is output from the 1 st round to the 64 th round of calculation, but the calculation A, B, C, D, E, F, G, H of the 64 th round is only calculated according to the values stored in the registers after the 63 rd round of calculation is finished, and the calculation result obtained from the 64 th round is only applied to the final output calculation, so that the SM3 algorithm calculation is finished after the encryption result is obtained.
In the above embodiment, the technology of the interface module is mature, and corresponding modules with the same function in the prior art can be adopted. Other memory modules may also be used in connection with the memory module, such as: memory storage modules, etc., as the present invention is not limited in this respect.
In the above embodiment, because of the requirement of the SM3 algorithm, the step of determining the number of bits of the message data in step 2) is not required, and certainly, when the message data is ensured to be 512 bits, the determination may not be performed.
The SM3 algorithm is realized through the hardware implementation device comprising 19 registers, the number of the registers is reduced, the area of the hardware implementation device is further reduced, and the cost is saved.
Hardware implementation of the SM3 algorithm example 2:
the hardware implementation apparatus of this embodiment is different from embodiment 1 in the number of registers, and the hardware implementation apparatus of this embodiment includes 16 basic message word registers and 2 dynamic message word registers, so that the dynamic message word registers W16 are reduced, the number of registers is further saved, the area of the hardware implementation apparatus is reduced, and the cost is saved. Other structures of the hardware implementation apparatus are the same as those of embodiment 1, and are not described herein.
To this end, the hardware implementation of the SM3 algorithm is in an extended 64-round calculation:
16 basic message word registers, storing first the 16 initial message words and then operating on the 16 basic message word registers in 64 rounds of extended calculations in the SM3 algorithm, the operations comprising: the non-reassignment operation of the 0 th round to the 11 th round and the dynamic assignment operation of the 12 th round to the 63 rd round are carried out, and the dynamic assignment rule is as follows: the 16 basic message word registers are encoded according to the sequence, the message word in the next basic message word register is assigned to the previous basic message word register, and the 16 basic message word registers are encoded according to the sequence
Figure BDA0003075744470000101
Assigning the result of (a) to the last basic message word register; the assignment calculation is the same as that of the dynamic message word register W16 in embodiment 1, except that the calculation result is directly assigned here, and a special dynamic message word register is not required.
2 dynamic message word registers for dynamically storing message words in each round of extended computation, wherein the dynamic updating process of each round of message words is as follows:
Figure BDA0003075744470000111
wherein Wt1 is a first dynamic message word register; wt2 is a second dynamic message word register.
The process of dynamically assigning 2 dynamic message word registers and 16 basic message word registers is the same as that in embodiment 1, and is not described herein again.

Claims (10)

1. A hardware implementation of the SM3 algorithm, comprising:
16 basic message word registers, storing first the 16 initial message words and then operating on the 16 basic message word registers in 64 rounds of extended calculations in the SM3 algorithm, the operations comprising: the non-reassignment operation of the 0 th round to the 11 th round and the dynamic assignment operation of the 12 th round to the 63 rd round are carried out, and the dynamic assignment rule is as follows: coding the 16 basic message word registers in sequence, assigning the message word in the next basic message word register to the previous basic message word register, and assigning the message word in the third dynamic message word register to the last basic message word register;
3 dynamic message word registers for dynamically storing message words in each round of extended computation, wherein the dynamic updating process of the message words in the 0 th round to the 11 th round is as follows:
Figure FDA0003075744460000011
the dynamic updating process of the message words of the 12 th round to the 63 rd round is as follows:
Figure FDA0003075744460000012
wherein Wt1 is a first dynamic message word register; wt2 is a second dynamic message word register; w16 is a third dynamic message word register; WJ is the basic message word register, J ═ 0, 1, … …, 15.
2. Hardware implementation of the SM3 algorithm according to claim 1, wherein each message word is 32 bits.
3. A hardware implementation of the SM3 algorithm according to claim 1 or 2, wherein before assigning values to the 16 basic message word registers, the method further comprises the step of determining the number of bits of the original message data:
judging whether the bit number of the original message data meets the set bit, and if not, performing complementation; if the number of the messages exceeds the preset number, the message blocks are grouped according to the set bit, and the surplus messages do not meet the complement of the set bit.
4. Hardware implementation of the SM3 algorithm according to claim 1 or 2, further comprising an interface module for receiving original message data and outputting the encryption result of the SM3 algorithm.
5. The hardware implementation of the SM3 algorithm of claim 4, further comprising a FIFO storage module coupled to the interface module for storing raw message data.
6. A hardware implementation of the SM3 algorithm, comprising:
16 basic message word registers, storing first the 16 initial message words and then operating on the 16 basic message word registers in 64 rounds of extended calculations in the SM3 algorithm, the operations comprising: the non-reassignment operation of the 0 th round to the 11 th round and the dynamic assignment operation of the 12 th round to the 63 rd round are carried out, and the dynamic assignment rule is as follows: the 16 basic message word registers are encoded according to the sequence, the message word in the next basic message word register is assigned to the previous basic message word register, and the 16 basic message word registers are encoded according to the sequence
Figure FDA0003075744460000021
Assigning the result of (a) to the last basic message word register;
2 dynamic message word registers for dynamically storing message words in each round of extended computation, wherein the dynamic updating process of the message words in the 0 th round to the 11 th round is as follows:
Figure FDA0003075744460000022
the dynamic updating process of the message words of the 12 th round to the 63 rd round is as follows:
Figure FDA0003075744460000023
wherein Wt1 is a first dynamic message word register; wt2 is a second dynamic message word register; WJ is the basic message word register, J ═ 0, 1, … …, 15.
7. Hardware implementation of the SM3 algorithm according to claim 6, wherein each message word is 32 bits.
8. The hardware implementation of the SM3 algorithm of claim 6 or 7, wherein before assigning values to the 16 basic message word registers, the method further comprises the step of determining the number of bits of the original message data:
judging whether the bit number of the original message data meets the set bit, and if not, performing complementation; if the number of the messages exceeds the preset number, the message blocks are grouped according to the set bit, and the surplus messages do not meet the complement of the set bit.
9. Hardware implementation of the SM3 algorithm according to claim 6 or 7, further comprising an interface module for receiving original message data and outputting the encryption result of the SM3 algorithm.
10. The hardware implementation of the SM3 algorithm of claim 9, further comprising a FIFO storage module coupled to the interface module for storing raw message data.
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