JP3275881B2 - Code generation method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a code generation method and apparatus.

[0002]

2. Description of the Related Art Conventional typical encryption algorithms include DES (Data Encryption Standard) and FEAL.
(Fast Encryption Standard) is known and DES
For example, (1) Koyama et al., "Modern Cryptography",
IEICE, pp. 41-49, September 1986, and regarding FEAL, (2) Shimizu et al., "High-speed Data Encryption Algorithm FEAL", IEICE Transactions D, Vol. J70-D. 7, pp. 1413 ~
1423, July 1987, respectively.

First, a non-linear calculation part in the DES process, that is, a process called an S box will be described (see (1) p. 45, FIGS. 3-2 and p 46, FIG.
3). The 32-bit R is first replaced by the extended transposition table shown in Table 1, and some bits are duplicated and expanded to 48 bits.

[0004] The 48-bit R obtained in this way forms the following eight sets of 6-bit blocks, each of which is obtained by adding the subsequent 2 bits for every 4 bits from the beginning.

[0005] r31 r1 r2 r3 r4 r5, r4 r5 r6 r7 r8 r9, r8 r9 r10 r11 r12 r13, r12 r13 ......, r28 r29, r28 r29 r30 r31 r32 r31 r32 r31 Similarly, an exclusive OR operation with the 48-bit key K is performed, and the result is divided into eight sets of 6 bits each and input to eight S boxes from S1 to S8.
S1 to S8 are called selection functions. These S boxes are
Input 6 bits and output 4 bits.

As an example, Table 2 shows a substitution table for one S box S1.

[0007] One S box has four types (line numbers 0, 1, 2,
3) is prepared, and the substitution table is selected by using the first and last bits of the input 6 bits to determine which of the four types of substitution table is used. Then, the central 4 bits of the 6 bits input according to the selected substitution table are substituted. As a specific example, the binary input pattern is 01 for S1.
If it is 1011, 01 represented by the first 0 and the last 1, that is, row 1 (binary 01 is decimal 1
) Is selected. Next, a column 1 represented by a central 4-bit pattern 1101 (decimal 13)
3 is output, and as a result, the value 5 specified in the row 1 and the column 13, that is, 0101 is output to form a 4-bit substitution pattern. In the DES, a single-stage process is configured using such a process f (R, K), and this is repeated 16 stages.

As can be seen from the above processing example, DES is based on 1-bit unit processing.

Next, a non-linear calculation part in the FEAL processing, that is, a part including the function S will be described (see p. 1416 of the above (2), FIGS. 4 and 5).
The non-linear part of FEAL is easier to describe mathematically than the non-linear part of DES. The 32-bit data α is divided into 8-bit data α0, α1, α2, and α3, respectively, and exclusive-ORed with the key data in 8-bit units. After that, processing by a predetermined function S is performed.

Function S: S (x1 + x2 + δ) = Rot2 (w) where w = (x1 + x2 + δ) mod 256 δ = 0 or 1 (constant) Using this process f (α, β), a one-stage process is configured. Repeated eight steps. As seen in the above process,
FEAL is based on 8-bit processing.

[0011]

With the spread and widespread use of computer networks due to advances in information processing and communication technology, data and computers on transmission lines are required to secure information security against unauthorized use or capture of data. It is considered that encrypting the data stored in the server is an effective countermeasure.

DES, established in 1982 by the United States Department of Commerce as a standard for encryption algorithms, is one means of encrypting data.

[0013] However, since DES performs a great deal of processing in bit units, it takes a long time to implement it with microcomputer software based on byte processing, and a practical speed cannot be obtained. .

In order to solve this problem, the FEAL is based on processing in units of 1 byte (8 bits). Therefore, when the FEAL is realized by an 8-bit microcomputer, it is possible to achieve speedup several times or more as compared with DES. did it. It is considered that FEAL has made it possible to obtain a practical speed to some extent using software of an 8-bit microcomputer.

However, with recent advances in microelectronics technology, 16-bit microcomputers have been replaced by 8-bit microcomputers,
32-bit microcomputers have been used rather than bit microcomputers. It is anticipated that the use of 32-bit microcomputers will increase significantly in the near future. In the era of 32-bit microcomputers, higher-speed encryption processing is expected to be required. However, since a 32-bit microcomputer performs processing based on 4-byte data, an F designed for an 8-bit microcomputer based on 1-byte data is used.
Attempting to implement the EAL with a 32-bit microcomputer was inefficient.

Therefore, there has been a demand for an encryption algorithm for a 32-bit microcomputer that performs a 4-byte key processing.

An object of the present invention is to provide an encryption device that performs suitable encryption in an arithmetic unit capable of processing in 32-bit units.

[0018]

To solve the above problems, the following means are used.

That is, key data K2 and K3 each having an n-bit length are cut out from the message, A and B are each data having an n-bit length, and π3 (A, B) is data A having an n-bit length and A and The first addition operation with the key data K2 is performed, the data obtained from the first addition operation is subjected to a cyclic shift by the first number of bits, and the data obtained from the cyclic shift by the first number of bits is performed. A second addition operation with the key data K3 is performed on the obtained data, a cyclic shift is performed on the data obtained from the second addition operation with a second number of bits different from the first, and the second addition operation is further performed. A function that outputs a set of data obtained from the cyclic shift with the number of bits of 2 and n-bit data obtained by performing a third addition operation on B is defined as an initial value consisting of two n-bit data. In contrast, a message Using key data K2 and K3 held in a register connected to a computing unit, processing including an operation defined by a function π3 is performed using an additive instruction, and a cyclic shift is performed using a cyclic shift instruction. Then, a 2n-bit length code is generated from two n-bit length data obtained as a result of execution by the arithmetic unit.

As a result, since 32-bit data is replaced or transposed by one basic instruction using a 32-bit microcomputer, code can be generated at high speed.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) First Embodiment FIG. 1 shows an embodiment of the present invention.

In FIG. 1, a 64-bit plaintext 101 and 64 bits × 4 = 256 bits of key data 100 are 32 bits.
Input to the 32-bit microcomputer 102, and thereafter, are cryptographically converted by the 32-bit microcomputer 102 in the order of the instructions in the program 103.
The 4-bit ciphertext 104 is output.

FIG. 2 shows a flow of a cryptographic conversion process executed by the 32-bit microcomputer 102 and the program 103 in FIG.

201: Input data M is divided into upper 32 bits M1 and lower 32 bits M2.

202: An exclusive OR operation corresponding to the bits of M1 and M2 is performed.

WORK2 ← M1 (+) M2 Hereinafter, (+) indicates the same processing. In the figure, the exclusive OR is indicated by a symbol obtained by superimposing ○ and +.

203: Modulo addition of WORK2 and key data K1 is performed.

X ← WORK2 + K1 Here, x + K1 indicates a modulo addition modulo 232, that is, a remainder obtained by dividing the sum of x and K1 by 232.

Hereinafter, + indicates the same processing.

204: After x is cyclically shifted to the left by 2 bits, modulo addition of the data and x and 1 is performed.

X ← Rot2 (x) + x + 1 Hereinafter, Rot2 indicates the same processing.

105: After x is cyclically shifted to the left by 4 bits, the exclusive OR of the data and x is calculated.

X ← Rot4 (x) (+) x Hereinafter, Rot4 indicates the same processing.

206: WORK1 ← x (+) M1 207: x ← x + K2 208: x ← Rot2 (x) + x + 1 y ← x 209: x ← Rot3 (x) (+) x Here, Rot3 (x) is x Is cyclically shifted left by 8 bits.

210: x ← x + K3 211: x ← Rot2 (x) + x + 1 212: x ← Rot16 (x) + (x∧y) where Rot16 (x) shifts x to the left by 16 bits. Show. In addition, x∧y indicates that a logical AND of x and y corresponding to bits is taken.

213: WORK2 ← x (+) WORK2 214: x ← WORK2 + K4 215: x ← Rot2 (x) + x 216: WORK1 ← WORK1 (+) x 217: WORK2 ← WORK2 (+) WORK1 218: Output data of WORK1 Upper 32 bits of W
ORK2 is output as the lower 32 bits of the output data.

As described above, when the functions π1 to π4 are defined as shown in FIG. 2, this embodiment can be expressed by a composite function as C = π1, π4, π3, π2, π1 (M).

All functions πi · πi (i = 1 to 4) have the property of repeating the same function conversion twice and returning as πi · πi (x) = x.

Therefore, if M = π1, π2, π3, π4, π1 (C) is used as the decryption function, the ciphertext C can be returned to the original plaintext M.

(2) Modification Example 1 of Embodiment A process obtained by repeating the process corresponding to the conversion functions π1 to π4 twice in the above embodiment may be used as the cryptographic conversion. That is, the cryptographic conversion is performed by C = π1 · π4.・ Π3 ・ π2 ・ π1 ・ π4 ・ π3 ・ π2
・ It may be π1 (M).

At this time, the equation of the decoding conversion is M = π1, π2, π3, π4, π1, π2, π3, π4.
Π1 (C)

Similarly, in general, what is obtained by repeating this embodiment n times may be used as encryption conversion.

(3) Second Modified Example of Embodiment FIG. 4 shows another embodiment of the present invention.

401: Input data M is divided into upper 16 bits M1 and lower 16 bits M2.

402: The exclusive OR of the bits of M1 and M2 is calculated.

WORK2 ← M1 + M2 Hereinafter, + indicates the same processing.

403: Modulo subtraction of x and key data K1 is performed.

X ← x−K1 Here, x−K1 indicates a modulo subtraction modulo 216, that is, the remainder obtained by dividing the difference between x and K1 by 216.

Hereinafter, "-" indicates the same processing.

404: After cyclically shifting x by 2 bits to the left, modulo subtraction of the data and 1 is performed.

X ← Rot (x) −x−1 Hereinafter, Rot2 indicates the same processing.

405: After x is cyclically shifted left by 4 bits, exclusive OR of the data and x is obtained.

X ← Rot4 (x) (+) x Hereinafter, Rot4 indicates the same processing.

406: WORK1 ← x (+) M1 407: x ← x−K2y ← x 408: x ← Rot2 (x) −x−1 409: Rot8 (x) − (x∧y) Here, Rot8 ( x) indicates that x is cyclically shifted left by 8 bits. In addition, x∧y indicates that a logical AND of x and y corresponding to bits is taken.

410: WORK2 ← x (+) WORK2 411: x ← WORK2-K3 412: x ← Rot2 (x) −x−1 413: WORK1 ← WORK1 (+) x 414: WORK2 ← WORK2 (+) WORK1 415 : WORK1 as upper 16 bits of output data, W
ORK2 is output as the lower 16 bits of the output data.

(4) Third Modification of Embodiment FIG. 5 shows another embodiment of the present invention.

501: Input data M is divided into upper 8 bits M1 and lower 8 bits M2.

502: An exclusive OR operation corresponding to the bits of M1 and M2 is performed.

WORK2 ← M1 (+) M2 Hereinafter, + indicates the same processing.

503: Modulo addition of x and key data K1 is performed.

X ← WORK2 + K1 y ← x Here, x + K1 indicates a modulo addition modulo 28 in which the difference between x and K1 is divided by 28.

Hereinafter, + indicates the same processing.

504: After shifting x by 2 bits to the left, modulo addition of the data and x and 1 is performed.

X ← Rot2 (x) + x + 1 Hereinafter, Rot2 indicates the same processing.

505: x ← Rot4 (x) + (x∧y) Here, Rot4 (x) indicates that x is cyclically shifted left by 4 bits. In addition, x∧y indicates that a logical AND of x and y corresponding to bits is taken.

506: WORK1 ← WORK1 (+) x 507: x ← WORK1 + K2 508: x ← Rot4 (x) + x + 1 509: WORK2 ← WORK2 (+) x 510: WORK1 ← WORK1 (+) WORK2 511: Output WORK1 Upper 8 bits of WO
RK2 is output as the lower 8 bits of the output data.

(5) Fourth Modified Example of Embodiment FIG. 6 shows another embodiment of the present invention.

(1) Using a message 62 for performing authentication as key data, an arbitrary initial value 61 is encrypted using an algorithm 63 according to the present invention.

(2) The encryption result 64 is encrypted again with the subsequent data of the message used in (1), and this operation is repeated until the end of the message.

(3) The final encryption result is output as the message authentication code 65.

(6) Fifth Modification of Embodiment FIG. 7 shows another embodiment of the present invention. This IC card generates an authentication code of the message.

(1) An initial value 76 necessary for message authentication is transmitted to the microcomputer 72 in the IC card 71 through the I / O 74.

(2) A message 77 for performing authentication is sent to (1)
The microcomputer 72 generates the authentication code 78 using the encryption software 75 stored in the memory 73 in the same manner as described above.

In this embodiment, substitution and transposition are repeated as shown in FIG.

That is, in the embodiment shown in FIG.
04), (207, 208), (210, 211),
The processing of (214, 215) has the form of x ← x + Kix ← Rot2 (x) + (x) +1, which is obtained by dividing 32-bit data into blocks each having 4 bits. Substitution processing for each block is performed by the above two data conversions.
It can be seen that they are going all at once for the block.

Here, 4-bit block data A = (a1, a2, a3, a4), where ai = 1 or 0 (i = 1 to 4), B = (b1, b2, b3, b4) However, the fact that the conversion is made to bi = 1 or 0 (i = 1 to 4) means that the Boolean algebra operation f
1, f2, f3, and f4 exist; b1 = f1 (a1, a2, a3, a4) b2 = f2 (a1, a2, a3, a4) b3 = f3 (a1, a2, a3, a4) b4 = f4 (a1, a2, a3, a4).

Further, 205, 209 and 212 in FIG. 2 are (1) x ← Rot4 (x) (+) x (2) x ← Rot8 (x) (+) x (3) x ← Rot16 (x ) + (X∧y), which are (1) transposed to perform a 4-bit left circular shift and then further substituted, (2) 8-bit left circular The figure shows a process of performing a transposition after performing a transposition of performing a shift, and a process of performing (3) a 16-bit left circular shift.

As is apparent from FIG. 3, any bit change in the first 32 bits of data is the last 32 bits.
It can be seen that all bits of data are affected.

[0079]

As a result, it can be seen that the present embodiment has an effect of efficiently performing encryption conversion having a high degree of randomness.

[Brief description of the drawings]

FIG. 1 shows an embodiment of a cryptographic conversion device for implementing the present invention.

FIG. 2 is a flowchart showing details of encryption conversion in FIG. 1;

FIG. 3 is an explanatory diagram showing that the embodiment of the present invention efficiently repeats substitution conversion and transposition conversion.

FIG. 4 is a flowchart showing details of cryptographic conversion when a 16-bit microcomputer is used.

FIG. 5 is a flowchart showing details of encryption conversion when an 8-bit microcomputer is used.

FIG. 6 is a flowchart illustrating a method for generating a message authentication code using a cryptographic algorithm according to the present invention.

FIG. 7 is a configuration diagram of an IC card that generates a message authentication code using an encryption algorithm according to the present invention.

[Explanation of symbols]

100: key data, 101: plaintext, 102: 32-bit microcomputer, 103: program, 104:
Cryptogram.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Ryoichi Sasaki 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture, Ltd. System Development Laboratory, Hitachi, Ltd. (56) References JP-A-63-58538 (JP, A) D . W. Davies and W. L. Price / Translated by Tadahiro Kamizono, Network Security, Japan, Nikkei McGraw-Hill, December 5, 1985, 1st edition, 1st press, p. 57-58H. Feistel, Cryptography and Computer Privacy, USA, Scientific American, Vol. 5, p. 15-23 (58) Field surveyed (Int. Cl. ⁷ , DB name) G09C 1/00

Claims (2)

(57) [Claims] 1. An addition operation of two 32- bit data can be executed by an addition instruction of one instruction by using a message as an initial value of a 64- bit length, and one 32- bit data is circulated by m bits. A code generation method for converting a shift operation into a 64- bit length code by an arithmetic unit capable of processing in 32-bit units, which can be executed by one circular shift instruction, wherein the message stored in a message storage means is provided. Or
Luo each cut out key data K2, K3 of 32-bit length, A, B and each 32-bit data, π3 (A, B) and a 32-bit data A, first of A and the key data K2 1 is performed, the data obtained from the first addition is subjected to a cyclic shift by a first number of bits, and the data obtained from the cyclic shift by the first number of bits is subjected to a key. A second addition operation with the data K3 is performed, a cyclic shift is performed on the data obtained from the second addition operation with a second number of bits different from the first, and further, the data is obtained with the second number of bits. 3 was subjected to the third addition operation between data and B obtained from the cyclic shift
A function for outputting a set of 2- bit data is used as a function. The key data K2 and K3 cut out from the message are compared with the initial value consisting of two 32- bit data.
With, the addition operation processing including operations defined by the function π3 using the additive instruction, cyclic shift of the two 32-bit length obtained as a result of executing by the arithmetic unit using the cyclic shift instruction A code generation method, comprising: generating the 64- bit length code from data. 2. A 32-bit unit for converting a 64- bit length initial value into a 64- bit length code using a message.
A code generating device having a processable calculator, key data K of each 32 bits long from the message
2. A cutout means for cutting out K3, A and B each being 32- bit data, and π3 (A, B) being a 32- bit data A, and performing a first addition operation of A and key data K2. Performs a cyclic shift by a first number of bits on data obtained from the first addition operation, and performs a second shift of key data K3 on data obtained from the circular shift by the first number of bits. Is performed, the data obtained from the second addition operation is subjected to a cyclic shift with a second number of bits different from the first, and the data obtained from the cyclic shift with the second number of bits is further performed. And a third addition operation of B and 3
A function that outputs a set of 2- bit data is used as a function. The key data K2 and K3 cut out from the message by the cut-out means are used for a function π3 with respect to the two initial values consisting of 32- bit data. Means for generating the 64- bit length code from two 32- bit length data obtained as a result of executing a process including an operation defined by the following.