CN113238897B - System-level test method and device for chip, computer equipment and storage medium - Google Patents
System-level test method and device for chip, computer equipment and storage medium Download PDFInfo
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Abstract
The invention discloses a system-level testing method and device of a chip, computer equipment and a storage medium. The method comprises the following steps: constructing transmission data and expected information corresponding to a target message, and storing the expected information in a preset storage area; inputting the transmission data into a reference model matched with the chip to be tested; updating interface data in transmission data of the current flow to the self module through each environment module in the reference model, and adding expected module information matched with the self module into expected information of a storage area; and carrying out system level test on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message and the expected information currently stored in the storage area. The technical scheme of the embodiment of the invention provides a new mode for carrying out simulation test on the chip, meets the system-level chip test requirement, can provide richer system-level chip test results for chip designers, and improves the development and online efficiency of the chip.
Description
Technical Field
The embodiment of the invention relates to a computer hardware technology, in particular to a chip testing technology, and especially relates to a system level testing method and device for a chip, computer equipment and a storage medium.
Background
In general, the data flow processing procedure in the network processor chip may simply include the following three parts: 1. slicing the received Ethernet message into a plurality of basic data units (i.e., cells); 2. generating some control information for each data unit through one or more modules in the chip, or storing, scheduling, editing and other operations for each data unit; 3. and assembling a plurality of data units into a complete message output.
Since the minimum processing object of each module in the network processing chip is a data unit, the existing simulation verification process of the network processing chip is mainly a simulation verification process of the module, that is, whether the behavior of each module in the network processing chip for processing the data unit is correct or not is verified in the simulation process.
The inventor has found that in the process of implementing the present invention, the main drawbacks of the prior art are: the prior art has no effective system-level chip test scheme which takes a message as a processing unit, and can not provide more abundant system-level chip test results for chip designers, which affects the development and online efficiency of chips to a certain extent.
Disclosure of Invention
The embodiment of the invention provides a system-level testing method, device, computer equipment and storage medium for chips, which provide a new method for performing simulation test on the chips and meet the system-level chip testing requirements.
In a first aspect, an embodiment of the present invention provides a system level testing method for a chip, including:
constructing transmission data and expected information corresponding to a target message, and storing the expected information in a preset storage area, wherein the expected information comprises an expected result message;
inputting transmission data into a reference model matched with a chip to be tested, wherein each environment module in the reference model corresponds to each entity module in the chip to be tested, and the initialized transmission data comprises a target message and interface data matched with the first environment module in the reference model;
updating interface data in transmission data of the current flow to the self module through each environment module in the reference model, and adding expected module information matched with the self module into expected information of a storage area;
and carrying out system level test on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message and the expected information currently stored in the storage area.
In a second aspect, an embodiment of the present invention further provides a system level testing apparatus for a chip, where the apparatus includes:
the initialization construction module is used for constructing transmission data and expected information corresponding to the target message, and storing the expected information in a preset storage area, wherein the expected information comprises an expected result message;
the transmission data input module is used for inputting transmission data into a reference model matched with the chip to be tested, each environment module in the reference model corresponds to each entity module in the chip to be tested, and the initialized transmission data comprises a target message and interface data matched with the first environment module in the reference model;
the expected information adding module is used for updating interface data in transmission data which is currently circulated to the self module through each environment module in the reference model, and adding expected module information matched with the self module into the expected information of the storage area;
and the system-level testing module is used for carrying out system-level testing on the chip to be tested according to the actual processing result output by the chip to be tested for the target message and the expected information currently stored in the storage area.
In a third aspect, an embodiment of the present invention further provides a computer apparatus, including:
At least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a system level test method of a chip according to any one of the embodiments of the present invention.
In a fourth aspect, embodiments of the present invention further provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform a system-level test method of a chip according to any one of the embodiments of the present invention.
According to the technical scheme, the expected result message is added into the expected information set in the initialization mode, the interface data in the transmission data of the current flow to the self module is updated through each environment module in the reference model, and after the expected module information matched with the self module is added into the expected information, the system level test can be carried out on the chip to be tested according to the actual processing result output by the chip to be tested for the target message, the expected result message in the expected information and the expected module information of each module, so that a new mode for carrying out simulation test on the chip is provided, the chip test requirement of the system level is met, richer system level chip test results can be provided for chip designers, and further the development and online efficiency of the chip can be improved.
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FIG. 1 is a flow chart showing an implementation of a system level test method for a chip according to a first embodiment of the present invention;
FIG. 2 is a flow chart showing an implementation of a system level test method for a chip in accordance with a second embodiment of the present invention;
FIG. 3 is a flow chart showing an implementation of a system level test method for a chip in accordance with a third embodiment of the present invention;
FIG. 4 is a schematic diagram of a system level testing apparatus for a chip according to a fourth embodiment of the present invention;
fig. 5 is a schematic structural diagram of a computer device in a fifth embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Example 1
Fig. 1 is a flowchart of a system level test method for a chip according to a first embodiment of the present invention, where the present embodiment is applicable to a case of performing a system level simulation test on a network processor chip in units of messages, and the method may be performed by a system level test device of the chip, where the device may be implemented by software and/or hardware, and may be generally integrated into a computer device for implementing a chip test function.
The method of the embodiment of the invention specifically comprises the following steps:
s110, constructing transmission data and expected information corresponding to the target message, and storing the expected information in a preset storage area.
Wherein the expected information comprises an expected result message.
In this embodiment, in order to implement the simulation test of the chip to be tested (typically, the network processor chip), it is necessary to first build a reference model matching the chip to be tested. Wherein, each environmental module in the reference model corresponds to each entity module in the chip to be tested one by one.
It should be emphasized that the chip to be tested is a hardware design model actually constructed by a chip designer, and the chip to be tested includes at least one entity module, where each entity module is a hardware entity for implementing a set data unit (cell) processing function. The reference model is a simulation model built by a chip verifier aiming at the chip to be tested, the simulation model comprises at least one environment module, one environment module corresponds to one entity module, and the environment module is used for carrying out environment simulation on the matched entity module.
In this embodiment, after the actual data processing results and the simulation processing results of the chip to be tested and the reference model for the same target packet are obtained respectively, the system level verification can be performed on the chip to be tested by comparing the differences between the two results. To meet the above-mentioned verification requirement, it is necessary to first construct transmission data and expected information corresponding to the target message.
The target message is a message actually input into the chip to be tested for actual data processing. Accordingly, in order to implement the simulation processing on the target message, it is necessary to first construct the expected information corresponding to the target message.
The expected information refers to simulation expected results of actual processing results of the chip to be tested. The expected information includes an expected result message in advance, and the expected result message refers to an ideal result output by the chip to be tested after the target message is input to the chip to be tested and processed according to an expected design requirement. By adding the expected result message into the expected information, after the actual processing result output by the chip to be tested aiming at the target message, whether the chip to be tested is correctly executed or not can be verified by taking the message as a unit, and the ideal processing result is output, namely, the most primary system level test requirement can be met.
The purpose of storing the expected information in the preset storage area is to enable each environment module in the reference model to access the expected information, and add the expected module information of the respective environment module to the expected information so as to perform the system level test with higher level requirements.
In an optional implementation manner of this embodiment, constructing the expected information corresponding to the target packet may include: constructing initialized expected information; generating an expected result message corresponding to the target message according to the message attribute information of the target message and the design index of the chip to be tested, and writing the expected result message into the expected information.
Specifically, the initialized expected information may be a blank file with a set file format, and after the expected result message is obtained, the expected result message may be added into the blank file.
The method comprises the steps of carrying out prediction on a chip processing operation form of a target message according to message attribute information of the target message and design indexes of a chip to be detected, and finally obtaining a predicted result message. The message attribute information may include: message type, message length, message version, etc.
In a specific example, according to the message attribute information of the target message and the design index of the chip to be tested, it is first expected that the processing flow needs to be performed on the target message and the information such as the output port of the target message, and then, according to the information, the expected result message corresponding to the target message can be determined.
S120, inputting the transmission data into a reference model matched with the chip to be tested.
As described above, after the transmission data is constructed, the transmission data may be input to the reference model constructed based on the chip to be tested, so as to implement the simulation of the process of actually processing the target message by the chip to be tested.
It should be noted that, when each environmental module in the reference model performs simulation processing of the actual entity module, the processed data is the data transferred from the previous environmental module to the module, and the processed data is continuously sent to the next environmental module. Based on this, the concept of interface data is defined in the present embodiment. Interface data is understood as control information, and each environment module can determine specific data content actually required to be processed by its own module by combining the interface data with a target message.
Taking the chip to be tested as an example and not by way of limitation, the exchange chip may be used as the control information including: source IP address, destination IP address, source MAC address, destination MAC address, VLAN ID, etc.
The transmission data refers to data which is circulated and transferred in each environment module in the reference model in the simulation test process, wherein the initialized transmission data comprises a target message and interface data matched with the first environment module in the reference model.
Correspondingly, after receiving the transmission data, the first environmental module in the reference model can determine specific data content which needs to be processed by the self module by analyzing the target message and the interface data aiming at the self module, and then can update the current interface data in the transmission data based on the specific data content and send the transmission data to the next environmental module.
In an optional implementation manner of this embodiment, the update manner of the interface data may be: adding one or more items of control information to the interface data, or removing one or more items of control information, or modifying one or more items of control information, etc.
Correspondingly, each environment module except the first environment module in the reference model can correspondingly update the interface data in the transmission data after receiving the transmission data sent by the previous environment module, and then send the transmission data to the next environment module.
In this embodiment, the transmission data including the target message and the interface data is provided to each environmental module in the reference model, so that the reference model simulates the real processing procedure of the chip to be tested on the target message.
S130, updating interface data in transmission data of the current flow to the self module through each environment module in the reference model, and adding expected module information matched with the self module into expected information of a storage area.
In this embodiment, after the transmission data is input into the reference model, the transmission data is transferred in circulation in each environment module in the reference model.
In a specific example, the reference model includes an environment module a, an environment module B, and an environment module C that are sequentially connected. The transmission data is input from the first environmental module A in the reference model, is processed by the environmental module A, flows from the environmental module A to the environmental module B for processing, flows from the environmental module B to the environmental module C for processing, and is finally output by the environmental module C.
When each environment module receives the transmission data transferred to the self module, updating the interface data in the transmission data transferred to the self module according to the target message and the current updated interface data included in the received transmission data, and adding the expected module information matched with the self module into the expected information of the storage area.
The expected module information refers to operation description of all expected processing expected to be performed on the transmission data or setting description information of a matched module setting mode and the like of an environment module after receiving the transmission data. Through the arrangement, after the reference model finally outputs the transmission data, the finally obtained expected information comprises the expected module information obtained by each environment module aiming at the transmission data besides the expected result message.
In an optional application scenario of this embodiment, the chip to be tested may be a switch chip. Correspondingly, the expected module information can be various exchange process information obtained after the simulation interaction processing of each environment module. Typically, the present embodiment is not limited to the egress port information, the forwarding type information, the forwarding attribute information, and the like.
The forwarding type information may be a secondary forwarding type (MAC forwarding) or a tertiary forwarding type (IP forwarding) of the packet, and the forwarding attribute information may include: (multicast group ID information of multicast message, VLAN information to which the message belongs, etc.).
The reason for this is that although the consistency between the actual processing result output by the chip to be tested for the target message and the expected result message is compared, the most primary system level test requirement can be achieved. However, there is an extreme case that when one or more entity modules in the chip to be tested are incorrectly configured, correspondingly, one or more environment modules in the environment module are also incorrectly configured. At this time, if the above-mentioned one or more error configuration modes, the actual processing result obtained by the final combined action is consistent with the expected result message, although the system level test of the message is verified, the error configuration information is actually required to be corrected, but cannot be detected effectively, so that the system level test with higher level requirements can be further performed in combination with the expected module information obtained by each environment module for the transmission data.
In an optional implementation manner of this embodiment, by referring to each environmental module in the model, adding the expected module information matched with the own module to the expected information of the storage area may include:
and calling an information access interface to access the storage area through each environment module in the reference model so as to add expected module information matched with the self module into the expected information of the storage area.
In this alternative embodiment, in order to ensure the security of the expected information stored in the storage area, an information access interface corresponding to the storage area may be formed, and the permission to call the information access interface may be allocated to each environment module in the reference model. Only if the environment module of the information access interface is successfully called, the expected information can be obtained from the storage area and is stored in the storage area again after the information of the expected information is updated.
S140, performing system level test on the chip to be tested according to the actual processing result output by the chip to be tested for the target message and the expected information currently stored in the storage area.
As described above, by using the actual processing result output by the chip to be tested for the target message, the expected result message included in the currently stored expected information and the expected module information respectively corresponding to each of the environmental modules, two different levels of system level tests may be performed.
In an optional implementation manner of this embodiment, according to an actual processing result output by the chip to be tested for the target message and the expected information currently stored in the storage area, performing the system level test on the chip to be tested may include:
according to the actual processing result and the expected result message in the expected information, verifying the processing correctness of the message;
and carrying out self-consistency verification on each environment module according to the expected module information respectively corresponding to each environment module in the expected information.
In this optional embodiment, the target message may be input into the chip to be tested, and each entity module in the chip to be tested performs step-by-step processing on a plurality of data units corresponding to the target message, and finally assembles the plurality of data units into a complete message, and outputs the complete message as an actual processing result.
And then, comparing the consistency between the actual processing result and an expected result message in the expected information, and carrying out system-level chip test by taking the message as a processing unit.
Further, by recording expected module information corresponding to each of the environmental modules in the expected information, it is possible to perform verification of self-consistency between the environmental modules after the system test is completed. The self-consistency verification is to verify whether each environment has consistency and has no contradictory processing mode for processing the same target message.
In a specific example, the reference model includes an environment module a and an environment module B, where the environment module a performs a class a operation for a class a message, performs a class B operation for a class B message, and the environment module B performs a class a 'operation for a class a message and performs a class B' operation for a class B message. Correspondingly, if the expected module information recorded by the environment module A aiming at the target message is determined to be A operation after the expected information is acquired, and the expected module information recorded by the environment module B aiming at the target message is determined to be B' operation, the environment module A and the environment module B are not verified by self-consistency.
In another specific example, the reference model includes an environment module C and an environment module D, where the multicast group ID recorded in the expected module information recorded by the environment module C for the target message is ID1, and the multicast group ID recorded in the expected module information recorded by the environment module D for the target message is ID2. At this time, the environment module C and the environment module D do not pass the self-consistency verification due to the inconsistency between the two.
At this time, the following error conditions may occur: for example, the configuration in the environment module a or the environment module B is incorrect, or the configuration in the entity module a corresponding to the environment module a or the entity module B corresponding to the environment module B is incorrect, or both the environment module a and the entity module a corresponding to the environment module a are designed to be in error, but the error results are the same, or both the environment module B and the entity module B corresponding to the environment module B are designed to be in error, but the error results are the same.
Correspondingly, based on the verification result of the self-consistency verification, the various possible error conditions can be checked in sequence, so that secret design or configuration errors can be found in the test process as much as possible.
Specifically, the proper self-consistency verification rule can be designed according to the functions of each entity module in the chip to be tested and the processing operation actually performed, and the embodiment is not limited to this.
The advantages of this arrangement are that: even if the configuration of one or more environment modules is incorrect (and the configuration of the matched entity modules is incorrect), the problems can be detected in the system test process when the finally obtained actual processing result is consistent with the expected result message in the expected information, so that the problems in the chip can be detected to the greatest extent, and the system-level test requirement can be met.
According to the technical scheme, the expected result message is added into the expected information set in the initialization mode, the interface data in the transmission data of the current flow to the self module is updated through each environment module in the reference model, and after the expected module information matched with the self module is added into the expected information, the system level test can be carried out on the chip to be tested according to the actual processing result output by the chip to be tested for the target message, the expected result message in the expected information and the expected module information of each module, so that a new mode for carrying out simulation test on the chip is provided, the chip test requirement of the system level is met, richer system level chip test results can be provided for chip designers, and further the development and online efficiency of the chip can be improved.
Example two
Fig. 2 is a flowchart of a system level testing method for a chip according to a second embodiment of the present invention, where the embodiment is further refined, and the same or corresponding terms as those of the embodiment are explained, and the technical solution of the present embodiment is not repeated, and may be combined with one or more methods in the solution of the embodiment. As shown in fig. 2, the method provided by the embodiment of the present invention may include:
s210, constructing transmission data and expected information corresponding to the target message, and storing the expected information in a preset storage area.
The initialized transmission data comprises a target message and interface data matched with a first environment module in the reference model, and the expected information comprises an expected result message.
In this embodiment, in order to further enrich the test result of the system-on-chip, the target message included in the transmission data may be modified, so that the target message finally output by the reference model is a module modified message processed by each module capable of modifying the message in the reference model.
Correspondingly, after receiving the transmission data from the current flow to the self module, each environment module modifies the matched message of the target message in the currently received transmission data if the self module is determined to modify the target message.
S220, inputting the transmission data into a reference model matched with the chip to be tested.
Wherein, each environment module in the reference model corresponds to each entity module in the chip to be tested.
And S230, updating interface data in transmission data of the current flow to the self module through each environment module in the reference model, and adding expected module information matched with the self module into expected information of the storage area.
S240, through each environment module in the reference model, if the module operation executed by the module is determined to be the message modification operation, the message modification is carried out on the target message in the transmission data.
S250, verifying the processing correctness of the message according to the actual processing result output by the chip to be tested for the target message, the target message in the transmission data finally output by the reference model and the expected result message included in the expected information.
In this embodiment, since the target message is no longer a message in the original form in the transmission data finally output by the reference model, the message is modified by the module modified by each reference model. By comparing the consistency between the template modification message (i.e. the target message in the transmission data finally output by the reference model) and the expected result message, the modification mode of each environment module in the reference model on the target message can be known, and whether the environment module with the configuration error exists in the reference model can be further detected.
The advantages of this arrangement are that: the system-level chip test results can be further enriched, chip designers are assisted in rapidly and effectively positioning the actual chip design problem, and the development and online efficiency of the chip are further improved.
S260, carrying out self-consistency verification on the environment modules according to the expected module information corresponding to the environment modules in the expected information.
According to the technical scheme, the expected result message is added into the expected information set in the initialization mode, the interface data in the transmission data of the current flow to the self module is updated through each environment module in the reference model, and after the expected module information matched with the self module is added into the expected information, the system level test can be carried out on the chip to be tested according to the actual processing result output by the chip to be tested for the target message, the expected result message in the expected information and the expected module information of each module, so that a new mode for carrying out simulation test on the chip is provided, the chip test requirement of the system level is met, richer system level chip test results can be provided for chip designers, and further the development and online efficiency of the chip can be improved.
Example III
Fig. 3 is a flowchart of a system level testing method for a chip according to a third embodiment of the present invention, where the embodiment is further refined, and the same or corresponding terms as those of the foregoing embodiment are explained, and the technical solution of the present embodiment is not repeated, and may be combined with one or more methods in the solution of the foregoing embodiment. In this embodiment, an implementation scheme for performing a system level test on a chip for a plurality of different target packets is specifically provided.
As shown in fig. 3, the method provided by the embodiment of the present invention may include:
s310, adding a message identification mark matched with the target message into the target message.
In this embodiment, in order to make the system level test result of the chip more accurate, a specific implementation manner of determining the final system level test result according to the system level test results of multiple target messages is provided, and accordingly, it is necessary to add a matched message identification identifier to each target message first, so as to distinguish the actual processing result and the expected information obtained for different target messages.
Wherein, a unique number can be generated for each target message (the condition that different target messages correspond to the same unique number does not occur), and the unique number is packaged to a designated position in the payload of the target message.
S320, constructing transmission data and expected information corresponding to the target message, and adding the message identification mark into the transmission data and the expected information.
As described above, after the message identification identifier is added to the target message, the message identification identifier may be added to the transmission data and the expected information correspondingly.
S330, the expected information is stored in a preset storage area.
S340, through each environment module in the reference model, when receiving the transmission data from the current flow to the self module, positioning the expected information matched with the message identification in the storage area according to the message identification included in the transmission data.
In this embodiment, when each environment module receives the transmission data, the packet identification identifier may be first extracted from the transmission data, and then, based on the packet identification identifier, the expected information matched with the packet identification identifier may be located in the storage area.
Through the arrangement, even if the expected information stored in the storage area is a plurality of, the one-to-one correspondence between the transmission data and the expected information can be ensured by a simple method of matching the message identification marks.
S350, adding expected module information matched with the module in the expected information according to the interface data in the transmission data by referring to each environment module in the model, and updating the interface data in the transmission data.
In this embodiment, after each environmental module receives the transmission data, the specific data content input to the environmental module may be determined according to the target message and the interface data in the transmission data, and based on the specific data content, the environmental module may add the expected module information matched with the self module into the located expected information, so as to update the interface data currently stored in the transmission data.
The updated interface data is used for the subsequent reference model to continue to be used until the updated interface data is finally output.
S360, positioning expected information corresponding to the message identification mark in the storage area according to the message identification mark of the target message included in the actual processing result.
S370, performing system level test on the chip to be tested according to the expected information positioned in the storage area according to the actual processing result output by the chip to be tested for the target message.
Further, since the target message also has the message identification identifier, after the actual processing result corresponding to the target message is obtained, the expected information matched with the actual processing result is extracted based on the message identification identifier, so as to perform subsequent system level test on the target message.
According to the technical scheme, the expected result message is added into the expected information set in the initialization mode, the interface data in the transmission data of the current flow to the self module is updated through each environment module in the reference model, and after the expected module information matched with the self module is added into the expected information, the system level test can be carried out on the chip to be tested according to the actual processing result output by the chip to be tested for the target message, the expected result message in the expected information and the expected module information of each module, so that a new mode for carrying out simulation test on the chip is provided, the chip test requirement of the system level is met, richer system level chip test results can be provided for chip designers, and further the development and online efficiency of the chip can be improved.
Example IV
Fig. 4 is a schematic structural diagram of a system-level testing apparatus for a chip according to a fourth embodiment of the present invention, as shown in fig. 4, the apparatus includes: the build module 410, the transmit data input module 420, the expected information addition module 430, and the system level test module 440 are initialized.
The initialization construction module 410 is configured to construct transmission data and expected information corresponding to the target message, and store the expected information in a preset storage area, where the expected information includes an expected result message.
The transmission data input module 420 is configured to input transmission data into a reference model matched with the chip to be tested, where each environmental module in the reference model corresponds to each entity module in the chip to be tested, and the initialized transmission data includes a target message and interface data matched with the first environmental module in the reference model.
The expected information adding module 430 is configured to update interface data in the transmission data currently flowing to the self module by referring to each environment module in the model, and add expected module information matched with the self module to the expected information in the storage area.
The system level test module 440 is configured to perform a system level test on the chip to be tested according to the actual processing result output by the chip to be tested for the target message and the expected information currently stored in the storage area.
According to the technical scheme, the expected result message is added into the expected information set in the initialization mode, the interface data in the transmission data of the current flow to the self module is updated through each environment module in the reference model, and after the expected module information matched with the self module is added into the expected information, the system level test can be carried out on the chip to be tested according to the actual processing result output by the chip to be tested for the target message, the expected result message in the expected information and the expected module information of each module, so that a new mode for carrying out simulation test on the chip is provided, the chip test requirement of the system level is met, richer system level chip test results can be provided for chip designers, and further the development and online efficiency of the chip can be improved. Based on the above embodiments, the system level test module 440 may be specifically configured to:
According to the actual processing result and the expected result message in the expected information, verifying the processing correctness of the message;
and carrying out self-consistency verification on each environment module according to the expected module information respectively corresponding to each environment module in the expected information.
Based on the above embodiments, the initialization construction module 410 may specifically be configured to:
constructing initialized expected information;
generating an expected result message corresponding to the target message according to the message attribute information of the target message and the design index of the chip to be tested, and writing the expected result message into the expected information.
On the basis of the foregoing embodiments, the apparatus may further include a message modification module configured to:
after updating interface data in transmission data of a current flow to a self module through each environment module in a reference model, if the module operation executed by the self module is determined to be a message modification operation through each environment module in the reference model, carrying out matched message modification on a target message in the transmission data.
Based on the above embodiments, the system level test module 440 may be specifically configured to:
According to the actual processing result output by the chip to be tested for the target message, the target message in the transmission data finally output by the reference model and the expected result message included in the expected information, carrying out the verification of the processing correctness of the message;
and carrying out self-consistency verification on each environment module according to the expected module information respectively corresponding to each environment module in the expected information.
On the basis of the above embodiments, the method may further include a first packet identification identifier adding module, configured to:
before constructing transmission data and expected information corresponding to a target message, adding a message identification mark matched with the target message into the target message;
the apparatus may further include: the second message identification mark adding module is used for adding the message identification mark into the transmission data and the expected information after constructing the transmission data and the expected information corresponding to the target message;
the expected information adding module 430 may be specifically configured to:
when receiving transmission data from a current flow to a self module, positioning expected information matched with a message identification identifier in the storage area according to the message identification identifier included in the transmission data through each environment module in a reference model;
Adding expected module information matched with the module of the module in the expected information according to the interface data in the transmission data by referring to each environment module in the model, and updating the interface data in the transmission data;
the apparatus may further include an expected information positioning module for: before a system level test is carried out on a chip to be tested according to an actual processing result output by the chip to be tested for a target message and the expected information stored in a storage area, according to a message identification mark of the target message included in the actual processing result, locating the expected information corresponding to the message identification mark in the storage area.
Based on the above embodiments, the expected information adding module 430 may specifically be used to:
and calling an information access interface to access the storage area through each environment module in the reference model so as to add expected module information matched with the self module into the expected information of the storage area.
The system-level testing device of the chip provided by the embodiment of the invention can execute the system-level testing method of the chip provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
Example five
Fig. 5 is a schematic structural diagram of a computer device according to a fifth embodiment of the present invention, and as shown in fig. 5, the computer device includes a processor 50, a memory 51, an input device 52 and an output device 53; the number of processors 50 in the computer device may be one or more, one processor 50 being taken as an example in fig. 5; the processor 50, the memory 51, the input means 52 and the output means 53 in the computer device may be connected by a bus or by other means, in fig. 5 by way of example.
The memory 51 is used as a computer readable storage medium for storing software programs, computer executable programs, and modules, such as program instructions/modules corresponding to a system level test method of a chip in an embodiment of the present invention (e.g., an initialization construction module 410, a transmission data input module 420, an expected information adding module 430, and a system level test module 440 in a system level test apparatus of a chip). The processor 50 executes various functional applications of the computer device and data processing by running software programs, instructions and modules stored in the memory 51, i.e. implements the system level test method of the chip described above, which includes:
Constructing transmission data and expected information corresponding to a target message, and storing the expected information in a preset storage area, wherein the expected information comprises an expected result message;
inputting transmission data into a reference model matched with a chip to be tested, wherein each environment module in the reference model corresponds to each entity module in the chip to be tested, and the initialized transmission data comprises a target message and interface data matched with the first environment module in the reference model;
updating interface data in transmission data of the current flow to the self module through each environment module in the reference model, and adding expected module information matched with the self module into expected information of a storage area;
and carrying out system level test on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message and the expected information currently stored in the storage area.
The memory 51 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for functions; the storage data area may store data created according to the use of the terminal, etc. In addition, memory 51 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some examples, memory 51 may further comprise memory located remotely from processor 50, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 52 is operable to receive input numeric or character information and to generate key signal inputs related to user settings and function control of the computer apparatus. The output means 53 may comprise a display device such as a display screen.
Constructing transmission data and expected information corresponding to a target message, and storing the expected information in a preset storage area, wherein the expected information comprises an expected result message;
inputting transmission data into a reference model matched with a chip to be tested, wherein each environment module in the reference model corresponds to each entity module in the chip to be tested, and the initialized transmission data comprises a target message and interface data matched with the first environment module in the reference model;
updating interface data in transmission data of the current flow to the self module through each environment module in the reference model, and adding expected module information matched with the self module into expected information of a storage area;
and carrying out system level test on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message and the expected information currently stored in the storage area.
Example six
A sixth embodiment of the present invention also provides a storage medium containing computer-executable instructions, which when executed by a computer processor, are for performing a system-level test method of a chip, the method comprising:
Of course, the storage medium containing the computer executable instructions provided in the embodiments of the present invention is not limited to the above-described method operations, but may also perform related operations in the system level test method of the chip provided in any embodiment of the present invention.
From the above description of embodiments, it will be clear to a person skilled in the art that the present invention may be implemented by means of software and necessary general purpose hardware, but of course also by means of hardware, although in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, etc., and include several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to the embodiments of the present invention.
It should be noted that, in the above-mentioned embodiments of the search apparatus, each unit and module included are only divided according to the functional logic, but not limited to the above-mentioned division, as long as the corresponding functions can be implemented; in addition, the specific names of the functional units are also only for distinguishing from each other, and are not used to limit the protection scope of the present invention.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (7)
1. A system-level testing method of a chip, comprising:
constructing transmission data and expected information corresponding to a target message, and storing the expected information in a preset storage area, wherein the expected information comprises an expected result message;
Inputting transmission data into a reference model matched with a chip to be tested, wherein each environment module in the reference model corresponds to each entity module in the chip to be tested, and the initialized transmission data comprises a target message and interface data matched with the first environment module in the reference model;
updating interface data in transmission data of the current flow to the self module through each environment module in the reference model, and adding expected module information matched with the self module into expected information of a storage area;
performing system level test on the chip to be tested according to the actual processing result output by the chip to be tested for the target message and the expected information currently stored in the storage area;
after updating the interface data in the transmission data of the current flow to the self module by each environment module in the reference model, the method further comprises the following steps:
through each environment module in the reference model, if the module operation executed by the module is determined to be the message modification operation, the message modification of matching is carried out on the target message in the transmission data;
according to the actual processing result output by the chip to be tested for the target message and the expected information currently stored in the storage area, performing system-level test on the chip to be tested, including:
According to the actual processing result output by the chip to be tested for the target message, the target message in the transmission data finally output by the reference model and the expected result message included in the expected information, carrying out the verification of the processing correctness of the message;
and carrying out self-consistency verification on each environment module according to the expected module information respectively corresponding to each environment module in the expected information.
2. The method of claim 1, wherein constructing the expected information corresponding to the target message comprises:
constructing initialized expected information;
generating an expected result message corresponding to the target message according to the message attribute information of the target message and the design index of the chip to be tested, and writing the expected result message into the expected information.
3. The method of claim 1, further comprising, prior to constructing the transmission data and the expected information corresponding to the target message:
adding a message identification mark matched with the target message into the target message;
after constructing the transmission data and the expected information corresponding to the target message, the method further comprises the following steps:
adding the message identification mark into the transmission data and the expected information;
Updating interface data in transmission data of the current flow to the self module by referring to each environment module in the model, and adding expected module information matched with the self module into expected information of a storage area, wherein the method comprises the following steps:
when receiving transmission data from a current flow to a self module, positioning expected information matched with a message identification identifier in the storage area according to the message identification identifier included in the transmission data through each environment module in a reference model;
adding expected module information matched with the module of the module in the expected information according to the interface data in the transmission data by referring to each environment module in the model, and updating the interface data in the transmission data;
before the system-level test is performed on the chip to be tested according to the actual processing result output by the chip to be tested for the target message and the expected information currently stored in the storage area, the system-level test method further comprises the following steps:
and positioning expected information corresponding to the message identification mark in the storage area according to the message identification mark of the target message included in the actual processing result.
4. The method of claim 1, wherein adding expected module information matching the own module to expected information of the storage area by referring to each environment module in the model, comprises:
And calling an information access interface to access the storage area through each environment module in the reference model so as to add expected module information matched with the self module into the expected information of the storage area.
5. A system-level testing apparatus for a chip, comprising:
the initialization construction module is used for constructing transmission data and expected information corresponding to the target message, and storing the expected information in a preset storage area, wherein the expected information comprises an expected result message;
the transmission data input module is used for inputting transmission data into a reference model matched with the chip to be tested, each environment module in the reference model corresponds to each entity module in the chip to be tested, and the initialized transmission data comprises a target message and interface data matched with the first environment module in the reference model;
the expected information adding module is used for updating interface data in transmission data which is currently circulated to the self module through each environment module in the reference model, and adding expected module information matched with the self module into the expected information of the storage area;
the system-level testing module is used for carrying out system-level testing on the chip to be tested according to the actual processing result output by the chip to be tested for the target message and the expected information currently stored in the storage area;
The message modifying module is used for modifying the message matched with the target message in the transmission data by each environment module in the reference model after updating the interface data in the transmission data currently flowing to the self module by each environment module in the reference model if the module operation executed by the self module is determined to be the message modifying operation;
the system level test module is specifically configured to:
according to the actual processing result output by the chip to be tested for the target message, the target message in the transmission data finally output by the reference model and the expected result message included in the expected information, carrying out the verification of the processing correctness of the message;
and carrying out self-consistency verification on each environment module according to the expected module information respectively corresponding to each environment module in the expected information.
6. A computer device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the system level test method of the chip of any one of claims 1-4.
7. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the system-level test method of the chip of any one of claims 1-4.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107688537A (en) * | 2017-08-25 | 2018-02-13 | 泰康保险集团股份有限公司 | Method of testing, device and front end processor |
| CN109802864A (en) * | 2017-11-16 | 2019-05-24 | 中兴通讯股份有限公司 | Chip design and verification method, device and chip tester |
| CN110399293A (en) * | 2019-06-21 | 2019-11-01 | 平安科技（深圳）有限公司 | System detection method, device, computer equipment and storage medium |
| CN110941519A (en) * | 2019-12-17 | 2020-03-31 | 锐捷网络股份有限公司 | Chip testing method and device of network equipment |
-
2021
- 2021-04-25 CN CN202110450217.2A patent/CN113238897B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107688537A (en) * | 2017-08-25 | 2018-02-13 | 泰康保险集团股份有限公司 | Method of testing, device and front end processor |
| CN109802864A (en) * | 2017-11-16 | 2019-05-24 | 中兴通讯股份有限公司 | Chip design and verification method, device and chip tester |
| CN110399293A (en) * | 2019-06-21 | 2019-11-01 | 平安科技（深圳）有限公司 | System detection method, device, computer equipment and storage medium |
| CN110941519A (en) * | 2019-12-17 | 2020-03-31 | 锐捷网络股份有限公司 | Chip testing method and device of network equipment |
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