CN113238897A - System-level test method and device of chip, computer equipment and storage medium - Google Patents
System-level test method and device of chip, computer equipment and storage medium Download PDFInfo
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Abstract
The invention discloses a system level test method and device of a chip, computer equipment and a storage medium. The method comprises the following steps: constructing transmission data and expected information corresponding to the target message, and storing the expected information in a preset storage area; inputting transmission data into a reference model matched with a chip to be tested; updating interface data in transmission data currently transferred to the self module by referring to each environment module in the model, and adding expected module information matched with the self module into expected information in the storage area; and performing system level test on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message and the expected information currently stored in the storage area. The technical scheme of the embodiment of the invention provides a new mode for carrying out simulation test on the chip, meets the test requirement of the system-level chip, can provide richer system-level chip test results for chip designers, and improves the development and online efficiency of the chip.
Description
Technical Field
The embodiment of the invention relates to a computer hardware technology, in particular to a chip testing technology, and particularly relates to a chip system level testing method and device, computer equipment and a storage medium.
Background
In general, the data stream processing procedure in a network processor chip can simply include the following three parts: 1. slicing the received Ethernet message into a plurality of basic data units (namely cells); 2. generating some control information for each data unit through one or more modules in the chip, or performing operations such as storage, scheduling and editing on each data unit; 3. and assembling a plurality of data units into a complete message output.
Because the minimum processing object of each module in the network processing chip is a data unit, the existing simulation verification process for the network processing chip is mainly a simulation verification process for the module, that is, whether the behavior of each module in the chip for processing the data unit is correct is verified in the simulation process.
In the process of implementing the invention, the inventor finds out that the main defects of the prior art are as follows: in the prior art, an effective system-level chip test scheme using a message as a processing unit does not exist, and richer system-level chip test results cannot be provided for chip designers, so that the development and online efficiency of a chip are influenced to a certain extent.
Disclosure of Invention
The embodiment of the invention provides a system level test method and device of a chip, computer equipment and a storage medium, and aims to provide a new mode for carrying out simulation test on the chip and meet the system level chip test requirement.
In a first aspect, an embodiment of the present invention provides a system-level test method for a chip, including:
constructing transmission data and expected information corresponding to the target message, and storing the expected information in a preset storage area, wherein the expected information comprises an expected result message;
inputting transmission data into a reference model matched with a chip to be detected, wherein each environment module in the reference model corresponds to each entity module in the chip to be detected, and initialized transmission data comprise a target message and interface data matched with a first environment module in the reference model;
updating interface data in transmission data currently transferred to the self module by referring to each environment module in the model, and adding expected module information matched with the self module into expected information in the storage area;
and performing system level test on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message and the expected information currently stored in the storage area.
In a second aspect, an embodiment of the present invention further provides a system-on-chip testing apparatus, including:
the initialization construction module is used for constructing transmission data and expected information corresponding to the target message and storing the expected information in a preset storage area, wherein the expected information comprises an expected result message;
the transmission data input module is used for inputting transmission data into a reference model matched with the chip to be detected, each environment module in the reference model corresponds to each entity module in the chip to be detected, and initialized transmission data comprise a target message and interface data matched with a first environment module in the reference model;
the expected information adding module is used for updating interface data in transmission data currently transferred to the self module by referring to each environment module in the model, and adding expected module information matched with the self module into the expected information in the storage area;
and the system level test module is used for carrying out system level test on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message and the expected information currently stored in the storage area.
In a third aspect, an embodiment of the present invention further provides a computer device, including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a system level test method for a chip according to any of the embodiments of the present invention.
In a fourth aspect, the present invention further provides a non-transitory computer readable storage medium storing computer instructions, where the computer instructions are configured to cause the computer to execute the system level test method for a chip according to any one of the embodiments of the present invention.
According to the technical scheme of the embodiment of the invention, the expected result message is added into the expected information which is initialized, the interface data in the transmission data which is currently transferred to the module is updated by referring to each environment module in the model, and after the expected module information matched with the module is added into the expected information, the system level test can be carried out on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message, the expected result message in the expected information and the expected module information of each module.
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Fig. 1 is a flowchart illustrating an implementation of a system level testing method for a chip according to a first embodiment of the present invention;
FIG. 2 is a flowchart illustrating an implementation of a system-level testing method for a chip according to a second embodiment of the present invention;
FIG. 3 is a flowchart illustrating an implementation of a system-level testing method for a chip according to a third embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a system-on-chip testing apparatus according to a fourth embodiment of the present invention;
fig. 5 is a schematic structural diagram of a computer device in the fifth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a flowchart of a system-on-chip testing method according to an embodiment of the present invention, where the present embodiment is applicable to a case where a network processor chip is subjected to a system-on-chip simulation test in units of messages, and the method may be executed by a system-on-chip testing apparatus, which may be implemented by software and/or hardware, and may be generally integrated in a computer device for implementing a chip testing function.
The method of the embodiment of the invention specifically comprises the following steps:
s110, constructing transmission data and expected information corresponding to the target message, and storing the expected information in a preset storage area.
The expected information comprises an expected result message.
In this embodiment, in order to implement a simulation test on a chip to be tested (typically, a network processor chip), a reference model matching with the chip to be tested needs to be established first. And the environment modules in the reference model correspond to the entity modules in the chip to be tested one by one.
It should be emphasized that the chip to be tested is a hardware design model actually constructed by a chip designer, the chip to be tested includes at least one entity module, and each entity module is a hardware entity and is used for implementing a set data unit (cell) processing function. The reference model is a simulation model which is set up by a chip verifying person aiming at the chip to be tested, the simulation model comprises at least one environment module, one environment module corresponds to one entity module, and the environment module is used for carrying out environment simulation on the matched entity module.
In this embodiment, after the actual data processing result and the simulation processing result of the chip to be tested and the reference model for the same target packet are obtained, the difference between the two results is compared, so that the system level verification can be performed on the chip to be tested. In order to meet the above verification requirement, it is necessary to first construct transmission data and expected information corresponding to the target packet.
The target message is a message which is actually input into the chip to be tested for actual data processing. Accordingly, in order to implement the simulation processing on the target packet, it is necessary to first construct expected information corresponding to the target packet.
The expected information refers to a simulation expected result of an actual processing result of the chip to be tested. The expected information includes an expected result message in advance, and the expected result message is an ideal result output after a target message is input to a chip to be tested and the chip to be tested processes the target message according to expected design requirements. By adding the expected result message into the expected information, after the actual processing result of the chip to be tested is output aiming at the target message, whether the chip to be tested is correctly executed or not can be verified by taking the message as a unit, and an ideal processing result is output, namely, the requirement of the primary system level test can be met.
The purpose of storing the expected information in the preset storage area is to enable each environment module in the reference model to access the expected information, and add the expected module information of each environment module to the expected information to perform a system level test with higher level requirements.
In an optional implementation manner of this embodiment, constructing the expected information corresponding to the target packet may include: constructing initialized expected information; and generating an expected result message corresponding to the target message according to the message attribute information of the target message and the design index of the chip to be tested, and writing the expected result message into the expected information.
Specifically, the initialized expected information may be a blank file with a set file format, and after obtaining the expected result message, the expected result message may be added to the blank file.
The expected result message can be finally obtained after the chip processing operation form of the target message is preset according to the message attribute information of the target message and the design index of the chip to be detected. The message attribute information may include: message type, message length, message version, and the like.
In a specific example, according to the message attribute information of the target message and the design index of the chip to be tested, information about which processing flows need to be performed on the target message, an output port of the target message, and the like can be expected first, and then an expected result message corresponding to the target message can be determined according to the information.
And S120, inputting the transmission data into a reference model matched with the chip to be tested.
As described above, after the transmission data is constructed, the transmission data may be input to the reference model constructed based on the chip to be tested, so as to implement analog simulation of the process of actually processing the target packet by the chip to be tested.
It should be noted that, referring to each environment module in the model, when performing simulation processing on an actual entity module, the processed data is data that is transferred to the module by a previous environment module, and the processed data is continuously sent to a subsequent environment module. Based on this, the concept of interface data is defined in the present embodiment. The interface data can be understood as some control information, and each environment module can determine specific data content which needs to be processed by the module of the environment module actually by combining the interface data with a target message.
Taking the chip to be tested as an exchange chip as an example, the control information may include, by way of example and not limitation: source IP address, destination IP address, source MAC address, destination MAC address, and VLAN ID.
The transmission data refers to data which is circulated and transmitted in each environment module in the reference model in the simulation test process, wherein the initialized transmission data comprises a target message and interface data matched with a first environment module in the reference model.
Correspondingly, after the first environment module in the reference model receives the transmission data, the specific data content to be processed by the self module can be determined by analyzing the target message and the interface data aiming at the self module in the transmission data, and then the current interface data in the transmission data can be updated based on the specific data content, and the transmission data is sent to the next environment module.
In an optional implementation manner of this embodiment, the updating manner of the interface data may be: adding one or more items of control information into the interface data, or removing one or more items of control information, or modifying one or more items of control information, etc.
Correspondingly, after receiving the transmission data sent by the previous environment module, each environment module except the first environment module in the reference model can correspondingly update the interface data in the transmission data and send the transmission data to the next environment module.
In this embodiment, the transmission data including the target packet and the interface data is provided to each environment module in the reference model, so that the reference model simulates a real processing process of the target packet by the chip to be tested.
S130, updating interface data in transmission data currently transferred to the self module by referring to each environment module in the model, and adding expected module information matched with the self module into the expected information in the storage area.
In this embodiment, after the transmission data is input into the reference model, the transmission data is transmitted in a stream in each environment module in the reference model.
In a specific example, the reference model includes an environment module a, an environment module B, and an environment module C, which are connected in sequence. The transmission data is input from the first environment module a in the reference model, and after being processed by the environment module a, the transmission data is firstly transferred from the environment module a to the environment module B for processing, and then transferred from the environment module B to the environment module C for processing until being finally output by the environment module C.
When each environment module receives transmission data transferred to the module, the interface data in the transmission data transferred to the module is updated according to a target message and the current updated interface data in the received transmission data, and expected module information matched with the module is added into the expected information in the storage area.
The expected module information refers to operation description of all expected processing to be performed on the transmission data by an environment module after the environment module receives the transmission data, or setting description information of a matched module setting mode, and the like. Through the arrangement, after the transmission data is finally output by the reference model, the finally obtained expected information comprises the expected result message and also comprises the expected module information obtained by each environment module according to the transmission data.
In an optional application scenario of this embodiment, the chip to be tested may be a switch chip. Correspondingly, the expected module information may be various exchange process information obtained after the simulation interaction processing is performed on each environment module. Typically, the egress port information, the forwarding type information, the forwarding attribute information, and the like, which is not limited in this embodiment.
The forwarding type information may be a secondary forwarding type (MAC forwarding) or a tertiary forwarding type (IP forwarding) of the packet, and the forwarding attribute information may include: (multicast group ID information of multicast packet and VLAN information to which packet belongs).
The reason for this is that the most primary system level test requirement can be achieved by comparing the consistency between the actual processing result output by the chip under test for the target message and the expected result message. However, there is an extreme case that when one or more entity modules in the chip to be tested are configured incorrectly, one or more environment modules in the environment module are also configured incorrectly. At this time, if the actual processing result obtained by the final combined action is consistent with the expected result message in the one or more error configuration modes, although the system level test of the message passes the verification, the entity module which is configured incorrectly is actually required to be corrected, and the error configuration information cannot be effectively detected, so that the system level test which requires a higher level can be further performed by combining the expected module information which is obtained by each environment module for the transmission data.
In an optional implementation manner of this embodiment, adding expected module information matching with its own module to the expected information in the storage area by referring to each environment module in the model may include:
and calling an information access interface to access the memory area by referring to each environment module in the model so as to add expected module information matched with the module of the memory area into the expected information of the memory area.
In this optional embodiment, in order to ensure the security of the expected information stored in the storage area, an information access interface corresponding to the storage area may be formed, and the calling authority for the information access interface may be assigned to each environment module in the reference model. The expected information can be obtained from the storage area only if the environment module of the information access interface is called successfully, and the expected information is stored in the storage area again after being updated.
And S140, performing system level test on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message and the expected information currently stored in the storage area.
As described above, by using the actual processing result output by the chip to be tested for the target packet, the expected result packet included in the currently stored expected information, and the expected module information respectively corresponding to each of the environment modules, two different levels of system level tests can be performed.
In an optional implementation manner of this embodiment, performing a system level test on the chip to be tested according to an actual processing result output by the chip to be tested for the target packet and the expected information currently stored in the storage area may include:
according to the actual processing result and an expected result message in the expected information, verifying the processing correctness of the message;
and carrying out self-consistency verification on each environment module according to expected module information which corresponds to each environment module in the expected information.
In this optional embodiment, the target packet may be input into the chip to be tested, each entity module in the chip to be tested performs step-by-step processing on a plurality of data units corresponding to the target packet, and finally assembles the plurality of data units into a complete packet, which is output as an actual processing result.
And then, comparing the consistency between the actual processing result and the expected result message in the expected information, and performing system-level chip test by using the message as a processing unit.
Furthermore, by recording the expected module information corresponding to each environment module in the expected information, the self-consistency verification can be performed between the environment modules after the system test is completed. The self-consistency verification is to verify whether the processing of each environment for the same target packet is consistent without conflicting processing modes.
In a specific example, the reference model includes an environment module a and an environment module B, where the environment module a performs a type a operation on a type a packet and performs a type B operation on a type B packet, and the environment module B performs an a 'operation on a type a packet and performs a B' operation on a type B packet. Correspondingly, if after obtaining the expected information, it is determined that the expected module information of the environment module a for the target message record is a operation a, and the expected module information of the environment module B for the target message record is a B' type operation, it indicates that the environment module a and the environment module B do not pass the self-consistency verification.
In another specific example, the reference model includes an environment module C and an environment module D, the multicast group ID recorded in the expected module information recorded by the environment module C for the target packet is ID1, and the multicast group ID recorded in the expected module information recorded by the environment module D for the target packet is ID 2. At this time, it is stated that the environment module C and the environment module D do not pass the self-consistency verification.
At this time, several error situations may occur: for example, the configuration of the environment module a or the environment module B is incorrect, or the configuration of the entity module a corresponding to the environment module a or the configuration of the entity module B corresponding to the environment module B is incorrect, or both the environment module a and the entity module a corresponding to the environment module a are designed to have errors, but the error results are the same, or both the environment module B and the entity module B corresponding to the environment module B are designed to have errors, but the error results are the same.
Accordingly, based on the verification result of the self-consistency verification, the various possible error conditions can be checked in sequence, so that a secret design or configuration error can be found in the test process as much as possible.
Specifically, a self-consistency verification rule suitable for the correspondence design may be designed according to the function and the actual processing operation of each entity module in the chip to be tested, which is not limited in this embodiment.
The advantages of such an arrangement are: even if the configuration of one or more environment modules is incorrect (so that the configuration of the matched entity module is incorrect), when the condition that the finally obtained actual processing result is consistent with the expected result message in the expected information occurs, the problem can be detected in the system test process, the problem occurring in the chip can be detected to the greatest extent, and the system level test requirement can be met.
According to the technical scheme of the embodiment of the invention, the expected result message is added into the expected information which is initialized, the interface data in the transmission data which is currently transferred to the module is updated by referring to each environment module in the model, and after the expected module information matched with the module is added into the expected information, the system level test can be carried out on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message, the expected result message in the expected information and the expected module information of each module.
Example two
Fig. 2 is a flowchart of a system-on-chip testing method according to a second embodiment of the present invention, where this embodiment further details the above-mentioned embodiment, and the same or corresponding terms as those in the above-mentioned embodiment are explained, and this embodiment is not repeated, and the technical solution of this embodiment may be combined with one or more methods in the solutions of the above-mentioned embodiment. As shown in fig. 2, a method provided in an embodiment of the present invention may include:
s210, constructing transmission data and expected information corresponding to the target message, and storing the expected information in a preset storage area.
The initialized transmission data comprises a target message and interface data matched with a first environment module in the reference model, and the expected information comprises an expected result message.
In this embodiment, in order to further enrich the system-on-chip test result, the target packet included in the transmission data may be modified, so that the target packet finally output by the reference model is a module modification packet processed by each module capable of modifying the packet in the reference model.
Correspondingly, after each environment module receives the transmission data currently transferred to the environment module, if the environment module determines that the environment module can modify the target message, the environment module modifies the matched message of the target message in the currently received transmission data.
And S220, inputting the transmission data into a reference model matched with the chip to be tested.
And each environment module in the reference model corresponds to each entity module in the chip to be tested.
And S230, updating interface data in the transmission data currently transferred to the self module by referring to each environment module in the model, and adding expected module information matched with the self module into the expected information in the storage area.
S240, by referring to each environment module in the model, if the module operation executed by the module is determined to be message modification operation, the matched message modification is carried out on the target message in the transmission data.
And S250, verifying the processing correctness of the message according to an actual processing result output by the chip to be tested aiming at the target message, the target message in the transmission data finally output by the reference model and an expected result message included by the expected information.
In this embodiment, in the transmission data finally output by the reference model, the target packet is not a packet in the original form any more, but a packet is modified by the module modified by each reference model. By comparing the consistency between the template modification message (i.e. the target message in the transmission data finally output by the reference model) and the expected result message, the modification mode of each environment module in the reference model to the target message can be known, and whether an environment module with configuration error exists in the reference model can be further detected.
The advantages of such an arrangement are: the system-level chip test result can be further enriched, a chip designer is assisted to quickly and effectively position the actual chip design problem, and the development and online efficiency of the chip are further improved.
And S260, carrying out self-consistency verification on each environment module according to expected module information which corresponds to each environment module in the expected information.
According to the technical scheme of the embodiment of the invention, the expected result message is added into the expected information which is initialized, the interface data in the transmission data which is currently transferred to the module is updated by referring to each environment module in the model, and after the expected module information matched with the module is added into the expected information, the system level test can be carried out on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message, the expected result message in the expected information and the expected module information of each module.
EXAMPLE III
Fig. 3 is a flowchart of a system-on-chip testing method according to a third embodiment of the present invention, where this embodiment further details the above-mentioned embodiment, and the same or corresponding terms as those in the above-mentioned embodiment are explained, and this embodiment is not repeated, and the technical solution of this embodiment may be combined with one or more methods in the solutions of the above-mentioned embodiment. In this embodiment, an implementation scheme for performing a system level test on a chip for a plurality of different target packets is specifically provided.
As shown in fig. 3, a method provided in an embodiment of the present invention may include:
s310, adding a message identification mark matched with the target message into the target message.
In this embodiment, in order to make the system level test result of the chip more accurate, a specific implementation manner for determining the final system level test result according to the system level test results of the multiple target packets is provided, and accordingly, a matched packet identification identifier needs to be added to each target packet to distinguish actual processing results and expected information obtained for different target packets.
First, a unique number may be generated for each target packet (a situation that different target packets correspond to the same unique number may not occur), and the unique number may be encapsulated to a specified position in the payload of the target packet.
S320, constructing transmission data and expected information corresponding to the target message, and adding the message identification mark into the transmission data and the expected information.
As mentioned above, after adding the message identification mark to the target message, the message identification mark may be added to the transmission data and the expected information.
And S330, storing the expected information in a preset storage area.
S340, by referring to each environment module in the model, when transmission data which are currently transferred to the self module are received, according to the message identification mark included in the transmission data, expected information matched with the message identification mark is positioned in the storage area.
In this embodiment, when each environment module receives transmission data, a message identification identifier may be first extracted from the transmission data, and then expected information matching the message identification identifier may be located in the storage area based on the message identification identifier.
Through the arrangement, even if a plurality of pieces of expected information are stored in the storage area, the one-to-one correspondence between the transmission data and the expected information can be ensured through a simple mode of matching the message identification marks.
And S350, adding expected module information matched with the self module into the located expected information according to the interface data in the transmission data by referring to each environment module in the model, and updating the interface data in the transmission data.
In this embodiment, after receiving the transmission data, each environment module may determine specific data content input to the environment module according to a target packet and interface data in the transmission data, and based on the specific data content, the environment module may add expected module information matched with its own module to the located expected information, and further update interface data currently stored in the transmission data.
And the updated interface data is used for the subsequent reference model to continue to use until the updated interface data is finally output.
S360, according to the message identification mark of the target message included in the actual processing result, positioning expected information corresponding to the message identification mark in the storage area.
S370, according to the actual processing result output by the chip to be tested aiming at the target message, the expected information positioned in the storage area is used for carrying out system level test on the chip to be tested.
Further, since the target packet also has the packet identification identifier, after an actual processing result corresponding to the target packet is obtained, expected information matching the actual processing result is extracted based on the packet identification identifier, so as to perform subsequent system level test on the target packet.
According to the technical scheme of the embodiment of the invention, the expected result message is added into the expected information which is initialized, the interface data in the transmission data which is currently transferred to the module is updated by referring to each environment module in the model, and after the expected module information matched with the module is added into the expected information, the system level test can be carried out on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message, the expected result message in the expected information and the expected module information of each module.
Example four
Fig. 4 is a schematic structural diagram of a system-on-chip testing apparatus according to a fourth embodiment of the present invention, as shown in fig. 4, the apparatus includes: an initialization build module 410, a transmission data input module 420, an expected information addition module 430, and a system level test module 440.
The initialization construction module 410 is configured to construct transmission data and expected information corresponding to the target packet, and store the expected information in a preset storage area, where the expected information includes an expected result packet.
And the transmission data input module 420 is configured to input transmission data into a reference model matched with the chip to be tested, where each environment module in the reference model corresponds to each entity module in the chip to be tested, and the initialized transmission data includes a target packet and interface data matched with a first environment module in the reference model.
And an expected information adding module 430, configured to update interface data in the transmission data currently flowing to the self module by referring to each environment module in the model, and add expected module information matching the self module to the expected information in the storage area.
The system level test module 440 is configured to perform a system level test on the chip to be tested according to an actual processing result output by the chip to be tested for the target packet and the expected information currently stored in the storage area.
According to the technical scheme of the embodiment of the invention, the expected result message is added into the expected information which is initialized, the interface data in the transmission data which is currently transferred to the module is updated by referring to each environment module in the model, and after the expected module information matched with the module is added into the expected information, the system level test can be carried out on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message, the expected result message in the expected information and the expected module information of each module. On the basis of the foregoing embodiments, the system level test module 440 may be specifically configured to:
according to the actual processing result and an expected result message in the expected information, verifying the processing correctness of the message;
and carrying out self-consistency verification on each environment module according to expected module information which corresponds to each environment module in the expected information.
On the basis of the foregoing embodiments, the initialization construction module 410 may be specifically configured to:
constructing initialized expected information;
and generating an expected result message corresponding to the target message according to the message attribute information of the target message and the design index of the chip to be tested, and writing the expected result message into the expected information.
On the basis of the foregoing embodiments, the apparatus may further include a message modification module, configured to:
after updating interface data in transmission data currently transferred to the self module through each environment module in the reference model, if the module operation executed by the self module is determined to be message modification operation through each environment module in the reference model, message modification matched with a target message in the transmission data is carried out.
On the basis of the foregoing embodiments, the system level test module 440 may be specifically configured to:
according to an actual processing result output by the chip to be tested aiming at the target message, the target message in the transmission data finally output by the reference model and an expected result message included by the expected information, verifying the processing correctness of the message;
and carrying out self-consistency verification on each environment module according to expected module information which corresponds to each environment module in the expected information.
On the basis of the foregoing embodiments, the method may further include a first packet identifier adding module, configured to:
before constructing transmission data and expected information corresponding to a target message, adding a message identification mark matched with the target message into the target message;
the apparatus may further include: the second message identification mark adding module is used for adding the message identification mark into transmission data and expected information after the transmission data and the expected information corresponding to the target message are constructed;
the expected information adding module 430 may be specifically configured to:
by referring to each environment module in the model, when transmission data which is currently transferred to the self module is received, according to a message identification mark included in the transmission data, expected information matched with the message identification mark is positioned in the storage area;
adding expected module information matched with the module per se into the located expected information according to interface data in the transmission data by referring to each environment module in the model, and updating the interface data in the transmission data;
the apparatus may further comprise an expected information location module to: before a chip to be tested is tested in a system level test according to an actual processing result output by the chip to be tested aiming at a target message and expected information currently stored in a storage area, expected information corresponding to a message identification mark is positioned in the storage area according to the message identification mark of the target message included in the actual processing result.
On the basis of the foregoing embodiments, the expected information adding module 430 may specifically be configured to:
and calling an information access interface to access the memory area by referring to each environment module in the model so as to add expected module information matched with the module of the memory area into the expected information of the memory area.
The system-level test device of the chip provided by the embodiment of the invention can execute the system-level test method of the chip provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
EXAMPLE five
Fig. 5 is a schematic structural diagram of a computer apparatus according to a fifth embodiment of the present invention, as shown in fig. 5, the computer apparatus includes a processor 50, a memory 51, an input device 52, and an output device 53; the number of processors 50 in the computer device may be one or more, and one processor 50 is taken as an example in fig. 5; the processor 50, the memory 51, the input device 52 and the output device 53 in the computer apparatus may be connected by a bus or other means, and the connection by the bus is exemplified in fig. 5.
The memory 51 is used as a computer-readable storage medium for storing software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the system-level testing method of the chip in the embodiment of the present invention (for example, the initialization construction module 410, the transmission data input module 420, the expected information adding module 430, and the system-level testing module 440 in the system-level testing apparatus of the chip). The processor 50 executes various functional applications and data processing of the computer device by executing software programs, instructions and modules stored in the memory 51, namely, the method for system level testing of the chip described above is realized, and the method comprises the following steps:
constructing transmission data and expected information corresponding to the target message, and storing the expected information in a preset storage area, wherein the expected information comprises an expected result message;
inputting transmission data into a reference model matched with a chip to be detected, wherein each environment module in the reference model corresponds to each entity module in the chip to be detected, and initialized transmission data comprise a target message and interface data matched with a first environment module in the reference model;
updating interface data in transmission data currently transferred to the self module by referring to each environment module in the model, and adding expected module information matched with the self module into expected information in the storage area;
and performing system level test on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message and the expected information currently stored in the storage area.
The memory 51 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 51 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the memory 51 may further include memory located remotely from the processor 50, which may be connected to a computer device over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 52 is operable to receive input numeric or character information and to generate key signal inputs relating to user settings and function controls of the computer apparatus. The output device 53 may include a display device such as a display screen.
Constructing transmission data and expected information corresponding to the target message, and storing the expected information in a preset storage area, wherein the expected information comprises an expected result message;
inputting transmission data into a reference model matched with a chip to be detected, wherein each environment module in the reference model corresponds to each entity module in the chip to be detected, and initialized transmission data comprise a target message and interface data matched with a first environment module in the reference model;
updating interface data in transmission data currently transferred to the self module by referring to each environment module in the model, and adding expected module information matched with the self module into expected information in the storage area;
and performing system level test on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message and the expected information currently stored in the storage area.
EXAMPLE six
An embodiment of the present invention further provides a storage medium containing computer-executable instructions, which when executed by a computer processor, perform a system level test method for a chip, the method including:
of course, the storage medium provided by the embodiments of the present invention contains computer-executable instructions, and the computer-executable instructions are not limited to the method operations described above, and may also perform related operations in the system level test method for a chip provided by any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention.
It should be noted that, in the embodiment of the above search apparatus, each included unit and module are merely divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A system level test method of a chip is characterized by comprising the following steps:
constructing transmission data and expected information corresponding to the target message, and storing the expected information in a preset storage area, wherein the expected information comprises an expected result message;
inputting transmission data into a reference model matched with a chip to be detected, wherein each environment module in the reference model corresponds to each entity module in the chip to be detected, and initialized transmission data comprise a target message and interface data matched with a first environment module in the reference model;
updating interface data in transmission data currently transferred to the self module by referring to each environment module in the model, and adding expected module information matched with the self module into expected information in the storage area;
and performing system level test on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message and the expected information currently stored in the storage area.
2. The method according to claim 1, wherein performing a system level test on the chip under test according to an actual processing result of the chip under test for the target packet output and expected information currently stored in the storage area comprises:
according to the actual processing result and an expected result message in the expected information, verifying the processing correctness of the message;
and carrying out self-consistency verification on each environment module according to expected module information which corresponds to each environment module in the expected information.
3. The method of claim 1, wherein constructing expected information corresponding to the target message comprises:
constructing initialized expected information;
and generating an expected result message corresponding to the target message according to the message attribute information of the target message and the design index of the chip to be tested, and writing the expected result message into the expected information.
4. The method of claim 1, further comprising, after updating the interface data in the transmission data currently flowing to the self module by referring to each environment module in the model, the following steps:
and by referring to each environment module in the model, if the module operation executed by the module is determined to be message modification operation, performing matched message modification on the target message in the transmission data.
5. The method according to claim 4, wherein performing a system level test on the chip under test according to an actual processing result of the chip under test for the target packet output and the expected information currently stored in the storage area comprises:
according to an actual processing result output by the chip to be tested aiming at the target message, the target message in the transmission data finally output by the reference model and an expected result message included by the expected information, verifying the processing correctness of the message;
and carrying out self-consistency verification on each environment module according to expected module information which corresponds to each environment module in the expected information.
6. The method of claim 1, further comprising, prior to constructing the transmission data and the expected information corresponding to the target message:
adding a message identification mark matched with the target message into the target message;
after constructing the transmission data and the expected information corresponding to the target message, the method further comprises the following steps:
adding the message identification mark into the transmission data and the expected information;
updating interface data in transmission data currently transferred to the self module by referring to each environment module in the model, and adding expected module information matched with the self module into the expected information in the storage area, wherein the expected module information comprises the following steps:
by referring to each environment module in the model, when transmission data which is currently transferred to the self module is received, according to a message identification mark included in the transmission data, expected information matched with the message identification mark is positioned in the storage area;
adding expected module information matched with the module per se into the located expected information according to interface data in the transmission data by referring to each environment module in the model, and updating the interface data in the transmission data;
before performing system level test on the chip to be tested according to an actual processing result output by the chip to be tested for the target message and expected information currently stored in the storage area, the method further comprises the following steps:
and positioning expected information corresponding to the message identification mark in the storage area according to the message identification mark of the target message included in the actual processing result.
7. The method of claim 1, wherein adding expected module information matching with the self module to the expected information in the storage area by referring to each environment module in the model comprises:
and calling an information access interface to access the memory area by referring to each environment module in the model so as to add expected module information matched with the module of the memory area into the expected information of the memory area.
8. A system level test apparatus for a chip, comprising:
the initialization construction module is used for constructing transmission data and expected information corresponding to the target message and storing the expected information in a preset storage area, wherein the expected information comprises an expected result message;
the transmission data input module is used for inputting transmission data into a reference model matched with the chip to be detected, each environment module in the reference model corresponds to each entity module in the chip to be detected, and initialized transmission data comprise a target message and interface data matched with a first environment module in the reference model;
the expected information adding module is used for updating interface data in transmission data currently transferred to the self module by referring to each environment module in the model, and adding expected module information matched with the self module into the expected information in the storage area;
and the system level test module is used for carrying out system level test on the chip to be tested according to the actual processing result output by the chip to be tested aiming at the target message and the expected information currently stored in the storage area.
9. A computer device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the system level testing method of the chip of any of claims 1-7.
10. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the system level testing method of the chip of any one of claims 1-7.
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