CN113223975A - 在半导体裸片的背侧金属化部上使用牺牲层的烧结方法 - Google Patents

在半导体裸片的背侧金属化部上使用牺牲层的烧结方法 Download PDF

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CN113223975A
CN113223975A CN202110163467.8A CN202110163467A CN113223975A CN 113223975 A CN113223975 A CN 113223975A CN 202110163467 A CN202110163467 A CN 202110163467A CN 113223975 A CN113223975 A CN 113223975A
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layer
sacrificial layer
electronic device
temperature
sacrificial
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F·奥托
P·弗兰克
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

一种电子装置(10)包括：半导体裸片(1)；层堆叠体(2.1)，其设置在半导体裸片(1)上并且包括一个或多个功能层，其中，层堆叠体(2.1)包括保护层(2.11)，所述保护层(2.11)是层堆叠体(2.1)的最外功能层；和牺牲层(2.2)，其设置在保护层(2.11)上，其中，牺牲层(2.2)包括在100℃至400℃之间的温度下分解或变得挥发的材料。

Description

在半导体裸片的背侧金属化部上使用牺牲层的烧结方法
技术领域
本公开涉及一种电子装置、一种用于制作电子装置的方法以及一种用于制作电子模块的方法。
背景技术
为了制作电子装置，经常必须将半导体裸片、半导体衬底或半导体晶片安装到诸如引线框架的载体上。当今在半导体工业中采用的两种最主要的方法是焊接和烧结。本公开总体上涉及烧结方法。就产品的热性能和机械性能而言，众所周知，烧结比传统的焊接工艺具有明显的优势。
文献EP 3 217 424 A1描述了通过烧结连接将半导体裸片固定在载体上，其中，该半导体裸片具有由Ti/Ni/Au层堆叠体制成的后电极，所述层堆叠体具有由金制成的最上方的保护层。将镍颗粒和有机分散体(如脂肪酸)构成的粘合层施加到此最上方的保护层，有机分散体在200℃C至400℃的烧结温度下挥发。
文献US 2010/0 055 839 A1也描述了半导体部件与载体的电连接，并且特别地示出了具有由一层或多层制成的后电极的半导体裸片，所述后电极上沉积有包含金属颗粒的膏，所述金属颗粒涂有一层有机材料或一种助熔剂(例如树脂)，并溶于在烧结温度下蒸发的蜡状液体中。
文献US 2019/0 264 072 A1描述了半导体和衬底之间利用连接膜的烧结连接，该连接膜沉积在箔上，并且该连接膜中的导电膜在溶液中包含金属细颗粒，该连接膜中的粘合膜由诸如脂肪酸的材料构成，所述脂肪酸在加热到烧结温度会溶解。
发明内容
然而，最近发现，烧结对所使用的半导体裸片，特别是对半导体裸片的背侧金属化部堆叠体产生了额外的、以前未知的要求。特别地，代表许多常规裸片背侧金属化部堆叠体上的终止保护层的Ag薄膜在升高的温下暴露于氧气时会遭受明显的微结构退化，进而会促进层离或腐蚀问题。
因此，需要本公开。
本公开的第一方面涉及一种电子装置，包括：半导体裸片；层堆叠体，其设置在半导体裸片上并且包括一个或多个功能层，其中，层堆叠体包括保护层，所述保护层是层堆叠体的最外功能层；和牺牲层，其设置在保护层上，其中，牺牲层包括在100℃至400℃之间的温度下分解或变得挥发的材料。
本公开的第二方面涉及一种用于制作电子装置的方法，所述方法包括：提供半导体裸片；在半导体裸片上设置层堆叠体，所述层堆叠体包括一个或多个功能层，其中，所述层堆叠体包括保护层，所述保护层是层堆叠体的最外功能层；和在保护层上设置牺牲层，其中，牺牲层包括在100℃至400℃之间的温度下分解或变得挥发的材料。
本公开的第三方面涉及一种用于制作电子模块的方法，所述方法包括：提供载体；提供电子装置，所述电子装置包括半导体裸片、设置在半导体裸片上并且包括一个或多个功能层的层堆叠体以及牺牲层，其中，所述层堆叠体包括作为层堆叠体的最外功能层的保护层，所述牺牲层设置在保护层上，其中，牺牲层包括在100℃至400℃之间的温度下分解或变得挥发的材料；将烧结膏施加到载体的主表面上；和在100℃至400℃之间的温度下将电子装置烧结到载体上，使得牺牲层完全分解或变得挥发。
附图说明
所包括的附图用以提供对实施例的进一步理解，并且附图被并入本说明书中并构成本说明书的一部分。附图示出了多个实施例，并且与说明书一起用于解释实施例的原理。其它实施例和实施例的许多预期优点将易于理解，因为通过参考以下详细描述，它们将变得更好理解。
附图的元件不一定相对于彼此成比例。相同的附图标记表示对应的相似或相同部件。
图1示出了根据第一方面的电子装置的示意性侧剖视图。
图2示出了根据第二方面的用于制作电子装置的方法的流程图。
图3示出了根据第三方面的用于制作电子模块的方法的流程图。
图4示出了中间产品的示意性侧剖视图，用于图示根据第三方面的用于制作电子模块的方法。
图5包括A部分和B部分，并且示出了温度随时间的曲线图(A)以及牺牲层剩余量随时间的曲线图(B)，用于图示在非连续温度下氧化或蒸发的牺牲层材料的假设处理序列。
图6包括A部分和B部分，并且示出了温度随时间的曲线图(A)以及牺牲层剩余量随时间的曲线图(B)，用于图示在扩展的温度范围上氧化或蒸发的牺牲层材料的假设处理序列。
具体实施方式
在下面的详细描述中，参考构成说明书的一部分的附图，在附图中通过图示的方式示出了可以实践本公开的特定实施例。在这方面，参考正描述的附图的方向使用诸如“顶”、“底”、“正”、“背”、“前导”、“尾后”等方向性术语。因为实施例的构件可以以许多不同的方向定位，所以方向性术语用于说明的目的，而绝不是限制性的。应当理解，在不脱离本公开的范围的情况下，可以利用其它实施例且可以进行结构或逻辑上的改变。因此，以下详细描述不应被理解为限制性的，本公开的范围由所附权利要求限定。
应当理解，除非另外特别指出，否则本文所述的各种示例性实施例的特征可以彼此组合。
如在本说明书中所采用的，术语“接合”、“附接”、“连接”、“耦接”和/或“电连接/电耦接”并不意味着元件或层必须直接接触在一起；可以在“接合”、“附接”、“连接”、“耦接”和/或“电连接/电耦接”的元件之间相应地设置居间元件或层。然而，根据本公开，上述术语还可以可选地具有特定含义，即元件或层直接接触在一起，即在“接合”、“附接”、“连接”、“耦接”和/或“电连接/电耦接”的元件之间相应地不设置居间元件或层。
此外，关于部件、元件或材料层形成在或位于一表面“之上”中所使用的词语“在…之上”在本文中可以用来表示该部件、元件或材料层“间接地”位于(例如放置在、形成在、沉积在等)所述表面上而有一个或多个附加部件、元件或层布置在所述表面与该部件、元件或材料层之间。然而，关于部件、元件或材料层形成在或位于一表面“之上”中所使用的词语“在…之上”还可以可选地具有该部件、元件或材料层直接地位于(例如放置在、形成在、沉积在等)所述表面上、例如与所述表面直接接触的特定含义。
详细说明
图1描绘了根据第一方面的电子装置。
电子装置10包括：半导体裸片1；设置在半导体裸片1上并包括一个或多个功能层的层堆叠体2.1，其中，层堆叠体2.1包括是层堆叠体2.1的最外功能层的保护层2.11；和设置在保护层2.11上的牺牲层2.2，其中，牺牲层2.2包括在100℃至400℃之间的温度下分解或变得挥发的材料。
图2示出了用于图示根据第二方面的方法的流程图。
图2的方法20包括：提供半导体裸片(21)；在半导体裸片上设置层堆叠体，所述层堆叠体包括一个或多个功能层，其中，所述层堆叠体包括是层堆叠体的最外功能层的保护层(22)；以及在保护层上设置牺牲层，其中，所述牺牲层包括在100℃至400℃之间的温度下分解或变得挥发的材料(23)；其中，范围的下限也可以是150℃、200℃或250℃，上限也可以是350℃、300℃或250℃。
特别地，图2的方法20可以被配置成用于制造如图1所描绘的电子装置，所述电子装置将在下面更详细地说明。
本公开的一个特征是牺牲层，其被添加在背侧金属化部堆叠体的顶部上，特别是沉积到可以是例如Ag层的终止层上。可以认为通过防止氧气进入背侧金属化部堆叠体来保护晶片的一个或多个半导体裸片。
可以将不同种类的材料用于牺牲层。潜在合适的层材料应满足以下特征1)到5)中的一项或多项：
1)所使用的材料在典型的环境条件下为固体，半导体裸片或包含半导体裸片的晶片在生产后在所述典型的环境条件下被存储或运输。
2)用于牺牲层的材料能够防止氧气能够吸附到终止层、例如银的背侧层。这可以通过阻断背侧终止层、例如银层上对氧有吸引力的吸附位点来实现。
3)牺牲层的材料在加热时会挥发，这里可以设想两种不同的机制：
a)材料与氧气反应，然后反应产物为挥发性化合物。
b)材料本身在升高的温度下变成气态，即蒸发。
4)独立于牺牲层变得挥发的确切性质(即3a或3b)，优选的是蒸发和/或反应在相当明确的温度下发生。这样，可以可靠地控制在功率模块生产期间从裸片背侧去除材料的阶段。
5)如果牺牲层的材料与氧气反应，则其反应产物对半导体组件无害。
根据电子装置或方法的一个实施例，牺牲层的材料包括碳。在氧气中高温处理下，碳将与周围的氧气反应生成二氧化碳，二氧化碳具有化学惰性并易于蒸发。替代地，例如金属或非金属的无机材料原则上也是可能的候选者，只要它们不与半导体装置相互作用并且变得挥发(以纯挥发的形式或氧化形式)即可。根据其另一示例，碳、金属或非金属牺牲层的厚度在0.1至200nm的范围内，其中，下限也可以是相应材料的单分子层(monolayer)的厚度0.5nm、1nm、2nm、5nm、10nm、20nm、30nm、40nm或50nm，上限也可以是180nm、160nm、140nm、120nm、100nm、80nm或60nm。
根据电子装置或方法的另一个实施例，牺牲层的材料包括有机分子、特别是复杂的有机分子，其可以被施加到层堆叠体上。例如，这可以通过热蒸发来完成。可以设想两种可能在此适用的类别：
1)被物理吸附到层堆叠体的终止层、例如Ag层的有机物。
2)被化学吸附到层堆叠体的终止层、例如Ag层的有机物。
从终止层去除物理/化学吸附物所需的能量或温度(在我们的情况下)与分子的化学性质有关。因此，可以根据用户的特定需求定制牺牲层的材料。例如，可以通过使用固有吸附强度不同的不同物质的混合物或纯物质进行调节。如果所使用的有机物非常好地粘附在终止层上(化学吸附)，则有机物的氧化可能先导于或伴随着解吸。在此，用于引发氧化反应的临界温度将指示牺牲层将被去除的温度阈值。
在下文中，给出了多个可能特别适合用作牺牲层的有机物质的示例。当然，满足上述标准的所有其它物质也是可能的。
1)脂肪酸。在合适的条件下，它们倾向于化学吸附到Ag表面。它们的解吸温度与临界温度和氧化分解的不饱和度一样与分子的碳链长度有关。这样，可以容易地微调牺牲层的挥发/分解。此外，脂肪酸容易获得且便宜。
2)中链至长链烃，例如烷烃。解吸/蒸发动力学特性与它们各自的碳链长度有关，因此使用户能够微调挥发动力学特性。
3)环氧乙烷(PEO)蜡或聚环氧丙烷(PPO)蜡，其氧化特性与项1和项2中的烃相似。它们的流变和亲水性可通过部分氧化和分子量分布来调节，这对于将它们应用于我们的晶片背侧是很有意义的。
4)项3的物质，带有一个附加的酰胺官能团。可以将这类蜡从非常软的材料调整为与PEO和PPO蜡的热和流变性质不同的硬质材料。
根据上述采用有机分子作为牺牲层的实施例的另一示例，这种牺牲层的厚度在0.1nm至10nm的范围内，其中，下限也可以是相应材料的单分子层的厚度0.2nm、0.3nm、0.4nm或0.5nm、1nm或2nm，上限也可以是9nm、8nm、7nm、6nm或5nm。
关于牺牲层的沉积，原则上允许将具有良好控制的厚度的均匀薄膜沉积到层堆叠体背侧上的任何方法都适合于在此描述的牺牲层的制作。然而，以下列出了一些示例性方法：物理气相沉积技术(PVD)通常用于薄膜沉积的前端中。使用PVD沉积牺牲层也将利用现有的设备和专业知识(-->通用性)，并且被认为在经济上是高效的。对于化学气相沉积技术，同样如此。根据要沉积的物质，简单的热蒸发工艺可能是制造牺牲层的最简单、最经济的方法。
另一选项似乎特别有吸引力，尽管这是在不引入附加工艺的情况下添加牺牲层的唯一方法。这里简要介绍一下：在分切之前，通常将我们的晶片的背侧粘合到本身固定在框架中的胶带材料上。分切后，使用紫外线对上述胶水进行处理，以建立一定的粘性，一方面确保对分切的晶片的安全操纵，另一方面允许在后端处理期间实现从胶带材料上完全自动拾取裸片。从胶带上拾取某些晶片时，一些胶水材料不可避免地会残留在裸片背侧。如果显示出可以确保从晶片胶带到裸片背侧的充分且可再现的材料转移，则这些(有机)残留物在本发明的意义上也可以用作牺牲层。
根据电子装置或方法的一个实施例，作为层堆叠体的终止层的保护层包括Ag层。
根据电子装置或方法的一个实施例，层堆叠体包括四层。根据其另一实施例，层堆叠体包括在半导体裸片、特别是硅裸片之后的以下层序列：Al层、Ti层、包括Ni的层和Ag层。包括Ni的层可以是例如NiV层或NiSi层。
图3示出了用于制作电子模块的方法的流程图。
图3的方法30包括：提供载体；提供包括半导体裸片、设置在半导体裸片上并包括一个或多个功能层的层堆叠体以及牺牲层的电子装置，其中，所述层堆叠体包括保护层，保护层是层堆叠体的最外功能层，牺牲层设置在保护层上，其中，牺牲层包括在100℃至400℃的温度下分解或变得挥发的材料(32)；将烧结膏施加到载体的主表面(33)；在100℃至400℃之间的温度下将电子装置烧结到载体上，使得牺牲层完全分解或变得挥发(34)。
在电子模块在含氧环境中制作期间，牺牲层通过防止氧能够吸附到终止层来保护裸片背侧金属化部堆叠体。只要存在牺牲层，所述保护作用就持续。然而，在进一步制作模块的过程中，必须去除牺牲物以便能够在裸片和烧结层之间形成良好的材料接合的互连。
根据图3的方法30的一个实施例，载体包括引线框架的一部分、直接铜接合(DCB)结构、活性金属铜焊(AMB)结构和隔离金属衬底(IMS)中的一个或多个。
根据图3的方法30的一个实施例，烧结在150℃至350℃的范围内的温度下进行，其中，下限也可以是200℃，上限也可以是300℃。
图4示出了中间产品的示意性侧剖视图，用于图示用于制作电子模块的方法。
特别地，图4描绘了将要连接到载体50的电子装置40。电子装置40包括：半导体裸片41；设置在半导体裸片41上并包括一个或多个功能层的层堆叠体42.1，其中，层堆叠体42.1包括作为层堆叠体42.1的最外功能层的保护层42.11；和设置在保护层42.11上的牺牲层42.2，其中，牺牲层42.2包括在100℃至400℃的温度下分解或变得挥发的材料。
电子装置40可以包括以下层序列：硅裸片41、Al层、Ti层、NiV或NiSi层、Ag层42.11、牺牲层42.2。
图4进一步示出了设置在电子装置40和载体50之间的烧结膏层43。载体50是包括第一上部Cu层51、第二下部Cu层53和中间介电层52的活性金属铜焊(AMB)衬底。Ag镀层54设置在第一上部Cu层51的顶部上。
图4示意性地图示了O2分子通过烧结膏层43扩散直到它们到达牺牲层42.2，在这里它们与牺牲层42.2的材料的成分发生反应。
烧结膏层43可以包括银薄片的细粉，并且整个组件可以在温度和压力的联合作用下被压实。压实的过程通常可以在砧冲装置中执行，其中，组件被放置在可引入机械压力和温度的加热的冲头和加热的砧之间。温度可在200℃至300℃的范围内，此时压力可在5MPa至30MPa的范围内，并且处理时间可以在1min至60min的范围内。为了清楚起见，此处未示出砧冲装置。
根据牺牲层的材料的选择，可以利用不同的去除操作。这些在下面被示意性地解释。需要强调的是，这些示例代表了简化的案例；实际上，应想到混合的操作。
图5包括A部分和B部分并且图示了非连续的去除动力学特性。特别地，图5示出了温度随时间的图(A)和牺牲层剩余量随时间的图(B)，用于图示在非连续温度下氧化或蒸发的牺牲层材料的假设处理序列。
设想牺牲层具有明确限定的温度，在该温度下它可以蒸发或与周围的氧气发生反应(然后蒸发)。现在设想所述层在含氧氛围中经受一系列温度步骤(例如不同的封装过程)。在这些条件下，牺牲层在高于非连续氧化/蒸发温度的温度下进行处理之前实际上保持不变。一旦达到这个临界温度，牺牲层将被去除。在图5的A部分中画出了这种假设的温度步骤序列，其中，牺牲层材料的非连续氧化/蒸发温度由黑色虚线突出显示。另外，图5的B部分还包含相应的质量损失曲线，其以牺牲层质量随时间变化的形式图示了牺牲层的去除动力学特性。如上所述，在前三个温度步骤中没有观察到质量损失，这是因为在太低的温度下进行而不会引起牺牲层的氧化/蒸发。然而，一旦超过临界温度，即在第四温度步骤期间，材料去除就很快。对于其中非连续氧化/蒸发温度代表两个稳定的热力学状态之间的阈值的过程，这种特性是可预期的。一个示例是水的沸腾，在给定压力下，水的沸腾发生在明确确定的温度下，在该温度以上，水以气态形式稳定，在该温度以下，水以液态形式稳定。当然，相变动力学特性仍会具有一定的温度依赖性(即过热度)；但对于具有高的蒸气压或反应性很强的材料，这可以忽略不计。
就上一节中概述的材料氧化/蒸发方案而言，可以预期的是，薄的碳层将表现出“非连续”类型的特性。
图6包括A部分和B部分并且图示了连续的去除动力学特性。特别地，图6示出了温度随时间的图(A)和牺牲层剩余量随时间的图(B)，用于图示在扩展的温度范围内氧化或蒸发的牺牲层材料的假设处理序列。
设想与先前示例相同的温度步骤序列。然而，这一次，存在发生氧化/蒸发的扩展温度范围。例如，如果氧化/蒸发在能量上可行的临界温度相对较低，而氧化/蒸发的速率强烈地随温度被激活，则是这种情况。在这种情况下，低温下已经会发生缓慢的氧化/蒸发，但是当温度升高时，氧化/蒸发会加速。在这种情况下，材料去除将以多个与温度相关的增量形式在多个温度步骤上展开。在图6的A部分中描绘了这种情况，其中示出了与图5的A部分相同的温度曲线。突出显示温度范围，其中，牺牲层的去除速率用灰度色调编码表示；灰色调越深，去除速率越高。图6的B部分中相应的质量损失曲线说明在这种情况下质量损失将分多个步骤发生。每个温度步骤的质量损失增量与绝对温度有关。对于给定的时间增量，与低温过程相比，高温过程会产生更高的因氧化/蒸发引起的质量损失。
对于上述氧化/蒸发特性中的哪个是优选的问题的答案可能随所考虑的特定处理序列而变化。只要存在足够的牺牲材料，就可以保护裸片背侧金属化部堆叠体中的终止Ag层免受氧气的侵入。
示例1是一种电子装置，包括：半导体裸片；层堆叠体，其设置在半导体裸片上并且包括一个或多个功能层，其中，层堆叠体包括保护层，所述保护层是层堆叠体的最外功能层；和牺牲层，其设置在保护层上，其中，牺牲层包括在100℃至400℃之间的温度下分解或变得挥发的材料。
在示例2中，在示例1的主题中，牺牲层的材料可选地包括碳。
在示例3中，在示例1的主题中，牺牲层的材料可选地包括金属。
在示例4中，在示例2或3的主题中，牺牲层的厚度在0.1nm或单分子层厚度至200nm的范围内。
在实施例5中，在前述实施例中任一项的主题中，牺牲层的材料包括一种或多种有机分子和/或脂肪酸。
在示例6中，在示例5的主题中，牺牲层的厚度在0.1至10nm的范围内。
在示例7中，在前述示例中任一项的主题中，保护层包括Ag。
在示例8中，在前述示例中任一项的主题中，层堆叠体包括四层。
在示例9中，在示例8的主题中，层堆叠体包括在半导体裸片之后的以下层序列：Al层、Ti层、包括Ni的层和Ag层。
示例10是一种方法，所述方法包括：提供半导体裸片；在半导体裸片上设置层堆叠体，所述层堆叠体包括一个或多个功能层，其中，所述层堆叠体包括保护层，所述保护层是层堆叠体的最外功能层；和在保护层上设置牺牲层，其中，牺牲层包括在100℃至400℃之间的温度下分解或变得挥发的材料。
在示例11中，在示例10的主题中，牺牲层的材料可选地包括碳。
在示例12中，在示例10的主题中，牺牲层的材料可选地包括金属。
在示例13中，在示例11或12的主题中，牺牲层的厚度在0.1nm或单分子层厚度至200nm的范围内。
在示例14中，在示例10的主题中，牺牲层的材料包括一种或多种有机分子和/或脂肪酸。
在示例15中，在示例14的主题中，牺牲层的厚度在0.1到10nm的范围内。
在示例16中，在前述示例中任一项的主题中，牺牲层通过箔辅助施加来设置。
示例17是一种用于制作电子模块的方法，所述方法包括：提供载体；提供电子装置，所述电子装置包括半导体裸片、设置在半导体裸片上并且包括一个或多个功能层的层堆叠体以及牺牲层，其中，所述层堆叠体包括作为层堆叠体的最外功能层的保护层，所述牺牲层设置在保护层上，其中，牺牲层包括在100℃至400℃之间的温度下自身分解或变得挥发的材料或者在与氧气或含氧化合物反应时或反应后在100℃至400℃之间的温度下分解或变得挥发的材料；将烧结膏施加到载体的主表面上；和在100℃至400℃之间的温度下将电子装置烧结到载体上，使得牺牲层本身完全分解或变得挥发，或者使得牺牲层在与氧气或含氧化合物反应时或反应后在100℃至400℃之间的温度下分解或变得挥发。
在示例18中，在示例17的主题中，载体包括引线框架的一部分、直接铜接合(DCB)结构、活性金属铜焊(AMB)结构和隔离金属衬底(IMS)的中的一个或多个。
在示例19中，在示例17或18的主题中，烧结在150℃至350℃范围内的温度下进行。
在示例20中，在示例19的主题中，烧结在200℃至300℃范围内的温度下进行。
另外，尽管可能已经针对几个实施方式中的仅一个实施方式公开了本公开的一个实施例的特定特征或方面，但是这种特征或方面可以与其它实施方式的一个或多个其它特征或方面组合，这对于任何给定的或特定的应用，可能是期望的和有利的。此外，对于在详细说明或权利要求书中使用的术语“包含”、“具有”、“带有”或其其它变体而言，这些术语旨在以类似于术语“包括”的方式是开放式包括。此外，应当理解，本公开的实施例可以以分立电路、部分集成电路或完全集成电路或编程装置实现。而且，术语“示例性”仅意味着示例，而不是最佳或最优的。还应当理解，为了简单和易于理解的目的，相对彼此以特定尺寸示出了本文所描绘的特征和/或元件，但实际尺寸可能与本文所示出的明显不同。
尽管本文已经图示和描述了特定实施例，但是本领域普通技术人员将理解，在不脱离本公开的范围的情况下，各种替代和/或等效实施方式可以替代所示出和描述的特定实施例。本申请旨在覆盖本文讨论的特定实施例的任何改型或变型。因此，本公开仅由权利要求及其等同替换限制。

Claims (20)

1.一种电子装置(10)，包括：
半导体裸片(1)；
层堆叠体(2.1)，其设置在半导体裸片(1)上并且包括一个或多个功能层，其中，层堆叠体(2.1)包括保护层(2.11)，所述保护层(2.11)是层堆叠体(2.1)的最外功能层；和
牺牲层(2.2)，其设置在保护层(2.11)上，其中，所述牺牲层(2.2)包括在100℃至400℃之间的温度下分解或变得挥发、从而被完全去除的材料。
2.根据权利要求1所述的电子装置(10)，其中
牺牲层(2.2)的材料包括碳。
3.根据权利要求1所述的电子装置(10)，其中
牺牲层(2.2)的材料包括金属。
4.根据权利要求2或3所述的电子装置，其中
牺牲层(2.2)的厚度在0.1nm或单分子层厚度至200nm的范围内。
5.根据前述权利要求中任一项所述的电子装置(10)，其中
牺牲层(2.2)的材料包括一种或多种有机分子和/或脂肪酸。
6.根据权利要求5所述的电子装置(10)，其中
牺牲层(2.2)的厚度在0.1至10nm的范围内。
7.根据前述权利要求中任一项所述的电子装置(10)，其中
保护层(2.11)包括Ag。
8.根据前述权利要求中任一项所述的电子装置(10)，其中
层堆叠体(2.1)包括四层。
9.根据权利要求8所述的电子装置(10)，其中
层堆叠体(2.1)包括在半导体裸片(1)之后的以下层序列：Al层、Ti层、包括Ni的层和Ag层。
10.一种用于制作电子装置的方法(20)，所述方法包括：
提供半导体裸片(21)；
在半导体裸片上设置层堆叠体，所述层堆叠体包括一个或多个功能层，其中，所述层堆叠体包括保护层，所述保护层是层堆叠体的最外功能层(22)；和
在保护层上设置牺牲层，其中，牺牲层包括在100℃至400℃之间的温度下分解或变得挥发、从而被完全去除的材料(23)。
11.根据权利要求10所述的方法，其中
牺牲层的材料包括碳。
12.根据权利要求10所述的方法，其中
牺牲层的材料包括金属。
13.根据权利要求11或12所述的方法，其中
牺牲层的厚度在0.1nm或单分子层厚度至200nm的范围内。
14.根据权利要求10所述的方法，其中
牺牲层的材料包括一种或多种有机分子和/或脂肪酸。
15.根据权利要求14所述的方法，其中
牺牲层的厚度在0.1至10nm的范围内。
16.根据前述权利要求中任一项所述的方法，其中
牺牲层通过箔辅助施加来设置。
17.一种用于制作电子模块的方法(30)，所述方法包括：
提供载体(31)；
提供电子装置，所述电子装置包括：半导体裸片；设置在半导体裸片上并且包括一个或多个功能层的层堆叠体，其中，所述层堆叠体包括作为层堆叠体的最外功能层的保护层；和设置在保护层上的牺牲层，其中，牺牲层包括在100℃至400℃之间的温度下自身分解或变得挥发的材料或者在与氧气或含氧化合物反应时或反应后在100℃至400℃之间的温度下分解或变得挥发的材料(32)；
将烧结膏施加到载体的主表面上(33)；和
在100℃至400℃之间的温度下将电子装置烧结到载体上，使得牺牲层本身完全分解或变得挥发且在任何情况下均被完全去除，或者使得牺牲层在与氧气或含氧化合物反应时或反应后在100℃至400℃之间的温度下分解或变得挥发且在任何情况下均被完全去除(34)。
18.根据权利要求17所述的方法，其中
载体包括引线框架的一部分、直接铜接合(DCB)结构、活性金属铜焊(AMB)结构和隔离金属衬底(IMS)中的一个或多个。
19.根据权利要求17或18所述的方法，其中
烧结在150℃至350℃范围内的温度下进行。
20.根据权利要求19所述的方法，其中，
烧结在200℃至300℃范围内的温度下进行。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4057340A1 (en) * 2021-03-08 2022-09-14 Infineon Technologies Austria AG Semiconductor device with a layer stack comprising a nisi layer and a niv layer for mounting on an electrically conductive layer, method for producing the same and corresponding mounted semiconductor arrangement
CN114107889A (zh) * 2021-11-11 2022-03-01 杭州四马化工科技有限公司 一种金属箔脱模方法
CN114086120A (zh) * 2021-11-11 2022-02-25 杭州四马化工科技有限公司 一种超薄金属箔的制备方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004072133A1 (en) * 2003-02-05 2004-08-26 Dow Global Technologies Inc. Sacrificial styrene benzocyclobutene copolymers for making air gap semiconductor devices
US20080166525A1 (en) * 2006-12-21 2008-07-10 Interuniversitair Microelektronica Centrum (Imec) Method for bonding a die or substrate to a carrier
US20120153527A1 (en) * 2010-12-21 2012-06-21 Toyota Motor Engineering & Manufacturing North America, Inc. Process for manufacturing a stand-alone thin film
US20130140685A1 (en) * 2011-12-01 2013-06-06 Infineon Technologies Ag Electronic Device and a Method for Fabricating an Electronic Device
CN103515311A (zh) * 2012-06-27 2014-01-15 英飞凌科技股份有限公司 芯片封装和制造芯片封装的方法
CN104022016A (zh) * 2010-08-06 2014-09-03 布鲁尔科技公司 薄晶片处理的多粘合层
CN106298650A (zh) * 2015-06-29 2017-01-04 意法半导体公司 使用牺牲材料而分离的半导体封装体
CN108109901A (zh) * 2016-11-25 2018-06-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制作方法
CN109075129A (zh) * 2016-05-10 2018-12-21 德州仪器公司 浮动裸片封装

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI316749B (en) 2006-11-17 2009-11-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
US7754533B2 (en) 2008-08-28 2010-07-13 Infineon Technologies Ag Method of manufacturing a semiconductor device
DE102008055134A1 (de) 2008-12-23 2010-07-01 Robert Bosch Gmbh Elektrisches oder elektronisches Verbundbauteil sowie Verfahren zum Herstellen eines elektrischen oder elektronischen Verbundbauteils
US9184319B2 (en) 2011-01-14 2015-11-10 The Board Of Trustees Of The Leland Stanford Junior University Multi-terminal multi-junction photovoltaic cells
US9105714B2 (en) * 2012-12-11 2015-08-11 LuxVue Technology Corporation Stabilization structure including sacrificial release layer and staging bollards
US9006899B2 (en) 2012-12-14 2015-04-14 Infineon Technologies Ag Layer stack
US9583466B2 (en) * 2013-12-27 2017-02-28 Apple Inc. Etch removal of current distribution layer for LED current confinement
US20170317048A1 (en) 2014-11-07 2017-11-02 Nippon Steel & Sumitomo Metal Corporation Conductive bonded assembly of electronic component, semiconductor device using same, and method of production of conductive bonded assembly
TWI693719B (zh) 2015-05-11 2020-05-11 日商半導體能源研究所股份有限公司 半導體裝置的製造方法
JP6440905B2 (ja) 2016-11-18 2018-12-19 古河電気工業株式会社 接合フィルム、ウエハ加工用テープ、接合体の製造方法および接合体
US20180286734A1 (en) * 2017-03-28 2018-10-04 X-Celeprint Limited Micro-device pockets for transfer printing
US9928947B1 (en) 2017-07-19 2018-03-27 National Cheng Kung University Method of fabricating highly conductive low-ohmic chip resistor having electrodes of base metal or base-metal alloy
US10679901B2 (en) * 2018-08-14 2020-06-09 International Business Machines Corporation Differing device characteristics on a single wafer by selective etch
US10790173B2 (en) * 2018-12-03 2020-09-29 X Display Company Technology Limited Printed components on substrate posts

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004072133A1 (en) * 2003-02-05 2004-08-26 Dow Global Technologies Inc. Sacrificial styrene benzocyclobutene copolymers for making air gap semiconductor devices
US20080166525A1 (en) * 2006-12-21 2008-07-10 Interuniversitair Microelektronica Centrum (Imec) Method for bonding a die or substrate to a carrier
CN104022016A (zh) * 2010-08-06 2014-09-03 布鲁尔科技公司 薄晶片处理的多粘合层
US20120153527A1 (en) * 2010-12-21 2012-06-21 Toyota Motor Engineering & Manufacturing North America, Inc. Process for manufacturing a stand-alone thin film
US20130140685A1 (en) * 2011-12-01 2013-06-06 Infineon Technologies Ag Electronic Device and a Method for Fabricating an Electronic Device
CN103515311A (zh) * 2012-06-27 2014-01-15 英飞凌科技股份有限公司 芯片封装和制造芯片封装的方法
CN106298650A (zh) * 2015-06-29 2017-01-04 意法半导体公司 使用牺牲材料而分离的半导体封装体
CN109075129A (zh) * 2016-05-10 2018-12-21 德州仪器公司 浮动裸片封装
CN108109901A (zh) * 2016-11-25 2018-06-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制作方法

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