CN113191110B

CN113191110B - DDR4 address control line mapping and Ball arrangement method for T-shaped topological structure

Info

Publication number: CN113191110B
Application number: CN202110495221.0A
Authority: CN
Inventors: 梁冬梅
Original assignee: Lusheng Technology Co ltd
Current assignee: Lusheng Technology Co ltd
Priority date: 2021-05-07
Filing date: 2021-05-07
Publication date: 2023-08-11
Anticipated expiration: 2041-05-07
Also published as: CN113191110A

Abstract

The invention provides a DDR4 address control line mapping and Ball arrangement method aiming at a T-shaped topological structure, which meets the requirements of signal quality and time sequence margin. The mapping and arrangement method of the present invention is characterized in that: according to the arrangement of the via holes, the adjacent address/control lines of the via holes are distributed in a group when mapped; i.e. sharing a delay configuration when configuring the DDR controller. The point-to-point signals are allocated in a group corresponding to the same memory. The pins of the DDR controller are arranged, and the arrangement positions of the pins in the same group are adjacent to ensure similar delay. Address/control signals within the same group are routed in the same inner layer. The comprehensive eye diagram is optimal in quality, and the difficulty of winding the PCB by equal length can be reduced while the time sequence margin is maximized. The method has the advantages that the maximization of the address/control line time sequence margin is met while special PCB equal-length processing is not needed, the PCB design is simplified, the wiring area is reduced, and meanwhile, the consistency of the hardware design is ensured.

Description

DDR4 address control line mapping and Ball arrangement method for T-shaped topological structure

Technical Field

The invention relates to the field of system-on-chip (SOC) packaging arrangement and address mapping, in particular to a DDR4 address control line mapping and Ball arrangement method aiming at a T-shaped topological structure.

Background

With the increase of the main frequency of the system, the application of high-definition cameras and more algorithm applications, such as face recognition, mobile phones and intelligent camera systems, have become higher and higher. The DDR memory rate used in the system is also increased, and the number of memories is also increased. With the signal integrity problem caused by the rate improvement, the topology structure of the multiple memories also makes the signal extremely deteriorated, and two address/control topologies commonly used in the industry have advantages and disadvantages:

the T-topology, a scheme commonly used for two-chip memories, is not suitable for multiple chips. The Fly-by structure is mostly used for a multi-chip scheme, the more the number of chips is, the more obvious the signal degradation is, the special design is required for the impedance of the branch and the main line to meet the impedance matching, and meanwhile, the influence of the length of the branch on the speed is obvious. The scheme of the T-shaped topology discussed herein is mostly used for driving two memories simultaneously, and the layout wiring area of the T-shaped structure is smaller than that of the Fly-by structure. The method has the defects that in a high-speed application scene, the delay difference from the bifurcation point of the T-shaped structure to the two memories affects the quality of an eye diagram and establishes the margin of the holding time. In order to ensure that the design meets the requirements of signal quality and timing margin, delay such as branch control is needed, delay difference of a plurality of signal lines in a control group is also needed, and the design requirement on the PCB strictly leads to enlarged wiring area. Meanwhile, the method is easy to neglect, and due to different wiring delays of the unit length of the outer layer and the unit length of the inner layer of the PCB, equal-length wiring can be caused, the actual delays are not consistent, and the requirement of signal quality control is delivered to a customer to have uncontrollable factors.

Disclosure of Invention

The invention provides a DDR4 address control line mapping and Ball arrangement method aiming at a T-shaped topological structure, which meets the requirements of signal quality and time sequence margin.

The technical problems to be solved by the invention are realized by the following technical scheme:

the invention provides a DDR4 address control line mapping and Ball arrangement method aiming at a T-shaped topological structure, which is characterized in that: according to the arrangement of the via holes, the adjacent address/control lines of the via holes are distributed in a group when mapped; i.e. sharing a delay configuration when configuring the DDR controller.

Preferably, the point-to-point signals are allocated within a group corresponding to the same memory.

Preferably, the pins of the DDR controller are arranged, and the arrangement positions of the pins in the same group are adjacent to each other so as to ensure similar delay.

Preferably, address/control signals within the same group are routed in the same inner layer.

The invention has the beneficial effects that: the comprehensive eye diagram is optimal in quality, the difficulty of PCB winding with equal length can be reduced while the maximization of time sequence margin is realized, and the wiring area of the PCB is reduced. The method has the advantages that the maximization of the address/control line time sequence margin is met while special PCB equal-length processing is not needed, the PCB design is simplified, the wiring area is reduced, and meanwhile, the consistency of the hardware design is ensured.

Drawings

FIG. 1 is a DDR4 address control line mapping and Ball alignment method application case for a T-type topology of the present invention;

FIG. 2 is a T-topology for which the DDR4 address control line mapping and Ball alignment method of the present invention is directed.

Detailed Description

The present invention will be described in further detail with reference to the following examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Fig. 1 is a diagram showing an application case of the DDR4 address control line mapping and Ball arrangement method for the T-type topology of the present embodiment. A and B are two address/control signals in the same group, and the delay of each segment is shown in the following chart, and for convenience of discussion, it is assumed that branches after T type are equal, namely T _a3 ＝ta4,t _b3 =tb4. At the receiving end of any one memory, the delay of the address control line satisfies the formula 1. From the previous discussion, the delay of the signals within the same group, network a, network B, will affect the size of the sampling window. For maximum timing margin, |t _A -t _B The i should be less than the delay adjustment step of the controller, or less. To meet this requirement, it is necessary to control |t on the PCB trace _A -t _B | a. The invention relates to a method for producing a fibre-reinforced plastic composite. Because of the fixed location of memory addresses in the JEDEC protocol, t _a3 ,t _b3 It is clear that t _a2 ,t _a3 ,t _b2 ,t _b3 The position of the Ball corresponding to the DDR controller is related, and if the network a and the network B are relatively far away from the DDR controller, delay compensation needs to be performed on the PCB trace to satisfy the delay deviation. Thus, the wiring difficulty and the wiring area of the PCB are increased.

The scheme provided by the invention is from the ball map arrangement and address/control signal mapping scheme, and the optimal timing margin is satisfied without additional PCB wiring compensation.

Equation 1:

t _A ＝t _a1 +t _a2 +t _a3

t _B ＝t _b1 +t _b2 +t _b3

the address Ball location of DDR4 memory, except for individual address signals such as RAS, CAS, BG1, is fixed because of the different number of pages, banks of memory. When a T-shaped mechanism is used, the two memories are in a back-to-back scheme, and the signal fanout mode is relatively fixed.

The principles of address mapping and pin distribution and PCB routing are as follows:

according to the arrangement of the via locations, the adjacent addresses/control lines of the via are allocated in a group when mapped. I.e. sharing a delay configuration when configuring the DDR controller.

The pins of the DDR controller are arranged, and the arrangement positions of the pins in the same group are adjacent to ensure that the delays are similar, and the delay adjustment is satisfied without additional routing with equal length

Address/control signals in the same group are routed in the same inner layer, so that signal delay differences in the same group caused by inconsistent via lengths can be avoided.

CS, ODT, CKE point-to-point signals, corresponding to one group of the same memory group

According to the three principles, the controller address remapping, pin arrangement and PCB wiring can meet the maximization of the address/control line time sequence margin without special PCB equal-length processing, simplify the PCB design, reduce the wiring area and ensure the consistency of hardware design.

The JESD79-4A protocol requires that the timing requirements for the DDR memory address signals meet certain setup hold times at the receiving end of the address signals, i.e., the input end of the memory. In practical applications, the address signal and the clock signal have delay adjustment mechanisms, which can adjust the delay of the clock and the address/control signal, i.e. adjust the signal sampling point, at least within one UI (unit time interval). The signal integrity simulation is no longer concerned with the specific setup hold time, but rather with the effective sampling window of the signal, i.e., the signal eye width. Considering the signal eye width, in addition to the sampling window of the memory itself, DDR controller clock jitter, power-induced signal jitter, and delay differences for the same set of address/control lines are also required.

It should be noted that, in the configuration of the DDR controller, the same group of address/control signals shares a delay configuration, which means that signal lines in the same group need to control delay differences between signal packages and PCBs in the group, which is smaller than a step of delay adjustment, so as to ensure delay adjustment of clocks and address/control signals, and to ensure effective setup and hold time within a minimum signal eye width. To meet the timing requirement, the signals CA1, CA2 in the same group are stepped by an additional delay of t=n. During the adjustment, CA1 and CA2 add additional sampling window requirements due to the fixed existence of delay delta t of the PCB due to the packaging. It is therefore necessary for address/control signal lines to be concerned about the delay difference of a plurality of signal lines within the same delay configuration group, in addition to the eye width.

Fig. 2 is a T-type topology for which the DDR4 address control line mapping and Ball arrangement method for T-type topology of the present embodiment is directed. After the DDR address/control line is routed to the surface layer for fanning out, the DDR address/control line passes through the branch point from the inner layer to the T-shaped structure, and then passes through the top layer and the bottom layer to the two memories respectively from the branch point, wherein the positions of the two memories are opposite. In order to analyze the influence of branching, a T-type topology is modeled in simulation software, the length from a controller to a branching point is fixed to l1=15 mm, the length of a trace from the branching point to a first memory is L2, and the length of a trace from the branching point to a second memory is L3. The following simulation cases adjust for the change in the length eye pattern of L2, L3.

L1=15mm, l2=5mm, l3=3mm, 4mm,5mm,6mm,7mm,8mm,9mm were fixed. From the simulation results, it can be seen that the eye patterns of memory 1 and memory 2 are identical when the lengths of the branches are equal. When the lengths of the branches are not equal, the memory reception eye pattern of the branch short is deteriorated, and as the difference in the branch lengths becomes larger, the eye pattern is further deteriorated. Fixing the eye patterns l1=15mm, l2=l3=5 mm and l2=l3=12 mm, it can be seen that the eye pattern of the signal deteriorates as the absolute length of the branches becomes longer. In practical application, due to crosstalk, as the length of the wiring is longer, crosstalk signal coupling is increased, and the eye diagram of the long branch is more obviously deteriorated.

To analyze the delay impact of vias, modeling was as follows: 6 a stacked layer structure, net a, fans out from the top layer through the vias to the fourth layer and then from the vias to the top layer. Network B fans out from the top layer through vias to the third layer and then through Kong Daoding layers of network. The length of each section is equal, the third layer and the fourth layer are complete, and the wiring length and the time delay are equal. In other words, the delay of the two networks varies, only from top layer to third layer, and from top layer to layer 4.

The delay results are as follows: the difference in via length from top layer to third layer and top layer to layer 4 resulted in a delay of 28.3ps depending on the stack. The adjustment of the address/control lines steps with respect to the delay difference of the tracks, which delay difference is already not negligible. This presents a problem when the thickness of the trace stack, i.e. the via length, is not fixed and the delays per unit length of the outer microstrip line and the inner microstrip line are not uniform in the actual trace. This results in delay control that is difficult to control by the length of the PCB trace. Even looking at equal length traces, the delays are not equal. The delays within the group cannot be known and controlled without simulation. Even the same wiring can lead to different delay introduced by different layers of through holes due to different thicknesses of the PCB, thereby causing inconsistent hardware and uncontrollable customer design scheme.

The above simulations are combined to conclude that: layout of two memories for T-shape

When the branch lengths are equal, the signal quality is the best.

The short branch signal eye degradation is more pronounced when the branch lengths are unequal.

Also, in the case of equal branch lengths, the shorter the branches, the better the branches, the length of which affects the eye width.

If the branch length is too long, or if the difference in trace lengths of the branches is large, the width of the eye pattern and thus the rate of address/control lines may be affected.

The vias introduce additional delay, for example, the same trace, due to the different layers in which the trace is located, signal delay differences within the same set of signals.

The above simulations are based on an evaluation of a single signal line, and in a practical system, eye closure will be more pronounced due to the effects of inter-line crosstalk.

The proposal of the pin arrangement in the invention is to adjust the address/control line mapping scheme of the controller according to the fixed address signal distribution of the DRAM, and control the group delay difference of the same group of address/control lines by using the simplest PCB wiring.

Claims

1. A DDR4 address control line mapping and Ball arrangement method for a T-shaped topological structure is characterized in that: according to the arrangement of the via holes, the adjacent address/control lines of the via holes are distributed in a group when mapped; namely, when the DDR controller is configured, sharing a delay configuration; the pins of the DDR controller are arranged, and the arrangement positions of the pins in the same group are adjacent to ensure that the delays are similar, and the delay adjustment is satisfied without additional routing with equal length; address/control signals in the same group are routed in the same inner layer, so that signal delay difference in the same group, which is caused by inconsistent via lengths, can be avoided; the point-to-point signals correspond to the same memory group; and satisfies the formula:

t _A ＝t _a1 +t _a2 +t _a3

t _B ＝t _b1 +t _b2 +t _b3 。